From: guoren@kernel.org To: guoren@kernel.org, palmer@dabbelt.com, arnd@arndb.de, anup.patel@wdc.com, gregkh@linuxfoundation.org, liush@allwinnertech.com, wefu@redhat.com, drew@beagleboard.org, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com> Subject: [PATCH 06/13] riscv: compat: syscall: Add entry.S implementation Date: Wed, 22 Dec 2021 00:35:25 +0800 [thread overview] Message-ID: <20211221163532.2636028-7-guoren@kernel.org> (raw) In-Reply-To: <20211221163532.2636028-1-guoren@kernel.org> From: Guo Ren <guoren@linux.alibaba.com> Implement the entry of compat_sys_call_table[] in asm. Ref to riscv-privileged spec 4.1.1 Supervisor Status Register (sstatus): BIT[32:33] = UXL[1:0]: - 1:32 - 2:64 - 3:128 Signed-off-by: Guo Ren <guoren@linux.alibaba.com> --- arch/riscv/include/asm/csr.h | 7 +++++++ arch/riscv/kernel/entry.S | 18 ++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 5046f431645c..7dac12366833 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -36,6 +36,13 @@ #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ #endif +#ifdef CONFIG_COMPAT +#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ +#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ +#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ +#define SR_UXL_SHIFT 32 +#endif + /* SATP flags */ #ifndef CONFIG_64BIT #define SATP_PPN _AC(0x003FFFFF, UL) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index ed29e9c8f660..1951743f09b3 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -207,13 +207,27 @@ check_syscall_nr: * Syscall number held in a7. * If syscall number is above allowed value, redirect to ni_syscall. */ - bgeu a7, t0, 1f + bgeu a7, t0, 3f +#ifdef CONFIG_COMPAT + REG_L s0, PT_STATUS(sp) + srli s0, s0, SR_UXL_SHIFT + andi s0, s0, (SR_UXL >> SR_UXL_SHIFT) + li t0, (SR_UXL_32 >> SR_UXL_SHIFT) + sub t0, s0, t0 + bnez t0, 1f + + /* Call compat_syscall */ + la s0, compat_sys_call_table + j 2f +1: +#endif /* Call syscall */ la s0, sys_call_table +2: slli t0, a7, RISCV_LGPTR add s0, s0, t0 REG_L s0, 0(s0) -1: +3: jalr s0 ret_from_syscall: -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org To: guoren@kernel.org, palmer@dabbelt.com, arnd@arndb.de, anup.patel@wdc.com, gregkh@linuxfoundation.org, liush@allwinnertech.com, wefu@redhat.com, drew@beagleboard.org, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com> Subject: [PATCH 06/13] riscv: compat: syscall: Add entry.S implementation Date: Wed, 22 Dec 2021 00:35:25 +0800 [thread overview] Message-ID: <20211221163532.2636028-7-guoren@kernel.org> (raw) In-Reply-To: <20211221163532.2636028-1-guoren@kernel.org> From: Guo Ren <guoren@linux.alibaba.com> Implement the entry of compat_sys_call_table[] in asm. Ref to riscv-privileged spec 4.1.1 Supervisor Status Register (sstatus): BIT[32:33] = UXL[1:0]: - 1:32 - 2:64 - 3:128 Signed-off-by: Guo Ren <guoren@linux.alibaba.com> --- arch/riscv/include/asm/csr.h | 7 +++++++ arch/riscv/kernel/entry.S | 18 ++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 5046f431645c..7dac12366833 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -36,6 +36,13 @@ #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ #endif +#ifdef CONFIG_COMPAT +#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ +#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ +#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ +#define SR_UXL_SHIFT 32 +#endif + /* SATP flags */ #ifndef CONFIG_64BIT #define SATP_PPN _AC(0x003FFFFF, UL) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index ed29e9c8f660..1951743f09b3 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -207,13 +207,27 @@ check_syscall_nr: * Syscall number held in a7. * If syscall number is above allowed value, redirect to ni_syscall. */ - bgeu a7, t0, 1f + bgeu a7, t0, 3f +#ifdef CONFIG_COMPAT + REG_L s0, PT_STATUS(sp) + srli s0, s0, SR_UXL_SHIFT + andi s0, s0, (SR_UXL >> SR_UXL_SHIFT) + li t0, (SR_UXL_32 >> SR_UXL_SHIFT) + sub t0, s0, t0 + bnez t0, 1f + + /* Call compat_syscall */ + la s0, compat_sys_call_table + j 2f +1: +#endif /* Call syscall */ la s0, sys_call_table +2: slli t0, a7, RISCV_LGPTR add s0, s0, t0 REG_L s0, 0(s0) -1: +3: jalr s0 ret_from_syscall: -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-12-21 16:36 UTC|newest] Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-21 16:35 [PATCH 00/13] riscv: compat: Add COMPAT mode support for rv64 guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 01/13] syscalls: compat: Fix the missing part for __SYSCALL_COMPAT guoren 2021-12-21 16:35 ` guoren 2021-12-21 17:08 ` Arnd Bergmann 2021-12-21 17:08 ` Arnd Bergmann 2021-12-22 11:16 ` Guo Ren 2021-12-22 11:16 ` Guo Ren 2021-12-22 11:24 ` Arnd Bergmann 2021-12-22 11:24 ` Arnd Bergmann 2021-12-24 6:52 ` Christoph Hellwig 2021-12-24 6:52 ` Christoph Hellwig 2021-12-21 16:35 ` [PATCH 02/13] riscv: Fixup difference with defconfig guoren 2021-12-21 16:35 ` guoren 2021-12-21 17:09 ` Arnd Bergmann 2021-12-21 17:09 ` Arnd Bergmann 2021-12-22 11:34 ` Guo Ren 2021-12-22 11:34 ` Guo Ren 2021-12-22 11:44 ` Arnd Bergmann 2021-12-22 11:44 ` Arnd Bergmann 2021-12-22 13:06 ` Guo Ren 2021-12-22 13:06 ` Guo Ren 2021-12-22 13:30 ` Arnd Bergmann 2021-12-22 13:30 ` Arnd Bergmann 2021-12-23 2:12 ` Guo Ren 2021-12-23 2:12 ` Guo Ren 2021-12-21 16:35 ` [PATCH 03/13] riscv: compat: Add basic compat date type implementation guoren 2021-12-21 16:35 ` guoren 2021-12-21 17:12 ` Arnd Bergmann 2021-12-21 17:12 ` Arnd Bergmann 2021-12-22 12:03 ` Guo Ren 2021-12-22 12:03 ` Guo Ren 2021-12-22 12:46 ` Arnd Bergmann 2021-12-22 12:46 ` Arnd Bergmann 2021-12-26 15:33 ` Guo Ren 2021-12-26 15:33 ` Guo Ren 2021-12-24 6:53 ` Christoph Hellwig 2021-12-24 6:53 ` Christoph Hellwig 2021-12-24 9:28 ` Guo Ren 2021-12-24 9:28 ` Guo Ren 2021-12-21 16:35 ` [PATCH 04/13] riscv: compat: Re-implement TASK_SIZE for COMPAT_32BIT guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 05/13] riscv: compat: syscall: Add compat_sys_call_table implementation guoren 2021-12-21 16:35 ` guoren 2021-12-21 17:15 ` Arnd Bergmann 2021-12-21 17:15 ` Arnd Bergmann 2021-12-22 12:43 ` Guo Ren 2021-12-22 12:43 ` Guo Ren 2021-12-22 13:21 ` Arnd Bergmann 2021-12-22 13:21 ` Arnd Bergmann 2021-12-22 14:00 ` Arnd Bergmann 2021-12-22 14:00 ` Arnd Bergmann 2021-12-24 9:42 ` Guo Ren 2021-12-24 9:42 ` Guo Ren 2021-12-21 16:35 ` guoren [this message] 2021-12-21 16:35 ` [PATCH 06/13] riscv: compat: syscall: Add entry.S implementation guoren 2021-12-21 16:35 ` [PATCH 07/13] riscv: compat: Add elf.h implementation guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 08/13] riscv: compat: Add COMPAT Kbuild skeletal support guoren 2021-12-21 16:35 ` guoren 2021-12-21 17:21 ` Arnd Bergmann 2021-12-21 17:21 ` Arnd Bergmann 2021-12-22 12:06 ` Guo Ren 2021-12-22 12:06 ` Guo Ren 2021-12-24 6:54 ` Christoph Hellwig 2021-12-24 6:54 ` Christoph Hellwig 2021-12-21 16:35 ` [PATCH 09/13] riscv: compat: init: Add hw-cap detect in setup_arch guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 10/13] riscv: compat: vdso: Add rv32 VDSO base code implementation guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 11/13] riscv: compat: vdso: Add setup additional pages implementation guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 12/13] riscv: compat: signal: Add rt_frame implementation guoren 2021-12-21 16:35 ` guoren 2021-12-21 16:35 ` [PATCH 13/13] riscv: compat: ptrace: Add compat_arch_ptrace implement guoren 2021-12-21 16:35 ` guoren 2021-12-21 17:38 ` [PATCH 00/13] riscv: compat: Add COMPAT mode support for rv64 Arnd Bergmann 2021-12-21 17:38 ` Arnd Bergmann 2021-12-22 12:59 ` Guo Ren 2021-12-22 12:59 ` Guo Ren 2021-12-22 13:29 ` Arnd Bergmann 2021-12-22 13:29 ` Arnd Bergmann 2021-12-26 8:22 ` Jisheng Zhang 2021-12-26 8:22 ` Jisheng Zhang 2021-12-26 12:38 ` Guo Ren 2021-12-26 12:38 ` Guo Ren 2021-12-26 20:31 ` Arnd Bergmann 2021-12-26 20:31 ` Arnd Bergmann 2021-12-27 1:16 ` Guo Ren 2021-12-27 1:16 ` Guo Ren 2021-12-27 2:29 ` Jessica Clarke 2021-12-27 2:29 ` Jessica Clarke 2021-12-28 10:45 ` Guo Ren 2021-12-28 10:45 ` Guo Ren 2021-12-22 12:00 ` Guo Ren 2021-12-22 12:00 ` Guo Ren
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