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* [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
@ 2021-12-21 22:48 ` Richard Schleich
  0 siblings, 0 replies; 6+ messages in thread
From: Richard Schleich @ 2021-12-21 22:48 UTC (permalink / raw)
  To: robh+dt, nsaenz, f.fainelli, bcm-kernel-feedback-list,
	devicetree, linux-rpi-kernel, linux-arm-kernel
  Cc: Richard Schleich

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2711 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
---
 arch/arm/boot/dts/bcm2711.dtsi | 50 ++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 9e01dbca4a01..b2f403fc420c 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -458,12 +458,26 @@
 		#size-cells = <0>;
 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+		/* Source for d/i-cache-line-size and d/i-cache-sets
+		 *  https://developer.arm.com/documentation/100095/0003
+		 *  /Level-1-Memory-System/About-the-L1-memory-system?lang=en
+		 * Source for d/i-cache-size
+		 *  https://www.raspberrypi.com/documentation/computers
+		 *  /processors.html#bcm2711
+		 */
 		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72";
 			reg = <0>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000d8>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu1: cpu@1 {
@@ -472,6 +486,13 @@
 			reg = <1>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e0>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu2: cpu@2 {
@@ -480,6 +501,13 @@
 			reg = <2>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e8>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu3: cpu@3 {
@@ -488,6 +516,28 @@
 			reg = <3>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000f0>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			/* Source for d/i-cache-line-size and d/i-cache-sets
+			 *  https://developer.arm.com/documentation/100095/0003
+			 *  /Level-2-Memory-System/About-the-L2-memory-system?lang=en
+			 *  Source for d/i-cache-size
+			 *  https://www.raspberrypi.com/documentation/computers
+			 *  /processors.html#bcm2711
+			 */
+			compatible = "cache";
+			cache-size = <0x100000>; // 1MB
+			cache-line-size = <64>; // Fixed line length of 64 bytes
+			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16000ways/16-way set
+			cache-level = <2>;
 		};
 	};
 
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
@ 2021-12-21 22:48 ` Richard Schleich
  0 siblings, 0 replies; 6+ messages in thread
From: Richard Schleich @ 2021-12-21 22:48 UTC (permalink / raw)
  To: robh+dt, nsaenz, f.fainelli, bcm-kernel-feedback-list,
	devicetree, linux-rpi-kernel, linux-arm-kernel
  Cc: Richard Schleich

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2711 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
---
 arch/arm/boot/dts/bcm2711.dtsi | 50 ++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 9e01dbca4a01..b2f403fc420c 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -458,12 +458,26 @@
 		#size-cells = <0>;
 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+		/* Source for d/i-cache-line-size and d/i-cache-sets
+		 *  https://developer.arm.com/documentation/100095/0003
+		 *  /Level-1-Memory-System/About-the-L1-memory-system?lang=en
+		 * Source for d/i-cache-size
+		 *  https://www.raspberrypi.com/documentation/computers
+		 *  /processors.html#bcm2711
+		 */
 		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72";
 			reg = <0>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000d8>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu1: cpu@1 {
@@ -472,6 +486,13 @@
 			reg = <1>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e0>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu2: cpu@2 {
@@ -480,6 +501,13 @@
 			reg = <2>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e8>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu3: cpu@3 {
@@ -488,6 +516,28 @@
 			reg = <3>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000f0>;
+			d-cache-size = <0x8000>; // 32KB 2-way set-associative data cache
+			d-cache-line-size = <64>;// Fixed line length of 64 bytes
+			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			i-cache-size = <0xc000>; // 48kB 3-way set-associative data cache
+			i-cache-line-size = <64>;// Fixed line length of 64 bytes
+			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			/* Source for d/i-cache-line-size and d/i-cache-sets
+			 *  https://developer.arm.com/documentation/100095/0003
+			 *  /Level-2-Memory-System/About-the-L2-memory-system?lang=en
+			 *  Source for d/i-cache-size
+			 *  https://www.raspberrypi.com/documentation/computers
+			 *  /processors.html#bcm2711
+			 */
+			compatible = "cache";
+			cache-size = <0x100000>; // 1MB
+			cache-line-size = <64>; // Fixed line length of 64 bytes
+			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16000ways/16-way set
+			cache-level = <2>;
 		};
 	};
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
  2021-12-21 22:48 ` Richard Schleich
@ 2021-12-28 16:30   ` Stefan Wahren
  -1 siblings, 0 replies; 6+ messages in thread
From: Stefan Wahren @ 2021-12-28 16:30 UTC (permalink / raw)
  To: Richard Schleich, robh+dt, nsaenz, f.fainelli,
	bcm-kernel-feedback-list, devicetree, linux-rpi-kernel,
	linux-arm-kernel

Am 21.12.21 um 23:48 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>

Tested-by: Stefan Wahren <stefan.wahren@i2se.com>

I tested the patch with a Raspberry Pi 4 (arm64/defconfig) and here are
some outputs:

/sys/devices/system/cpu/cpu0/cache

./index2/number_of_sets:1024
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:1024K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:256
./index0/ways_of_associativity:2
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:3
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:48K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1

lscpu

Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              4
On-line CPU(s) list: 0-3
Thread(s) per core:  1
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Vendor ID:           ARM
Model:               3
Model name:          Cortex-A72
Stepping:            r0p3
CPU max MHz:         1500,0000
CPU min MHz:         600,0000
BogoMIPS:            108.00
L1d cache:           32K
L1i cache:           48K
L2 cache:            1024K
NUMA node0 CPU(s):   0-3
Flags:               fp asimd evtstrm crc32 cpuid


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
@ 2021-12-28 16:30   ` Stefan Wahren
  0 siblings, 0 replies; 6+ messages in thread
From: Stefan Wahren @ 2021-12-28 16:30 UTC (permalink / raw)
  To: Richard Schleich, robh+dt, nsaenz, f.fainelli,
	bcm-kernel-feedback-list, devicetree, linux-rpi-kernel,
	linux-arm-kernel

Am 21.12.21 um 23:48 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
>
> Signed-off-by: Richard Schleich <rs@noreya.tech>

Tested-by: Stefan Wahren <stefan.wahren@i2se.com>

I tested the patch with a Raspberry Pi 4 (arm64/defconfig) and here are
some outputs:

/sys/devices/system/cpu/cpu0/cache

./index2/number_of_sets:1024
./index2/ways_of_associativity:16
./index2/shared_cpu_list:0-3
./index2/type:Unified
./index2/size:1024K
./index2/level:2
./index2/coherency_line_size:64
./index2/shared_cpu_map:f
./index0/number_of_sets:256
./index0/ways_of_associativity:2
./index0/shared_cpu_list:0
./index0/type:Data
./index0/size:32K
./index0/level:1
./index0/coherency_line_size:64
./index0/shared_cpu_map:1
./index1/number_of_sets:256
./index1/ways_of_associativity:3
./index1/shared_cpu_list:0
./index1/type:Instruction
./index1/size:48K
./index1/level:1
./index1/coherency_line_size:64
./index1/shared_cpu_map:1

lscpu

Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              4
On-line CPU(s) list: 0-3
Thread(s) per core:  1
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Vendor ID:           ARM
Model:               3
Model name:          Cortex-A72
Stepping:            r0p3
CPU max MHz:         1500,0000
CPU min MHz:         600,0000
BogoMIPS:            108.00
L1d cache:           32K
L1i cache:           48K
L2 cache:            1024K
NUMA node0 CPU(s):   0-3
Flags:               fp asimd evtstrm crc32 cpuid


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
  2021-12-21 22:48 ` Richard Schleich
@ 2022-02-01  0:36   ` Florian Fainelli
  -1 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2022-02-01  0:36 UTC (permalink / raw)
  To: Richard Schleich, robh+dt, nsaenz, bcm-kernel-feedback-list,
	devicetree, linux-rpi-kernel, linux-arm-kernel



On 12/21/2021 2:48 PM, Richard Schleich wrote:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
> 
> Signed-off-by: Richard Schleich <rs@noreya.tech>

Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, 
thanks!

I did remove the comments that were not helpful for the 'd-cache-size', 
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size'  since they 
are self explanatory.
-- 
Florian

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information
@ 2022-02-01  0:36   ` Florian Fainelli
  0 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2022-02-01  0:36 UTC (permalink / raw)
  To: Richard Schleich, robh+dt, nsaenz, bcm-kernel-feedback-list,
	devicetree, linux-rpi-kernel, linux-arm-kernel



On 12/21/2021 2:48 PM, Richard Schleich wrote:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
> 
> Signed-off-by: Richard Schleich <rs@noreya.tech>

Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, 
thanks!

I did remove the comments that were not helpful for the 'd-cache-size', 
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size'  since they 
are self explanatory.
-- 
Florian

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-01  0:38 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-21 22:48 [PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information Richard Schleich
2021-12-21 22:48 ` Richard Schleich
2021-12-28 16:30 ` Stefan Wahren
2021-12-28 16:30   ` Stefan Wahren
2022-02-01  0:36 ` Florian Fainelli
2022-02-01  0:36   ` Florian Fainelli

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