* [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
@ 2021-12-20 13:31 Lad Prabhakar
2021-12-20 13:31 ` [PATCH 5.10.y-cip 01/22] mm: slab: provide krealloc_array() Lad Prabhakar
` (23 more replies)
0 siblings, 24 replies; 36+ messages in thread
From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
Hi All,
This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
All the patches have been cherry picked from v5.16-rc5.
I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
[0] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/merge_requests/53
Cheers,
Prabhakar
Bartosz Golaszewski (1):
mm: slab: provide krealloc_array()
Biju Das (11):
pinctrl: renesas: rzg2l: Fix missing port register 21h
clk: renesas: r9a07g044: Add I2C clocks/resets
dt-bindings: i2c: renesas,riic: Document RZ/G2L I2C controller
arm64: dts: renesas: r9a07g044: Add I2C nodes
clk: renesas: r9a07g044: Add DMAC clocks/resets
dt-bindings: dma: Document RZ/G2L bindings
dmaengine: Extend the dma_slave_width for 128 bytes
dmaengine: sh: Add DMAC driver for RZ/G2L SoC
dmaengine: sh: rz-dmac: Add DMA clock handling
arm64: dts: renesas: r9a07g044: Add DMAC support
arm64: defconfig: Enable RZ_DMAC
Colin Ian King (2):
dmaengine: sh: Fix unused initialization of pointer lmdesc
dmaengine: sh: make array ds_lut static
Dan Carpenter (1):
dmaengine: sh: fix some NULL dereferences
Geert Uytterhoeven (2):
dt-bindings: i2c: renesas,riic: Convert to json-schema
arm64: dts: renesas: r9a07g044: Add I2C interrupt-names
Lad Prabhakar (5):
clk: renesas: r9a07g044: Add GPIO clock and reset entries
dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl
pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
arm64: dts: renesas: rzg2l-smarc: Add scif0 pins
arm64: dts: renesas: r9a07g044: Add pinctrl node
Documentation/core-api/memory-allocation.rst | 4 +
.../bindings/dma/renesas,rz-dmac.yaml | 130 ++
.../devicetree/bindings/i2c/renesas,riic.txt | 32 -
.../devicetree/bindings/i2c/renesas,riic.yaml | 93 ++
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 155 +++
MAINTAINERS | 2 +-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 137 ++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 25 +
drivers/dma/sh/Kconfig | 9 +
drivers/dma/sh/Makefile | 1 +
drivers/dma/sh/rz-dmac.c | 983 ++++++++++++++
drivers/pinctrl/renesas/Kconfig | 11 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1175 +++++++++++++++++
include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 +
include/linux/dmaengine.h | 3 +-
include/linux/slab.h | 18 +
19 files changed, 2779 insertions(+), 34 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
delete mode 100644 Documentation/devicetree/bindings/i2c/renesas,riic.txt
create mode 100644 Documentation/devicetree/bindings/i2c/renesas,riic.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
create mode 100644 drivers/dma/sh/rz-dmac.c
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c
create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h
--
2.17.1
^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 5.10.y-cip 01/22] mm: slab: provide krealloc_array() 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 02/22] clk: renesas: r9a07g044: Add GPIO clock and reset entries Lad Prabhakar ` (22 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Bartosz Golaszewski <bgolaszewski@baylibre.com> commit f0dbd2bd1c22c6670e83ddcd46a9beb8b575e86d upstream. When allocating an array of elements, users should check for multiplication overflow or preferably use one of the provided helpers like: kmalloc_array(). There's no krealloc_array() counterpart but there are many users who use regular krealloc() to reallocate arrays. Let's provide an actual krealloc_array() implementation. While at it: add some documentation regarding krealloc. Link: https://lkml.kernel.org/r/20201109110654.12547-3-brgl@bgdev.pl Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Vlastimil Babka <vbabka@suse.cz> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Borislav Petkov <bp@suse.de> Cc: Christian Knig <christian.koenig@amd.com> Cc: Christoph Lameter <cl@linux.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: David Airlie <airlied@linux.ie> Cc: David Rientjes <rientjes@google.com> Cc: Gustavo Padovan <gustavo@padovan.org> Cc: James Morse <james.morse@arm.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Jason Wang <jasowang@redhat.com> Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Maxime Ripard <mripard@kernel.org> Cc: "Michael S . Tsirkin" <mst@redhat.com> Cc: Pekka Enberg <penberg@kernel.org> Cc: Robert Richter <rric@kernel.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Takashi Iwai <tiwai@suse.com> Cc: Takashi Iwai <tiwai@suse.de> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- Documentation/core-api/memory-allocation.rst | 4 ++++ include/linux/slab.h | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/Documentation/core-api/memory-allocation.rst b/Documentation/core-api/memory-allocation.rst index 4446a1ac36cc..5954ddf6ee13 100644 --- a/Documentation/core-api/memory-allocation.rst +++ b/Documentation/core-api/memory-allocation.rst @@ -147,6 +147,10 @@ The address of a chunk allocated with `kmalloc` is aligned to at least ARCH_KMALLOC_MINALIGN bytes. For sizes which are a power of two, the alignment is also guaranteed to be at least the respective size. +Chunks allocated with kmalloc() can be resized with krealloc(). Similarly +to kmalloc_array(): a helper for resizing arrays is provided in the form of +krealloc_array(). + For large allocations you can use vmalloc() and vzalloc(), or directly request pages from the page allocator. The memory allocated by `vmalloc` and related functions is not physically contiguous. diff --git a/include/linux/slab.h b/include/linux/slab.h index dd6897f62010..be4ba5867ac5 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -592,6 +592,24 @@ static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) return __kmalloc(bytes, flags); } +/** + * krealloc_array - reallocate memory for an array. + * @p: pointer to the memory chunk to reallocate + * @new_n: new number of elements to alloc + * @new_size: new size of a single member of the array + * @flags: the type of memory to allocate (see kmalloc) + */ +static __must_check inline void * +krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) +{ + size_t bytes; + + if (unlikely(check_mul_overflow(new_n, new_size, &bytes))) + return NULL; + + return krealloc(p, bytes, flags); +} + /** * kcalloc - allocate memory for an array. The memory is set to zero. * @n: number of elements. -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 02/22] clk: renesas: r9a07g044: Add GPIO clock and reset entries 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 01/22] mm: slab: provide krealloc_array() Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl Lad Prabhakar ` (21 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das commit d85b82f09a03c2e1f06da740c6c47dd098b16ca5 upstream. Add GPIO clock and reset entries in CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210712194422.12405-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index fb8e199c7409..ad3bc21d26c1 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -102,6 +102,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x584, 4), DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 0x588, 0), + DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, + 0x598, 0), }; static struct rzg2l_reset r9a07g044_resets[] = { @@ -114,6 +116,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), + DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), }; static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 01/22] mm: slab: provide krealloc_array() Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 02/22] clk: renesas: r9a07g044: Add GPIO clock and reset entries Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-22 9:45 ` Pavel Machek 2021-12-20 13:31 ` [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Lad Prabhakar ` (20 subsequent siblings) 23 siblings, 1 reply; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das commit 7958f88aa6636f1927513c887a00e83168f12e35 upstream. Add device tree binding documentation and header file for Renesas RZ/G2L pinctrl. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210727112328.18809-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 155 ++++++++++++++++++ include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 +++ 2 files changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml new file mode 100644 index 000000000000..ef68dabcf4dc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L combined Pin and GPIO controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + controller. + Pin multiplexing and GPIO configuration is performed on a per-pin basis. + Each port features up to 8 pins, each of them configurable for GPIO function + (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the + second cell represents consumer flag as mentioned in ../gpio/gpio.txt + E.g. "RZG2L_GPIO(39, 1)" for P39_1. + + gpio-ranges: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + items: + - description: GPIO_RSTN signal + - description: GPIO_PORT_RESETN signal + - description: GPIO_SPARE_RESETN signal + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + phandle: true + pinmux: + description: + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZG2L_PORT_PINMUX() + helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>. + pins: true + drive-strength: + enum: [ 2, 4, 8, 12 ] + power-source: + enum: [ 1800, 2500, 3300 ] + slew-rate: true + gpio-hog: true + gpios: true + input-enable: true + output-high: true + output-low: true + line-name: true + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - clocks + - power-domains + - resets + +examples: + - | + #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + #include <dt-bindings/clock/r9a07g044-cpg.h> + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g044-pinctrl"; + reg = <0x11030000 0x10000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; + resets = <&cpg R9A07G044_GPIO_RSTN>, + <&cpg R9A07G044_GPIO_PORT_RESETN>, + <&cpg R9A07G044_GPIO_SPARE_RESETN>; + power-domains = <&cpg>; + + scif0_pins: serial0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */ + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(39, 2) 0>; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_mux { + pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */ + <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */ + power-source = <3300>; + }; + + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h new file mode 100644 index 000000000000..b48f8c7a5556 --- /dev/null +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family pinctrl bindings. + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZG2L_PINCTRL_H +#define __DT_BINDINGS_RZG2L_PINCTRL_H + +#define RZG2L_PINS_PER_PORT 8 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ + #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl 2021-12-20 13:31 ` [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl Lad Prabhakar @ 2021-12-22 9:45 ` Pavel Machek 2021-12-22 11:05 ` Prabhakar Mahadev Lad 0 siblings, 1 reply; 36+ messages in thread From: Pavel Machek @ 2021-12-22 9:45 UTC (permalink / raw) To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das [-- Attachment #1: Type: text/plain, Size: 672 bytes --] Hi! > commit 7958f88aa6636f1927513c887a00e83168f12e35 upstream. > > Add device tree binding documentation and header file for Renesas > RZ/G2L pinctrl. > > + drive-strength: > + enum: [ 2, 4, 8, 12 ] > + power-source: > + enum: [ 1800, 2500, 3300 ] These are likely milliamps and millivolts, right? Elsewhere in device trees microvolts and microamps are used, so that is not too consistent. Is the unit mentioned somewhere / should it be? Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl 2021-12-22 9:45 ` Pavel Machek @ 2021-12-22 11:05 ` Prabhakar Mahadev Lad 0 siblings, 0 replies; 36+ messages in thread From: Prabhakar Mahadev Lad @ 2021-12-22 11:05 UTC (permalink / raw) To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das Hi Pavel, Thank you for the review. > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: 22 December 2021 09:46 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L > pinctrl > > Hi! > > > commit 7958f88aa6636f1927513c887a00e83168f12e35 upstream. > > > > Add device tree binding documentation and header file for Renesas > > RZ/G2L pinctrl. > > > > + drive-strength: > > + enum: [ 2, 4, 8, 12 ] > > + power-source: > > + enum: [ 1800, 2500, 3300 ] > > These are likely milliamps and millivolts, right? Elsewhere in device trees microvolts and microamps > are used, so that is not too consistent. > Its in millivolts in our case. > Is the unit mentioned somewhere / should it be? > I can update the renesas,rzg2l-pinctrl.yaml binding do to add a description and state the values are in millivolts. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (2 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-22 9:48 ` Pavel Machek 2021-12-20 13:31 ` [PATCH 5.10.y-cip 05/22] pinctrl: renesas: rzg2l: Fix missing port register 21h Lad Prabhakar ` (19 subsequent siblings) 23 siblings, 1 reply; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das commit c4c4637eb57f2a25c445421aadeb689a2538b20b upstream. Add support for pin and gpio controller driver for RZ/G2L SoC. Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727112328.18809-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [PL: manually applied changes to Kconfig file] Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/Kconfig | 11 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1175 +++++++++++++++++++++++ 3 files changed, 1187 insertions(+) create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index e941b8440dbc..356a70739689 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -36,6 +36,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77980 if ARCH_R8A77980 select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 + select PINCTRL_RZG2L if ARCH_R9A07G044 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 @@ -171,6 +172,16 @@ config PINCTRL_RZA2 help This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. +config PINCTRL_RZG2L + bool "pin control support for RZ/G2L" if COMPILE_TEST + depends on OF + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms. + config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST select PINCTRL_SH_PFC diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 1f6d7dd019d8..4580a2968a33 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o +obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o ifeq ($(CONFIG_COMPILE_TEST),y) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c new file mode 100644 index 000000000000..dbf2f521bb27 --- /dev/null +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -0,0 +1,1175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L Pin Control and GPIO driver core + * + * Copyright (C) 2021 Renesas Electronics Corporation. + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/gpio/driver.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/spinlock.h> + +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define DRV_NAME "pinctrl-rzg2l" + +/* + * Use 16 lower bits [15:0] for pin identifier + * Use 16 higher bits [31:16] for pin mux function + */ +#define MUX_PIN_ID_MASK GENMASK(15, 0) +#define MUX_FUNC_MASK GENMASK(31, 16) +#define MUX_FUNC_OFFS 16 +#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) + +/* PIN capabilities */ +#define PIN_CFG_IOLH BIT(0) +#define PIN_CFG_SR BIT(1) +#define PIN_CFG_IEN BIT(2) +#define PIN_CFG_PUPD BIT(3) +#define PIN_CFG_IOLH_SD0 BIT(4) +#define PIN_CFG_IOLH_SD1 BIT(5) +#define PIN_CFG_IOLH_QSPI BIT(6) +#define PIN_CFG_IOLH_ETH0 BIT(7) +#define PIN_CFG_IOLH_ETH1 BIT(8) +#define PIN_CFG_FILONOFF BIT(9) +#define PIN_CFG_FILNUM BIT(10) +#define PIN_CFG_FILCLKSEL BIT(11) + +#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \ + PIN_CFG_SR | \ + PIN_CFG_PUPD | \ + PIN_CFG_FILONOFF | \ + PIN_CFG_FILNUM | \ + PIN_CFG_FILCLKSEL) + +#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ + PIN_CFG_FILONOFF | \ + PIN_CFG_FILNUM | \ + PIN_CFG_FILCLKSEL) + +/* + * n indicates number of pins in the port, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) +#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) + +/* + * BIT(31) indicates dedicated pin, p is the register index while + * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits + * (b * 8) and f is the pin configuration capabilities supported. + */ +#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ + ((p) << 24) | ((b) << 20) | (f)) +#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) & GENMASK(30, 24)) >> 24) +#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) +#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) + +#define P(n) (0x0000 + 0x10 + (n)) +#define PM(n) (0x0100 + 0x20 + (n) * 2) +#define PMC(n) (0x0200 + 0x10 + (n)) +#define PFC(n) (0x0400 + 0x40 + (n) * 4) +#define PIN(n) (0x0800 + 0x10 + (n)) +#define IEN(n) (0x1800 + (n) * 8) +#define PWPR (0x3014) +#define SD_CH(n) (0x3000 + (n) * 4) +#define QSPI (0x3008) + +#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ + +#define PWPR_B0WI BIT(7) /* Bit Write Disable */ +#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ + +#define PM_MASK 0x03 +#define PVDD_MASK 0x01 +#define PFC_MASK 0x07 +#define IEN_MASK 0x01 + +#define PM_INPUT 0x1 +#define PM_OUTPUT 0x2 + +#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) +#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) + +struct rzg2l_dedicated_configs { + const char *name; + u32 config; +}; + +struct rzg2l_pinctrl_data { + const char * const *port_pins; + const u32 *port_pin_configs; + struct rzg2l_dedicated_configs *dedicated_pins; + unsigned int n_port_pins; + unsigned int n_dedicated_pins; +}; + +struct rzg2l_pinctrl { + struct pinctrl_dev *pctl; + struct pinctrl_desc desc; + struct pinctrl_pin_desc *pins; + + const struct rzg2l_pinctrl_data *data; + void __iomem *base; + struct device *dev; + struct clk *clk; + + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range gpio_range; + + spinlock_t lock; +}; + +static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, + u8 port, u8 pin, u8 func) +{ + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* Set pin to 'Non-use (Hi-Z input protection)' */ + reg = readw(pctrl->base + PM(port)); + reg &= ~(PM_MASK << (pin * 2)); + writew(reg, pctrl->base + PM(port)); + + /* Temporarily switch to GPIO mode with PMC register */ + reg = readb(pctrl->base + PMC(port)); + writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); + + /* Set the PWPR register to allow PFC register to write */ + writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ + writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ + + /* Select Pin function mode with PFC register */ + reg = readl(pctrl->base + PFC(port)); + reg &= ~(PFC_MASK << (pin * 4)); + writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); + + /* Set the PWPR register to be write-protected */ + writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ + writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ + + /* Switch to Peripheral pin function with PMC register */ + reg = readb(pctrl->base + PMC(port)); + writeb(reg | BIT(pin), pctrl->base + PMC(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); +}; + +static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct function_desc *func; + unsigned int i, *psel_val; + struct group_desc *group; + int *pins; + + func = pinmux_generic_get_function(pctldev, func_selector); + if (!func) + return -EINVAL; + group = pinctrl_generic_get_group(pctldev, group_selector); + if (!group) + return -EINVAL; + + psel_val = func->data; + pins = group->pins; + + for (i = 0; i < group->num_pins; i++) { + dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", + RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), + psel_val[i]); + rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), + RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); + } + + return 0; +}; + +static int rzg2l_map_add_config(struct pinctrl_map *map, + const char *group_or_pin, + enum pinctrl_map_type type, + unsigned long *configs, + unsigned int num_configs) +{ + unsigned long *cfgs; + + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), + GFP_KERNEL); + if (!cfgs) + return -ENOMEM; + + map->type = type; + map->data.configs.group_or_pin = group_or_pin; + map->data.configs.configs = cfgs; + map->data.configs.num_configs = num_configs; + + return 0; +} + +static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps, + unsigned int *index) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct pinctrl_map *maps = *map; + unsigned int nmaps = *num_maps; + unsigned long *configs = NULL; + unsigned int *pins, *psel_val; + unsigned int num_pinmux = 0; + unsigned int idx = *index; + unsigned int num_pins, i; + unsigned int num_configs; + struct property *pinmux; + struct property *prop; + int ret, gsel, fsel; + const char **pin_fn; + const char *pin; + + pinmux = of_find_property(np, "pinmux", NULL); + if (pinmux) + num_pinmux = pinmux->length / sizeof(u32); + + ret = of_property_count_strings(np, "pins"); + if (ret == -EINVAL) { + num_pins = 0; + } else if (ret < 0) { + dev_err(pctrl->dev, "Invalid pins list in DT\n"); + return ret; + } else { + num_pins = ret; + } + + if (!num_pinmux && !num_pins) + return 0; + + if (num_pinmux && num_pins) { + dev_err(pctrl->dev, + "DT node must contain either a pinmux or pins and not both\n"); + return -EINVAL; + } + + ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); + if (ret < 0) + return ret; + + if (num_pins && !num_configs) { + dev_err(pctrl->dev, "DT node must contain a config\n"); + ret = -ENODEV; + goto done; + } + + if (num_pinmux) + nmaps += 1; + + if (num_pins) + nmaps += num_pins; + + maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); + if (!maps) { + ret = -ENOMEM; + goto done; + } + + *map = maps; + *num_maps = nmaps; + if (num_pins) { + of_property_for_each_string(np, "pins", prop, pin) { + ret = rzg2l_map_add_config(&maps[idx], pin, + PIN_MAP_TYPE_CONFIGS_PIN, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + ret = 0; + goto done; + } + + pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); + psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), + GFP_KERNEL); + pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); + if (!pins || !psel_val || !pin_fn) { + ret = -ENOMEM; + goto done; + } + + /* Collect pin locations and mux settings from DT properties */ + for (i = 0; i < num_pinmux; ++i) { + u32 value; + + ret = of_property_read_u32_index(np, "pinmux", i, &value); + if (ret) + goto done; + pins[i] = value & MUX_PIN_ID_MASK; + psel_val[i] = MUX_FUNC(value); + } + + /* Register a single pin group listing all the pins we read from DT */ + gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); + if (gsel < 0) { + ret = gsel; + goto done; + } + + /* + * Register a single group function where the 'data' is an array PSEL + * register values read from DT. + */ + pin_fn[0] = np->name; + fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, + psel_val); + if (fsel < 0) { + ret = fsel; + goto remove_group; + } + + maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; + maps[idx].data.mux.group = np->name; + maps[idx].data.mux.function = np->name; + idx++; + + dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); + ret = 0; + goto done; + +remove_group: + pinctrl_generic_remove_group(pctldev, gsel); +done: + *index = idx; + kfree(configs); + return ret; +} + +static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + unsigned int i; + + if (!map) + return; + + for (i = 0; i < num_maps; ++i) { + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || + map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) + kfree(map[i].data.configs.configs); + } + kfree(map); +} + +static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct device_node *child; + unsigned int index; + int ret; + + *map = NULL; + *num_maps = 0; + index = 0; + + for_each_child_of_node(np, child) { + ret = rzg2l_dt_subnode_to_map(pctldev, child, map, + num_maps, &index); + if (ret < 0) { + of_node_put(child); + goto done; + } + } + + if (*num_maps == 0) { + ret = rzg2l_dt_subnode_to_map(pctldev, np, map, + num_maps, &index); + if (ret < 0) + goto done; + } + + if (*num_maps) + return 0; + + dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); + ret = -EINVAL; + +done: + if (ret < 0) + rzg2l_dt_free_map(pctldev, *map, *num_maps); + + return ret; +} + +static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *config) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; + unsigned int *pin_data = pin->drv_data; + unsigned int arg = 0; + unsigned long flags; + void __iomem *addr; + u32 port = 0, reg; + u32 cfg = 0; + u8 bit = 0; + + if (!pin_data) + return -EINVAL; + + if (*pin_data & RZG2L_SINGLE_PIN) { + port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); + bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + } + + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: + if (!(cfg & PIN_CFG_IEN)) + return -EINVAL; + spin_lock_irqsave(&pctrl->lock, flags); + /* handle _L/_H for 32-bit register read/write */ + addr = pctrl->base + IEN(port); + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + reg = readl(addr) & (IEN_MASK << (bit * 8)); + arg = (reg >> (bit * 8)) & 0x1; + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + + case PIN_CONFIG_POWER_SOURCE: { + u32 pwr_reg = 0x0; + + if (cfg & PIN_CFG_IOLH_SD0) + pwr_reg = SD_CH(0); + else if (cfg & PIN_CFG_IOLH_SD1) + pwr_reg = SD_CH(1); + else if (cfg & PIN_CFG_IOLH_QSPI) + pwr_reg = QSPI; + else + return -EINVAL; + + spin_lock_irqsave(&pctrl->lock, flags); + addr = pctrl->base + pwr_reg; + arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + } + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +}; + +static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *_configs, + unsigned int num_configs) +{ + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; + unsigned int *pin_data = pin->drv_data; + enum pin_config_param param; + unsigned long flags; + void __iomem *addr; + u32 port = 0, reg; + unsigned int i; + u32 cfg = 0; + u8 bit = 0; + + if (!pin_data) + return -EINVAL; + + if (*pin_data & RZG2L_SINGLE_PIN) { + port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data); + cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); + bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + } + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(_configs[i]); + switch (param) { + case PIN_CONFIG_INPUT_ENABLE: { + unsigned int arg = + pinconf_to_config_argument(_configs[i]); + + if (!(cfg & PIN_CFG_IEN)) + return -EINVAL; + + /* handle _L/_H for 32-bit register read/write */ + addr = pctrl->base + IEN(port); + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + reg = readl(addr) & ~(IEN_MASK << (bit * 8)); + writel(reg | (arg << (bit * 8)), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + } + + case PIN_CONFIG_POWER_SOURCE: { + unsigned int mV = pinconf_to_config_argument(_configs[i]); + u32 pwr_reg = 0x0; + + if (mV != 1800 && mV != 3300) + return -EINVAL; + + if (cfg & PIN_CFG_IOLH_SD0) + pwr_reg = SD_CH(0); + else if (cfg & PIN_CFG_IOLH_SD1) + pwr_reg = SD_CH(1); + else if (cfg & PIN_CFG_IOLH_QSPI) + pwr_reg = QSPI; + else + return -EINVAL; + + addr = pctrl->base + pwr_reg; + spin_lock_irqsave(&pctrl->lock, flags); + writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + } + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +}; + +static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int i, npins, prev_config = 0; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); + if (ret) + return ret; + + /* Check config matching between to pin */ + if (i && prev_config != *config) + return -EOPNOTSUPP; + + prev_config = *config; + } + + return 0; +}; + +static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = rzg2l_dt_node_to_map, + .dt_free_map = rzg2l_dt_free_map, +}; + +static const struct pinmux_ops rzg2l_pinctrl_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = rzg2l_pinctrl_set_mux, + .strict = true, +}; + +static const struct pinconf_ops rzg2l_pinctrl_confops = { + .is_generic = true, + .pin_config_get = rzg2l_pinctrl_pinconf_get, + .pin_config_set = rzg2l_pinctrl_pinconf_set, + .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, + .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + unsigned long flags; + u8 reg8; + int ret; + + ret = pinctrl_gpio_request(chip->base + offset); + if (ret) + return ret; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* Select GPIO mode in PMC Register */ + reg8 = readb(pctrl->base + PMC(port)); + reg8 &= ~BIT(bit); + writeb(reg8, pctrl->base + PMC(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, + u8 bit, bool output) +{ + unsigned long flags; + u16 reg16; + + spin_lock_irqsave(&pctrl->lock, flags); + + reg16 = readw(pctrl->base + PM(port)); + reg16 &= ~(PM_MASK << (bit * 2)); + + reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); + writew(reg16, pctrl->base + PM(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + + if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { + u16 reg16; + + reg16 = readw(pctrl->base + PM(port)); + reg16 = (reg16 >> (bit * 2)) & PM_MASK; + if (reg16 == PM_OUTPUT) + return GPIO_LINE_DIRECTION_OUT; + } + + return GPIO_LINE_DIRECTION_IN; +} + +static int rzg2l_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + + rzg2l_gpio_set_direction(pctrl, port, bit, false); + + return 0; +} + +static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + unsigned long flags; + u8 reg8; + + spin_lock_irqsave(&pctrl->lock, flags); + + reg8 = readb(pctrl->base + P(port)); + + if (value) + writeb(reg8 | BIT(bit), pctrl->base + P(port)); + else + writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int rzg2l_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + + rzg2l_gpio_set(chip, offset, value); + rzg2l_gpio_set_direction(pctrl, port, bit, true); + + return 0; +} + +static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + u32 port = RZG2L_PIN_ID_TO_PORT(offset); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + u16 reg16; + + reg16 = readw(pctrl->base + PM(port)); + reg16 = (reg16 >> (bit * 2)) & PM_MASK; + + if (reg16 == PM_INPUT) + return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); + else if (reg16 == PM_OUTPUT) + return !!(readb(pctrl->base + P(port)) & BIT(bit)); + else + return -EINVAL; +} + +static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + pinctrl_gpio_free(chip->base + offset); + + /* + * Set the GPIO as an input to ensure that the next GPIO request won't + * drive the GPIO pin as an output. + */ + rzg2l_gpio_direction_input(chip, offset); +} + +static const char * const rzg2l_gpio_names[] = { + "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", + "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", + "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", + "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", + "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", + "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", + "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", + "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", + "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", + "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", + "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", + "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", + "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", + "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", + "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", + "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", + "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", + "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", + "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", + "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", + "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", + "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", + "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", + "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", + "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", + "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", + "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", + "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", + "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", + "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", + "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", + "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", + "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", + "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", + "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", + "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", + "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", + "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", + "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", + "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", + "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", + "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", + "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", + "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", + "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", + "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", + "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", + "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", + "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", +}; + +static const u32 rzg2l_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), +}; + +static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, + (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, + (PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, + { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))}, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) }, + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, + (PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) }, + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, +}; + +static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) +{ + struct device_node *np = pctrl->dev->of_node; + struct gpio_chip *chip = &pctrl->gpio_chip; + const char *name = dev_name(pctrl->dev); + struct of_phandle_args of_args; + int ret; + + ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); + if (ret) { + dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); + return ret; + } + + if (of_args.args[0] != 0 || of_args.args[1] != 0 || + of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) { + dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); + return -EINVAL; + } + + chip->names = rzg2l_gpio_names; + chip->request = rzg2l_gpio_request; + chip->free = rzg2l_gpio_free; + chip->get_direction = rzg2l_gpio_get_direction; + chip->direction_input = rzg2l_gpio_direction_input; + chip->direction_output = rzg2l_gpio_direction_output; + chip->get = rzg2l_gpio_get; + chip->set = rzg2l_gpio_set; + chip->label = name; + chip->parent = pctrl->dev; + chip->owner = THIS_MODULE; + chip->base = -1; + chip->ngpio = of_args.args[2]; + + pctrl->gpio_range.id = 0; + pctrl->gpio_range.pin_base = 0; + pctrl->gpio_range.base = 0; + pctrl->gpio_range.npins = chip->ngpio; + pctrl->gpio_range.name = chip->label; + pctrl->gpio_range.gc = chip; + ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "failed to add GPIO controller\n"); + return ret; + } + + dev_dbg(pctrl->dev, "Registered gpio controller\n"); + + return 0; +} + +static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) +{ + struct pinctrl_pin_desc *pins; + unsigned int i, j; + u32 *pin_data; + int ret; + + pctrl->desc.name = DRV_NAME; + pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; + pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; + pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; + pctrl->desc.confops = &rzg2l_pinctrl_confops; + pctrl->desc.owner = THIS_MODULE; + + pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, + sizeof(*pin_data), GFP_KERNEL); + if (!pin_data) + return -ENOMEM; + + pctrl->pins = pins; + pctrl->desc.pins = pins; + + for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { + pins[i].number = i; + pins[i].name = pctrl->data->port_pins[i]; + if (i && !(i % RZG2L_PINS_PER_PORT)) + j++; + pin_data[i] = pctrl->data->port_pin_configs[j]; + pins[i].drv_data = &pin_data[i]; + } + + for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { + unsigned int index = pctrl->data->n_port_pins + i; + + pins[index].number = index; + pins[index].name = pctrl->data->dedicated_pins[i].name; + pin_data[index] = pctrl->data->dedicated_pins[i].config; + pins[index].drv_data = &pin_data[index]; + } + + ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, + &pctrl->pctl); + if (ret) { + dev_err(pctrl->dev, "pinctrl registration failed\n"); + return ret; + } + + ret = pinctrl_enable(pctrl->pctl); + if (ret) { + dev_err(pctrl->dev, "pinctrl enable failed\n"); + return ret; + } + + ret = rzg2l_gpio_register(pctrl); + if (ret) { + dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); + return ret; + } + + return 0; +} + +static void rzg2l_pinctrl_clk_disable(void *data) +{ + clk_disable_unprepare(data); +} + +static int rzg2l_pinctrl_probe(struct platform_device *pdev) +{ + struct rzg2l_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + + pctrl->data = of_device_get_match_data(&pdev->dev); + if (!pctrl->data) + return -EINVAL; + + pctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->base)) + return PTR_ERR(pctrl->base); + + pctrl->clk = devm_clk_get(pctrl->dev, NULL); + if (IS_ERR(pctrl->clk)) { + ret = PTR_ERR(pctrl->clk); + dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); + return ret; + } + + spin_lock_init(&pctrl->lock); + + platform_set_drvdata(pdev, pctrl); + + ret = clk_prepare_enable(pctrl->clk); + if (ret) { + dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, + pctrl->clk); + if (ret) { + dev_err(pctrl->dev, + "failed to register GPIO clk disable action, %i\n", + ret); + return ret; + } + + ret = rzg2l_pinctrl_register(pctrl); + if (ret) + return ret; + + dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); + return 0; +} + +static struct rzg2l_pinctrl_data r9a07g044_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = rzg2l_gpio_configs, + .dedicated_pins = rzg2l_dedicated_pins, + .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins), +}; + +static const struct of_device_id rzg2l_pinctrl_of_table[] = { + { + .compatible = "renesas,r9a07g044-pinctrl", + .data = &r9a07g044_data, + }, + { /* sentinel */ } +}; + +static struct platform_driver rzg2l_pinctrl_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), + }, + .probe = rzg2l_pinctrl_probe, +}; + +static int __init rzg2l_pinctrl_init(void) +{ + return platform_driver_register(&rzg2l_pinctrl_driver); +} +core_initcall(rzg2l_pinctrl_init); + +MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); +MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver 2021-12-20 13:31 ` [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Lad Prabhakar @ 2021-12-22 9:48 ` Pavel Machek 2021-12-22 10:54 ` Prabhakar Mahadev Lad 0 siblings, 1 reply; 36+ messages in thread From: Pavel Machek @ 2021-12-22 9:48 UTC (permalink / raw) To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das [-- Attachment #1: Type: text/plain, Size: 697 bytes --] Hi! > Add support for pin and gpio controller driver for RZ/G2L SoC. > > Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>. > +static int rzg2l_map_add_config(struct pinctrl_map *map, > + const char *group_or_pin, > + enum pinctrl_map_type type, > + unsigned long *configs, > + unsigned int num_configs) > +{ > + unsigned long *cfgs; > + > + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), > + GFP_KERNEL); Should we check for overflows here, too? Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver 2021-12-22 9:48 ` Pavel Machek @ 2021-12-22 10:54 ` Prabhakar Mahadev Lad 0 siblings, 0 replies; 36+ messages in thread From: Prabhakar Mahadev Lad @ 2021-12-22 10:54 UTC (permalink / raw) To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das Hi Pavel, Thank you for the review. > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: 22 December 2021 09:48 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver > > Hi! > > > Add support for pin and gpio controller driver for RZ/G2L SoC. > > > > Based on a patch in the BSP by Hien Huynh <hien.huynh.px@renesas.com>. > > > +static int rzg2l_map_add_config(struct pinctrl_map *map, > > + const char *group_or_pin, > > + enum pinctrl_map_type type, > > + unsigned long *configs, > > + unsigned int num_configs) > > +{ > > + unsigned long *cfgs; > > + > > + cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), > > + GFP_KERNEL); > > Should we check for overflows here, too? > num_configs should take care while accessing the cfg. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 05/22] pinctrl: renesas: rzg2l: Fix missing port register 21h 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (3 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 06/22] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins Lad Prabhakar ` (18 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit fcfb63148c241adad54ed99fc318167176d7254b upstream. Remove the duplicate port register 22h and replace it with missing port register 21h. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922074140.22178-1-biju.das.jz@bp.renesas.com Fixes: c4c4637eb57f2a25 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index dbf2f521bb27..20b2af889ca9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -852,7 +852,7 @@ static const u32 rzg2l_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 06/22] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (4 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 05/22] pinctrl: renesas: rzg2l: Fix missing port register 21h Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 07/22] arm64: dts: renesas: r9a07g044: Add pinctrl node Lad Prabhakar ` (17 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das commit 471178aa263cb89d43e38c0a279926c99cf67176 upstream. Add scif0 pins in pinctrl node and update the scif0 node to include pinctrl properties. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727112328.18809-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index adcd4f50519e..0987163f25ee 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { aliases { @@ -22,6 +23,15 @@ clock-frequency = <24000000>; }; +&pinctrl { + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; status = "okay"; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 07/22] arm64: dts: renesas: r9a07g044: Add pinctrl node 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (5 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 06/22] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 08/22] clk: renesas: r9a07g044: Add I2C clocks/resets Lad Prabhakar ` (16 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das commit a8675b2d4608aa86d7e5bbfce88cee670fb51191 upstream. Add GPIO/pinctrl node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727112328.18809-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 01482d227506..17afb4bb6261 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -111,6 +111,19 @@ status = "disabled"; }; + pinctrl: pin-controller@11030000 { + compatible = "renesas,r9a07g044-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPIO_RSTN>, + <&cpg R9A07G044_GPIO_PORT_RESETN>, + <&cpg R9A07G044_GPIO_SPARE_RESETN>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 08/22] clk: renesas: r9a07g044: Add I2C clocks/resets 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (6 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 07/22] arm64: dts: renesas: r9a07g044: Add pinctrl node Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 09/22] dt-bindings: i2c: renesas,riic: Convert to json-schema Lad Prabhakar ` (15 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit 1962dd36db4ffe0411e3cb06f0797b7aacf0ca99 upstream. Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index ad3bc21d26c1..39658c315b32 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -90,6 +90,14 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x518, 0), DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 0x518, 1), + DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, + 0x580, 0), + DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, + 0x580, 1), + DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, + 0x580, 2), + DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, + 0x580, 3), DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 0x584, 0), DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, @@ -110,6 +118,10 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), + DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), + DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), + DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), + DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3), DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 09/22] dt-bindings: i2c: renesas,riic: Convert to json-schema 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (7 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 08/22] clk: renesas: r9a07g044: Add I2C clocks/resets Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 10/22] dt-bindings: i2c: renesas,riic: Document RZ/G2L I2C controller Lad Prabhakar ` (14 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Geert Uytterhoeven <geert+renesas@glider.be> commit 92b7716f4c54cb61b30e4680ea436a9e0cc6f4de upstream. Convert the Renesas RZ/A I2C Bus Interface (RIIC) Device Tree binding documentation to json-schema. Document missing properties. Update the example to match reality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Wolfram Sang <wsa@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../devicetree/bindings/i2c/renesas,riic.txt | 32 -------- .../devicetree/bindings/i2c/renesas,riic.yaml | 82 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 83 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/renesas,riic.txt create mode 100644 Documentation/devicetree/bindings/i2c/renesas,riic.yaml diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.txt b/Documentation/devicetree/bindings/i2c/renesas,riic.txt deleted file mode 100644 index e26fe3ad86a9..000000000000 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.txt +++ /dev/null @@ -1,32 +0,0 @@ -Device tree configuration for Renesas RIIC driver - -Required properties: -- compatible : - "renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC. - "renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC. - "renesas,riic-rz" for a generic RZ/A compatible device. -- reg : address start and address range size of device -- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI) -- clock-frequency : frequency of bus clock in Hz -- #address-cells : should be <1> -- #size-cells : should be <0> - -Pinctrl properties might be needed, too. See there. - -Example: - - i2c0: i2c@fcfee000 { - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, - <0 158 IRQ_TYPE_EDGE_RISING>, - <0 159 IRQ_TYPE_EDGE_RISING>, - <0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 164 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml new file mode 100644 index 000000000000..2d6378164958 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/renesas,riic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A I2C Bus Interface (RIIC) + +maintainers: + - Chris Brandt <chris.brandt@renesas.com> + - Wolfram Sang <wsa+renesas@sang-engineering.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,riic-r7s72100 # RZ/A1H + - renesas,riic-r7s9210 # RZ/A2M + - const: renesas,riic-rz # RZ/A + + reg: + maxItems: 1 + + interrupts: + items: + - description: Transmit End Interrupt (TEI) + - description: Receive Data Full Interrupt (RI) + - description: Transmit Data Empty Interrupt (TI) + - description: Stop Condition Detection Interrupt (SPI) + - description: Start Condition Detection Interrupt (STI) + - description: NACK Reception Interrupt (NAKI) + - description: Arbitration-Lost Interrupt (ALI) + - description: Timeout Interrupt (TMOI) + + clock-frequency: + description: + Desired I2C bus clock frequency in Hz. The absence of this property + indicates the default frequency 100 kHz. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-frequency + - power-domains + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r7s72100-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c0: i2c@fcfee000 { + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 4fef10dd2975..591b401f4fbe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14932,7 +14932,7 @@ F: drivers/thermal/rcar_thermal.c RENESAS RIIC DRIVER M: Chris Brandt <chris.brandt@renesas.com> S: Supported -F: Documentation/devicetree/bindings/i2c/renesas,riic.txt +F: Documentation/devicetree/bindings/i2c/renesas,riic.yaml F: drivers/i2c/busses/i2c-riic.c RENESAS USB PHY DRIVER -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 10/22] dt-bindings: i2c: renesas,riic: Document RZ/G2L I2C controller 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (8 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 09/22] dt-bindings: i2c: renesas,riic: Convert to json-schema Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 11/22] arm64: dts: renesas: r9a07g044: Add I2C nodes Lad Prabhakar ` (13 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit a431a0914f9276aa70b7075cb43b9cdc537eaf29 upstream. Document RZ/G2L I2C controller bindings. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../devicetree/bindings/i2c/renesas,riic.yaml | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml index 2d6378164958..52d92ec7ec0b 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/renesas,riic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/A I2C Bus Interface (RIIC) +title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC) maintainers: - Chris Brandt <chris.brandt@renesas.com> @@ -17,9 +17,10 @@ properties: compatible: items: - enum: - - renesas,riic-r7s72100 # RZ/A1H - - renesas,riic-r7s9210 # RZ/A2M - - const: renesas,riic-rz # RZ/A + - renesas,riic-r7s72100 # RZ/A1H + - renesas,riic-r7s9210 # RZ/A2M + - renesas,riic-r9a07g044 # RZ/G2{L,LC} + - const: renesas,riic-rz # RZ/A or RZ/G2L reg: maxItems: 1 @@ -56,6 +57,16 @@ required: - '#address-cells' - '#size-cells' +if: + properties: + compatible: + contains: + enum: + - renesas,riic-r9a07g044 +then: + required: + - resets + unevaluatedProperties: false examples: -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 11/22] arm64: dts: renesas: r9a07g044: Add I2C nodes 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (9 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 10/22] dt-bindings: i2c: renesas,riic: Document RZ/G2L I2C controller Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 12/22] arm64: dts: renesas: r9a07g044: Add I2C interrupt-names Lad Prabhakar ` (12 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit 13df5e881d147d2390e207e854463a1c9bbb7b61 upstream. Add I2C{0,1,2,3} nodes to RZ/G2L (R9A07G044) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-11-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 17afb4bb6261..22fa8dea0805 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -89,6 +89,86 @@ status = "disabled"; }; + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058000 0 0x400>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058400 0 0x400>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058c00 0 0x400>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 12/22] arm64: dts: renesas: r9a07g044: Add I2C interrupt-names 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (10 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 11/22] arm64: dts: renesas: r9a07g044: Add I2C nodes Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 13/22] clk: renesas: r9a07g044: Add DMAC clocks/resets Lad Prabhakar ` (11 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Geert Uytterhoeven <geert+renesas@glider.be> commit 8e8890ea1a5e6ba0649e0d4f7447e812884c7ef4 upstream. Add "interrupt-names" properties to the I2C device nodes, to make it easier to review the interrupt mappings. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/d35ba11bd705e3c728f94ff0414ac6ae1156244f.1626267422.git.geert+renesas@glider.be Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 22fa8dea0805..6e9643c36229 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -102,6 +102,8 @@ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C0_MRST>; @@ -122,6 +124,8 @@ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C1_MRST>; @@ -142,6 +146,8 @@ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C2_MRST>; @@ -162,6 +168,8 @@ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; clock-frequency = <100000>; resets = <&cpg R9A07G044_I2C3_MRST>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 13/22] clk: renesas: r9a07g044: Add DMAC clocks/resets 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (11 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 12/22] arm64: dts: renesas: r9a07g044: Add I2C interrupt-names Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 14/22] dt-bindings: dma: Document RZ/G2L bindings Lad Prabhakar ` (10 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit eb829e549ba65e48b1c16ddecb892a32b366d5e4 upstream. Add DMAC clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 39658c315b32..740355fe7d5c 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -37,6 +37,7 @@ enum clk_ids { CLK_PLL5, CLK_PLL5_DIV2, CLK_PLL6, + CLK_P1_DIV2, /* Module Clocks */ MOD_CLK_BASE, @@ -79,6 +80,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), }; @@ -90,6 +92,10 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x518, 0), DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 0x518, 1), + DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, + 0x52c, 0), + DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, + 0x52c, 1), DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 0x580, 0), DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, @@ -118,6 +124,8 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), + DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), + DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 14/22] dt-bindings: dma: Document RZ/G2L bindings 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (12 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 13/22] clk: renesas: r9a07g044: Add DMAC clocks/resets Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 15/22] dmaengine: Extend the dma_slave_width for 128 bytes Lad Prabhakar ` (9 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit 9b9b12537d3a7b5bea6b9e8f20bffc2338724269 upstream. Document RZ/G2L DMAC bindings. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210806095322.2326-2-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- .../bindings/dma/renesas,rz-dmac.yaml | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml new file mode 100644 index 000000000000..7a4f415d74dc --- /dev/null +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L DMA Controller + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - const: renesas,rz-dmac + + reg: + items: + - description: Control and channel register block + - description: DMA extended resource selector block + + interrupts: + maxItems: 17 + + interrupt-names: + items: + - const: error + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 + + clocks: + items: + - description: DMA main clock + - description: DMA register access clock + + '#dma-cells': + const: 1 + description: + The cell specifies the encoded MID/RID values of the DMAC port + connected to the DMA client and the slave channel configuration + parameters. + bits[0:9] - Specifies MID/RID value + bit[10] - Specifies DMA request high enable (HIEN) + bit[11] - Specifies DMA request detection type (LVL) + bits[12:14] - Specifies DMAACK output mode (AM) + bit[15] - Specifies Transfer Mode (TM) + + dma-channels: + const: 16 + + power-domains: + maxItems: 1 + + resets: + items: + - description: Reset for DMA ARESETN reset terminal + - description: Reset for DMA RST_ASYNC reset terminal + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - '#dma-cells' + - dma-channels + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a07g044-cpg.h> + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g044-dmac", + "renesas,rz-dmac"; + reg = <0x11820000 0x10000>, + <0x11830000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_DMAC_ARESETN>, + <&cpg R9A07G044_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 15/22] dmaengine: Extend the dma_slave_width for 128 bytes 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (13 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 14/22] dt-bindings: dma: Document RZ/G2L bindings Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 16/22] dmaengine: sh: Add DMAC driver for RZ/G2L SoC Lad Prabhakar ` (8 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit ab959c7d4ea086852f35c7ff20ecd79b7471cfad upstream. Add DMA_SLAVE_BUSWIDTH_128_BYTES to dma_slave_width for DMA engines and users to select 128 bytes as bus width. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210806095322.2326-3-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- include/linux/dmaengine.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index dd357a747780..256592c0a365 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -378,6 +378,7 @@ enum dma_slave_buswidth { DMA_SLAVE_BUSWIDTH_16_BYTES = 16, DMA_SLAVE_BUSWIDTH_32_BYTES = 32, DMA_SLAVE_BUSWIDTH_64_BYTES = 64, + DMA_SLAVE_BUSWIDTH_128_BYTES = 128, }; /** @@ -396,7 +397,7 @@ enum dma_slave_buswidth { * @src_addr_width: this is the width in bytes of the source (RX) * register where DMA data shall be read. If the source * is memory this may be ignored depending on architecture. - * Legal values: 1, 2, 3, 4, 8, 16, 32, 64. + * Legal values: 1, 2, 3, 4, 8, 16, 32, 64, 128. * @dst_addr_width: same as src_addr_width but for destination * target (TX) mutatis mutandis. * @src_maxburst: the maximum number of words (note: words, as in -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 16/22] dmaengine: sh: Add DMAC driver for RZ/G2L SoC 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (14 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 15/22] dmaengine: Extend the dma_slave_width for 128 bytes Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 17/22] dmaengine: sh: Fix unused initialization of pointer lmdesc Lad Prabhakar ` (7 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit 5000d37042a61ca556fde2782ca40dbfa802ea16 upstream. Add DMA Controller driver for RZ/G2L SoC. Based on the work done by Chris Brandt for RZ/A DMA driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210806095322.2326-4-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/dma/sh/Kconfig | 9 + drivers/dma/sh/Makefile | 1 + drivers/dma/sh/rz-dmac.c | 971 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 981 insertions(+) create mode 100644 drivers/dma/sh/rz-dmac.c diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig index 13437323a85b..a46296285307 100644 --- a/drivers/dma/sh/Kconfig +++ b/drivers/dma/sh/Kconfig @@ -47,3 +47,12 @@ config RENESAS_USB_DMAC help This driver supports the USB-DMA controller found in the Renesas SoCs. + +config RZ_DMAC + tristate "Renesas RZ/G2L DMA Controller" + depends on ARCH_R9A07G044 || COMPILE_TEST + select RENESAS_DMA + select DMA_VIRTUAL_CHANNELS + help + This driver supports the general purpose DMA controller found in the + Renesas RZ/G2L SoC variants. diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile index 112fbd22bb3f..9b2927f543bf 100644 --- a/drivers/dma/sh/Makefile +++ b/drivers/dma/sh/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_SH_DMAE) += shdma.o obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o +obj-$(CONFIG_RZ_DMAC) += rz-dmac.o diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c new file mode 100644 index 000000000000..11986a8d22fc --- /dev/null +++ b/drivers/dma/sh/rz-dmac.c @@ -0,0 +1,971 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L DMA Controller Driver + * + * Based on imx-dma.c + * + * Copyright (C) 2021 Renesas Electronics Corp. + * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com> + */ + +#include <linux/dma-mapping.h> +#include <linux/dmaengine.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_dma.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#include "../dmaengine.h" +#include "../virt-dma.h" + +enum rz_dmac_prep_type { + RZ_DMAC_DESC_MEMCPY, + RZ_DMAC_DESC_SLAVE_SG, +}; + +struct rz_lmdesc { + u32 header; + u32 sa; + u32 da; + u32 tb; + u32 chcfg; + u32 chitvl; + u32 chext; + u32 nxla; +}; + +struct rz_dmac_desc { + struct virt_dma_desc vd; + dma_addr_t src; + dma_addr_t dest; + size_t len; + struct list_head node; + enum dma_transfer_direction direction; + enum rz_dmac_prep_type type; + /* For slave sg */ + struct scatterlist *sg; + unsigned int sgcount; +}; + +#define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd) + +struct rz_dmac_chan { + struct virt_dma_chan vc; + void __iomem *ch_base; + void __iomem *ch_cmn_base; + unsigned int index; + int irq; + struct rz_dmac_desc *desc; + int descs_allocated; + + enum dma_slave_buswidth src_word_size; + enum dma_slave_buswidth dst_word_size; + dma_addr_t src_per_address; + dma_addr_t dst_per_address; + + u32 chcfg; + u32 chctrl; + int mid_rid; + + struct list_head ld_free; + struct list_head ld_queue; + struct list_head ld_active; + + struct { + struct rz_lmdesc *base; + struct rz_lmdesc *head; + struct rz_lmdesc *tail; + dma_addr_t base_dma; + } lmdesc; +}; + +#define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan) + +struct rz_dmac { + struct dma_device engine; + struct device *dev; + void __iomem *base; + void __iomem *ext_base; + + unsigned int n_channels; + struct rz_dmac_chan *channels; + + DECLARE_BITMAP(modules, 1024); +}; + +#define to_rz_dmac(d) container_of(d, struct rz_dmac, engine) + +/* + * ----------------------------------------------------------------------------- + * Registers + */ + +#define CHSTAT 0x0024 +#define CHCTRL 0x0028 +#define CHCFG 0x002c +#define NXLA 0x0038 + +#define DCTRL 0x0000 + +#define EACH_CHANNEL_OFFSET 0x0040 +#define CHANNEL_0_7_OFFSET 0x0000 +#define CHANNEL_0_7_COMMON_BASE 0x0300 +#define CHANNEL_8_15_OFFSET 0x0400 +#define CHANNEL_8_15_COMMON_BASE 0x0700 + +#define CHSTAT_ER BIT(4) +#define CHSTAT_EN BIT(0) + +#define CHCTRL_CLRINTMSK BIT(17) +#define CHCTRL_CLRSUS BIT(9) +#define CHCTRL_CLRTC BIT(6) +#define CHCTRL_CLREND BIT(5) +#define CHCTRL_CLRRQ BIT(4) +#define CHCTRL_SWRST BIT(3) +#define CHCTRL_STG BIT(2) +#define CHCTRL_CLREN BIT(1) +#define CHCTRL_SETEN BIT(0) +#define CHCTRL_DEFAULT (CHCTRL_CLRINTMSK | CHCTRL_CLRSUS | \ + CHCTRL_CLRTC | CHCTRL_CLREND | \ + CHCTRL_CLRRQ | CHCTRL_SWRST | \ + CHCTRL_CLREN) + +#define CHCFG_DMS BIT(31) +#define CHCFG_DEM BIT(24) +#define CHCFG_DAD BIT(21) +#define CHCFG_SAD BIT(20) +#define CHCFG_REQD BIT(3) +#define CHCFG_SEL(bits) ((bits) & 0x07) +#define CHCFG_MEM_COPY (0x80400008) +#define CHCFG_FILL_DDS(a) (((a) << 16) & GENMASK(19, 16)) +#define CHCFG_FILL_SDS(a) (((a) << 12) & GENMASK(15, 12)) +#define CHCFG_FILL_TM(a) (((a) & BIT(5)) << 22) +#define CHCFG_FILL_AM(a) (((a) & GENMASK(4, 2)) << 6) +#define CHCFG_FILL_LVL(a) (((a) & BIT(1)) << 5) +#define CHCFG_FILL_HIEN(a) (((a) & BIT(0)) << 5) + +#define MID_RID_MASK GENMASK(9, 0) +#define CHCFG_MASK GENMASK(15, 10) +#define CHCFG_DS_INVALID 0xFF +#define DCTRL_LVINT BIT(1) +#define DCTRL_PR BIT(0) +#define DCTRL_DEFAULT (DCTRL_LVINT | DCTRL_PR) + +/* LINK MODE DESCRIPTOR */ +#define HEADER_LV BIT(0) + +#define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16 +#define RZ_DMAC_MAX_CHANNELS 16 +#define DMAC_NR_LMDESC 64 + +/* + * ----------------------------------------------------------------------------- + * Device access + */ + +static void rz_dmac_writel(struct rz_dmac *dmac, unsigned int val, + unsigned int offset) +{ + writel(val, dmac->base + offset); +} + +static void rz_dmac_ext_writel(struct rz_dmac *dmac, unsigned int val, + unsigned int offset) +{ + writel(val, dmac->ext_base + offset); +} + +static u32 rz_dmac_ext_readl(struct rz_dmac *dmac, unsigned int offset) +{ + return readl(dmac->ext_base + offset); +} + +static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val, + unsigned int offset, int which) +{ + if (which) + writel(val, channel->ch_base + offset); + else + writel(val, channel->ch_cmn_base + offset); +} + +static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel, + unsigned int offset, int which) +{ + if (which) + return readl(channel->ch_base + offset); + else + return readl(channel->ch_cmn_base + offset); +} + +/* + * ----------------------------------------------------------------------------- + * Initialization + */ + +static void rz_lmdesc_setup(struct rz_dmac_chan *channel, + struct rz_lmdesc *lmdesc) +{ + u32 nxla; + + channel->lmdesc.base = lmdesc; + channel->lmdesc.head = lmdesc; + channel->lmdesc.tail = lmdesc; + nxla = channel->lmdesc.base_dma; + while (lmdesc < (channel->lmdesc.base + (DMAC_NR_LMDESC - 1))) { + lmdesc->header = 0; + nxla += sizeof(*lmdesc); + lmdesc->nxla = nxla; + lmdesc++; + } + + lmdesc->header = 0; + lmdesc->nxla = channel->lmdesc.base_dma; +} + +/* + * ----------------------------------------------------------------------------- + * Descriptors preparation + */ + +static void rz_dmac_lmdesc_recycle(struct rz_dmac_chan *channel) +{ + struct rz_lmdesc *lmdesc = channel->lmdesc.head; + + while (!(lmdesc->header & HEADER_LV)) { + lmdesc->header = 0; + lmdesc++; + if (lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC)) + lmdesc = channel->lmdesc.base; + } + channel->lmdesc.head = lmdesc; +} + +static void rz_dmac_enable_hw(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan = &channel->vc.chan; + struct rz_dmac *dmac = to_rz_dmac(chan->device); + unsigned long flags; + u32 nxla; + u32 chctrl; + u32 chstat; + + dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); + + local_irq_save(flags); + + rz_dmac_lmdesc_recycle(channel); + + nxla = channel->lmdesc.base_dma + + (sizeof(struct rz_lmdesc) * (channel->lmdesc.head - + channel->lmdesc.base)); + + chstat = rz_dmac_ch_readl(channel, CHSTAT, 1); + if (!(chstat & CHSTAT_EN)) { + chctrl = (channel->chctrl | CHCTRL_SETEN); + rz_dmac_ch_writel(channel, nxla, NXLA, 1); + rz_dmac_ch_writel(channel, channel->chcfg, CHCFG, 1); + rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1); + rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1); + } + + local_irq_restore(flags); +} + +static void rz_dmac_disable_hw(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan = &channel->vc.chan; + struct rz_dmac *dmac = to_rz_dmac(chan->device); + unsigned long flags; + + dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); + + local_irq_save(flags); + rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + local_irq_restore(flags); +} + +static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars) +{ + u32 dmars_offset = (nr / 2) * 4; + u32 shift = (nr % 2) * 16; + u32 dmars32; + + dmars32 = rz_dmac_ext_readl(dmac, dmars_offset); + dmars32 &= ~(0xffff << shift); + dmars32 |= dmars << shift; + + rz_dmac_ext_writel(dmac, dmars32, dmars_offset); +} + +static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan = &channel->vc.chan; + struct rz_dmac *dmac = to_rz_dmac(chan->device); + struct rz_lmdesc *lmdesc = channel->lmdesc.base; + struct rz_dmac_desc *d = channel->desc; + u32 chcfg = CHCFG_MEM_COPY; + + lmdesc = channel->lmdesc.tail; + + /* prepare descriptor */ + lmdesc->sa = d->src; + lmdesc->da = d->dest; + lmdesc->tb = d->len; + lmdesc->chcfg = chcfg; + lmdesc->chitvl = 0; + lmdesc->chext = 0; + lmdesc->header = HEADER_LV; + + rz_dmac_set_dmars_register(dmac, channel->index, 0); + + channel->chcfg = chcfg; + channel->chctrl = CHCTRL_STG | CHCTRL_SETEN; +} + +static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan = &channel->vc.chan; + struct rz_dmac *dmac = to_rz_dmac(chan->device); + struct rz_dmac_desc *d = channel->desc; + struct scatterlist *sg, *sgl = d->sg; + struct rz_lmdesc *lmdesc; + unsigned int i, sg_len = d->sgcount; + + channel->chcfg |= CHCFG_SEL(channel->index) | CHCFG_DEM | CHCFG_DMS; + + if (d->direction == DMA_DEV_TO_MEM) { + channel->chcfg |= CHCFG_SAD; + channel->chcfg &= ~CHCFG_REQD; + } else { + channel->chcfg |= CHCFG_DAD | CHCFG_REQD; + } + + lmdesc = channel->lmdesc.tail; + + for (i = 0, sg = sgl; i < sg_len; i++, sg = sg_next(sg)) { + if (d->direction == DMA_DEV_TO_MEM) { + lmdesc->sa = channel->src_per_address; + lmdesc->da = sg_dma_address(sg); + } else { + lmdesc->sa = sg_dma_address(sg); + lmdesc->da = channel->dst_per_address; + } + + lmdesc->tb = sg_dma_len(sg); + lmdesc->chitvl = 0; + lmdesc->chext = 0; + if (i == (sg_len - 1)) { + lmdesc->chcfg = (channel->chcfg & ~CHCFG_DEM); + lmdesc->header = HEADER_LV; + } else { + lmdesc->chcfg = channel->chcfg; + lmdesc->header = HEADER_LV; + } + if (++lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC)) + lmdesc = channel->lmdesc.base; + } + + channel->lmdesc.tail = lmdesc; + + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + channel->chctrl = CHCTRL_SETEN; +} + +static int rz_dmac_xfer_desc(struct rz_dmac_chan *chan) +{ + struct rz_dmac_desc *d = chan->desc; + struct virt_dma_desc *vd; + + vd = vchan_next_desc(&chan->vc); + if (!vd) + return 0; + + list_del(&vd->node); + + switch (d->type) { + case RZ_DMAC_DESC_MEMCPY: + rz_dmac_prepare_desc_for_memcpy(chan); + break; + + case RZ_DMAC_DESC_SLAVE_SG: + rz_dmac_prepare_descs_for_slave_sg(chan); + break; + + default: + return -EINVAL; + } + + rz_dmac_enable_hw(chan); + + return 0; +} + +/* + * ----------------------------------------------------------------------------- + * DMA engine operations + */ + +static int rz_dmac_alloc_chan_resources(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + + while (channel->descs_allocated < RZ_DMAC_MAX_CHAN_DESCRIPTORS) { + struct rz_dmac_desc *desc; + + desc = kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) + break; + + list_add_tail(&desc->node, &channel->ld_free); + channel->descs_allocated++; + } + + if (!channel->descs_allocated) + return -ENOMEM; + + return channel->descs_allocated; +} + +static void rz_dmac_free_chan_resources(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + struct rz_dmac *dmac = to_rz_dmac(chan->device); + struct rz_lmdesc *lmdesc = channel->lmdesc.base; + struct rz_dmac_desc *desc, *_desc; + unsigned long flags; + unsigned int i; + + spin_lock_irqsave(&channel->vc.lock, flags); + + for (i = 0; i < DMAC_NR_LMDESC; i++) + lmdesc[i].header = 0; + + rz_dmac_disable_hw(channel); + list_splice_tail_init(&channel->ld_active, &channel->ld_free); + list_splice_tail_init(&channel->ld_queue, &channel->ld_free); + + if (channel->mid_rid >= 0) { + clear_bit(channel->mid_rid, dmac->modules); + channel->mid_rid = -EINVAL; + } + + spin_unlock_irqrestore(&channel->vc.lock, flags); + + list_for_each_entry_safe(desc, _desc, &channel->ld_free, node) { + kfree(desc); + channel->descs_allocated--; + } + + INIT_LIST_HEAD(&channel->ld_free); + vchan_free_chan_resources(&channel->vc); +} + +static struct dma_async_tx_descriptor * +rz_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + struct rz_dmac *dmac = to_rz_dmac(chan->device); + struct rz_dmac_desc *desc; + + dev_dbg(dmac->dev, "%s channel: %d src=0x%pad dst=0x%pad len=%zu\n", + __func__, channel->index, &src, &dest, len); + + if (list_empty(&channel->ld_free)) + return NULL; + + desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + + desc->type = RZ_DMAC_DESC_MEMCPY; + desc->src = src; + desc->dest = dest; + desc->len = len; + desc->direction = DMA_MEM_TO_MEM; + + list_move_tail(channel->ld_free.next, &channel->ld_queue); + return vchan_tx_prep(&channel->vc, &desc->vd, flags); +} + +static struct dma_async_tx_descriptor * +rz_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, + enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + struct rz_dmac_desc *desc; + struct scatterlist *sg; + int dma_length = 0; + int i = 0; + + if (list_empty(&channel->ld_free)) + return NULL; + + desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + + for_each_sg(sgl, sg, sg_len, i) { + dma_length += sg_dma_len(sg); + } + + desc->type = RZ_DMAC_DESC_SLAVE_SG; + desc->sg = sgl; + desc->sgcount = sg_len; + desc->len = dma_length; + desc->direction = direction; + + if (direction == DMA_DEV_TO_MEM) + desc->src = channel->src_per_address; + else + desc->dest = channel->dst_per_address; + + list_move_tail(channel->ld_free.next, &channel->ld_queue); + return vchan_tx_prep(&channel->vc, &desc->vd, flags); +} + +static int rz_dmac_terminate_all(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + unsigned long flags; + LIST_HEAD(head); + + rz_dmac_disable_hw(channel); + spin_lock_irqsave(&channel->vc.lock, flags); + list_splice_tail_init(&channel->ld_active, &channel->ld_free); + list_splice_tail_init(&channel->ld_queue, &channel->ld_free); + spin_unlock_irqrestore(&channel->vc.lock, flags); + vchan_get_all_descriptors(&channel->vc, &head); + vchan_dma_desc_free_list(&channel->vc, &head); + + return 0; +} + +static void rz_dmac_issue_pending(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + struct rz_dmac *dmac = to_rz_dmac(chan->device); + struct rz_dmac_desc *desc; + unsigned long flags; + + spin_lock_irqsave(&channel->vc.lock, flags); + + if (!list_empty(&channel->ld_queue)) { + desc = list_first_entry(&channel->ld_queue, + struct rz_dmac_desc, node); + channel->desc = desc; + if (vchan_issue_pending(&channel->vc)) { + if (rz_dmac_xfer_desc(channel) < 0) + dev_warn(dmac->dev, "ch: %d couldn't issue DMA xfer\n", + channel->index); + else + list_move_tail(channel->ld_queue.next, + &channel->ld_active); + } + } + + spin_unlock_irqrestore(&channel->vc.lock, flags); +} + +static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds) +{ + u8 i; + const enum dma_slave_buswidth ds_lut[] = { + DMA_SLAVE_BUSWIDTH_1_BYTE, + DMA_SLAVE_BUSWIDTH_2_BYTES, + DMA_SLAVE_BUSWIDTH_4_BYTES, + DMA_SLAVE_BUSWIDTH_8_BYTES, + DMA_SLAVE_BUSWIDTH_16_BYTES, + DMA_SLAVE_BUSWIDTH_32_BYTES, + DMA_SLAVE_BUSWIDTH_64_BYTES, + DMA_SLAVE_BUSWIDTH_128_BYTES, + }; + + for (i = 0; i < ARRAY_SIZE(ds_lut); i++) { + if (ds_lut[i] == ds) + return i; + } + + return CHCFG_DS_INVALID; +} + +static int rz_dmac_config(struct dma_chan *chan, + struct dma_slave_config *config) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + u32 val; + + channel->src_per_address = config->src_addr; + channel->src_word_size = config->src_addr_width; + channel->dst_per_address = config->dst_addr; + channel->dst_word_size = config->dst_addr_width; + + val = rz_dmac_ds_to_val_mapping(config->dst_addr_width); + if (val == CHCFG_DS_INVALID) + return -EINVAL; + + channel->chcfg |= CHCFG_FILL_DDS(val); + + val = rz_dmac_ds_to_val_mapping(config->src_addr_width); + if (val == CHCFG_DS_INVALID) + return -EINVAL; + + channel->chcfg |= CHCFG_FILL_SDS(val); + + return 0; +} + +static void rz_dmac_virt_desc_free(struct virt_dma_desc *vd) +{ + /* + * Place holder + * Descriptor allocation is done during alloc_chan_resources and + * get freed during free_chan_resources. + * list is used to manage the descriptors and avoid any memory + * allocation/free during DMA read/write. + */ +} + +/* + * ----------------------------------------------------------------------------- + * IRQ handling + */ + +static void rz_dmac_irq_handle_channel(struct rz_dmac_chan *channel) +{ + struct dma_chan *chan = &channel->vc.chan; + struct rz_dmac *dmac = to_rz_dmac(chan->device); + u32 chstat, chctrl; + + chstat = rz_dmac_ch_readl(channel, CHSTAT, 1); + if (chstat & CHSTAT_ER) { + dev_err(dmac->dev, "DMAC err CHSTAT_%d = %08X\n", + channel->index, chstat); + rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + goto done; + } + + chctrl = rz_dmac_ch_readl(channel, CHCTRL, 1); + rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1); +done: + return; +} + +static irqreturn_t rz_dmac_irq_handler(int irq, void *dev_id) +{ + struct rz_dmac_chan *channel = dev_id; + + if (channel) { + rz_dmac_irq_handle_channel(channel); + return IRQ_WAKE_THREAD; + } + /* handle DMAERR irq */ + return IRQ_HANDLED; +} + +static irqreturn_t rz_dmac_irq_handler_thread(int irq, void *dev_id) +{ + struct rz_dmac_chan *channel = dev_id; + struct rz_dmac_desc *desc = NULL; + unsigned long flags; + + spin_lock_irqsave(&channel->vc.lock, flags); + + if (list_empty(&channel->ld_active)) { + /* Someone might have called terminate all */ + goto out; + } + + desc = list_first_entry(&channel->ld_active, struct rz_dmac_desc, node); + vchan_cookie_complete(&desc->vd); + list_move_tail(channel->ld_active.next, &channel->ld_free); + if (!list_empty(&channel->ld_queue)) { + desc = list_first_entry(&channel->ld_queue, struct rz_dmac_desc, + node); + channel->desc = desc; + if (rz_dmac_xfer_desc(channel) == 0) + list_move_tail(channel->ld_queue.next, &channel->ld_active); + } +out: + spin_unlock_irqrestore(&channel->vc.lock, flags); + + return IRQ_HANDLED; +} + +/* + * ----------------------------------------------------------------------------- + * OF xlate and channel filter + */ + +static bool rz_dmac_chan_filter(struct dma_chan *chan, void *arg) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + struct rz_dmac *dmac = to_rz_dmac(chan->device); + struct of_phandle_args *dma_spec = arg; + u32 ch_cfg; + + channel->mid_rid = dma_spec->args[0] & MID_RID_MASK; + ch_cfg = (dma_spec->args[0] & CHCFG_MASK) >> 10; + channel->chcfg = CHCFG_FILL_TM(ch_cfg) | CHCFG_FILL_AM(ch_cfg) | + CHCFG_FILL_LVL(ch_cfg) | CHCFG_FILL_HIEN(ch_cfg); + + return !test_and_set_bit(channel->mid_rid, dmac->modules); +} + +static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + dma_cap_mask_t mask; + + if (dma_spec->args_count != 1) + return NULL; + + /* Only slave DMA channels can be allocated via DT */ + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec); +} + +/* + * ----------------------------------------------------------------------------- + * Probe and remove + */ + +static int rz_dmac_chan_probe(struct rz_dmac *dmac, + struct rz_dmac_chan *channel, + unsigned int index) +{ + struct platform_device *pdev = to_platform_device(dmac->dev); + struct rz_lmdesc *lmdesc; + char pdev_irqname[5]; + char *irqname; + int ret; + + channel->index = index; + channel->mid_rid = -EINVAL; + + /* Request the channel interrupt. */ + sprintf(pdev_irqname, "ch%u", index); + channel->irq = platform_get_irq_byname(pdev, pdev_irqname); + if (channel->irq < 0) + return channel->irq; + + irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u", + dev_name(dmac->dev), index); + if (!irqname) + return -ENOMEM; + + ret = devm_request_threaded_irq(dmac->dev, channel->irq, + rz_dmac_irq_handler, + rz_dmac_irq_handler_thread, 0, + irqname, channel); + if (ret) { + dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", + channel->irq, ret); + return ret; + } + + /* Set io base address for each channel */ + if (index < 8) { + channel->ch_base = dmac->base + CHANNEL_0_7_OFFSET + + EACH_CHANNEL_OFFSET * index; + channel->ch_cmn_base = dmac->base + CHANNEL_0_7_COMMON_BASE; + } else { + channel->ch_base = dmac->base + CHANNEL_8_15_OFFSET + + EACH_CHANNEL_OFFSET * (index - 8); + channel->ch_cmn_base = dmac->base + CHANNEL_8_15_COMMON_BASE; + } + + /* Allocate descriptors */ + lmdesc = dma_alloc_coherent(&pdev->dev, + sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC, + &channel->lmdesc.base_dma, GFP_KERNEL); + if (!lmdesc) { + dev_err(&pdev->dev, "Can't allocate memory (lmdesc)\n"); + return -ENOMEM; + } + rz_lmdesc_setup(channel, lmdesc); + + /* Initialize register for each channel */ + rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + + channel->vc.desc_free = rz_dmac_virt_desc_free; + vchan_init(&channel->vc, &dmac->engine); + INIT_LIST_HEAD(&channel->ld_queue); + INIT_LIST_HEAD(&channel->ld_free); + INIT_LIST_HEAD(&channel->ld_active); + + return 0; +} + +static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) +{ + struct device_node *np = dev->of_node; + int ret; + + ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels); + if (ret < 0) { + dev_err(dev, "unable to read dma-channels property\n"); + return ret; + } + + if (!dmac->n_channels || dmac->n_channels > RZ_DMAC_MAX_CHANNELS) { + dev_err(dev, "invalid number of channels %u\n", dmac->n_channels); + return -EINVAL; + } + + return 0; +} + +static int rz_dmac_probe(struct platform_device *pdev) +{ + const char *irqname = "error"; + struct dma_device *engine; + struct rz_dmac *dmac; + int channel_num; + unsigned int i; + int ret; + int irq; + + dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL); + if (!dmac) + return -ENOMEM; + + dmac->dev = &pdev->dev; + platform_set_drvdata(pdev, dmac); + + ret = rz_dmac_parse_of(&pdev->dev, dmac); + if (ret < 0) + return ret; + + dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels, + sizeof(*dmac->channels), GFP_KERNEL); + if (!dmac->channels) + return -ENOMEM; + + /* Request resources */ + dmac->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dmac->base)) + return PTR_ERR(dmac->base); + + dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(dmac->ext_base)) + return PTR_ERR(dmac->ext_base); + + /* Register interrupt handler for error */ + irq = platform_get_irq_byname(pdev, irqname); + if (irq < 0) + return irq; + + ret = devm_request_irq(&pdev->dev, irq, rz_dmac_irq_handler, 0, + irqname, NULL); + if (ret) { + dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n", + irq, ret); + return ret; + } + + /* Initialize the channels. */ + INIT_LIST_HEAD(&dmac->engine.channels); + + for (i = 0; i < dmac->n_channels; i++) { + ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i); + if (ret < 0) + goto err; + } + + /* Register the DMAC as a DMA provider for DT. */ + ret = of_dma_controller_register(pdev->dev.of_node, rz_dmac_of_xlate, + NULL); + if (ret < 0) + goto err; + + /* Register the DMA engine device. */ + engine = &dmac->engine; + dma_cap_set(DMA_SLAVE, engine->cap_mask); + dma_cap_set(DMA_MEMCPY, engine->cap_mask); + rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); + rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); + + engine->dev = &pdev->dev; + + engine->device_alloc_chan_resources = rz_dmac_alloc_chan_resources; + engine->device_free_chan_resources = rz_dmac_free_chan_resources; + engine->device_tx_status = dma_cookie_status; + engine->device_prep_slave_sg = rz_dmac_prep_slave_sg; + engine->device_prep_dma_memcpy = rz_dmac_prep_dma_memcpy; + engine->device_config = rz_dmac_config; + engine->device_terminate_all = rz_dmac_terminate_all; + engine->device_issue_pending = rz_dmac_issue_pending; + + engine->copy_align = DMAENGINE_ALIGN_1_BYTE; + dma_set_max_seg_size(engine->dev, U32_MAX); + + ret = dma_async_device_register(engine); + if (ret < 0) { + dev_err(&pdev->dev, "unable to register\n"); + goto dma_register_err; + } + return 0; + +dma_register_err: + of_dma_controller_free(pdev->dev.of_node); +err: + channel_num = i ? i - 1 : 0; + for (i = 0; i < channel_num; i++) { + struct rz_dmac_chan *channel = &dmac->channels[i]; + + dma_free_coherent(NULL, + sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC, + channel->lmdesc.base, + channel->lmdesc.base_dma); + } + + return ret; +} + +static int rz_dmac_remove(struct platform_device *pdev) +{ + struct rz_dmac *dmac = platform_get_drvdata(pdev); + unsigned int i; + + for (i = 0; i < dmac->n_channels; i++) { + struct rz_dmac_chan *channel = &dmac->channels[i]; + + dma_free_coherent(NULL, + sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC, + channel->lmdesc.base, + channel->lmdesc.base_dma); + } + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(&dmac->engine); + + return 0; +} + +static const struct of_device_id of_rz_dmac_match[] = { + { .compatible = "renesas,rz-dmac", }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_rz_dmac_match); + +static struct platform_driver rz_dmac_driver = { + .driver = { + .name = "rz-dmac", + .of_match_table = of_rz_dmac_match, + }, + .probe = rz_dmac_probe, + .remove = rz_dmac_remove, +}; + +module_platform_driver(rz_dmac_driver); + +MODULE_DESCRIPTION("Renesas RZ/G2L DMA Controller Driver"); +MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 17/22] dmaengine: sh: Fix unused initialization of pointer lmdesc 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (15 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 16/22] dmaengine: sh: Add DMAC driver for RZ/G2L SoC Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 18/22] dmaengine: sh: fix some NULL dereferences Lad Prabhakar ` (6 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Colin Ian King <colin.king@canonical.com> commit 1e008336b9f590eb749ac96ccef4ea0301f79619 upstream. Pointer lmdesc is being inintialized with a value that is never read, it is later being re-assigned a new value. Fix this by initializing it with the latter value. Addresses-Coverity: ("Unused value") Fixes: 550c591a89a1 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210829152811.529766-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/dma/sh/rz-dmac.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 11986a8d22fc..3d1c239de306 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -308,12 +308,10 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) { struct dma_chan *chan = &channel->vc.chan; struct rz_dmac *dmac = to_rz_dmac(chan->device); - struct rz_lmdesc *lmdesc = channel->lmdesc.base; + struct rz_lmdesc *lmdesc = channel->lmdesc.tail; struct rz_dmac_desc *d = channel->desc; u32 chcfg = CHCFG_MEM_COPY; - lmdesc = channel->lmdesc.tail; - /* prepare descriptor */ lmdesc->sa = d->src; lmdesc->da = d->dest; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 18/22] dmaengine: sh: fix some NULL dereferences 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (16 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 17/22] dmaengine: sh: Fix unused initialization of pointer lmdesc Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 19/22] dmaengine: sh: rz-dmac: Add DMA clock handling Lad Prabhakar ` (5 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Dan Carpenter <dan.carpenter@oracle.com> commit 11a427be2c4749954e8b868ef5301dc65ca5a14b upstream. The dma_free_coherent() function needs a valid device pointer or it will crash. Fixes: 550c591a89a1 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20210827085410.GA9183@kili Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/dma/sh/rz-dmac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 3d1c239de306..f9f30cbeccbe 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -919,7 +919,7 @@ static int rz_dmac_probe(struct platform_device *pdev) for (i = 0; i < channel_num; i++) { struct rz_dmac_chan *channel = &dmac->channels[i]; - dma_free_coherent(NULL, + dma_free_coherent(&pdev->dev, sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC, channel->lmdesc.base, channel->lmdesc.base_dma); @@ -936,7 +936,7 @@ static int rz_dmac_remove(struct platform_device *pdev) for (i = 0; i < dmac->n_channels; i++) { struct rz_dmac_chan *channel = &dmac->channels[i]; - dma_free_coherent(NULL, + dma_free_coherent(&pdev->dev, sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC, channel->lmdesc.base, channel->lmdesc.base_dma); -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 19/22] dmaengine: sh: rz-dmac: Add DMA clock handling 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (17 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 18/22] dmaengine: sh: fix some NULL dereferences Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static Lad Prabhakar ` (4 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit 161596fd776a54df922158175ed844804a861c37 upstream. Currently, DMA clocks are turned on by the bootloader. This patch adds support for DMA clock handling so that the driver manages the DMA clocks. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210923102451.11403-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/dma/sh/rz-dmac.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index f9f30cbeccbe..d9f2cfef878e 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -18,6 +18,7 @@ #include <linux/of_dma.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -872,6 +873,13 @@ static int rz_dmac_probe(struct platform_device *pdev) /* Initialize the channels. */ INIT_LIST_HEAD(&dmac->engine.channels); + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); + goto err_pm_disable; + } + for (i = 0; i < dmac->n_channels; i++) { ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i); if (ret < 0) @@ -925,6 +933,10 @@ static int rz_dmac_probe(struct platform_device *pdev) channel->lmdesc.base_dma); } + pm_runtime_put(&pdev->dev); +err_pm_disable: + pm_runtime_disable(&pdev->dev); + return ret; } @@ -943,6 +955,8 @@ static int rz_dmac_remove(struct platform_device *pdev) } of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&dmac->engine); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); return 0; } -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (18 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 19/22] dmaengine: sh: rz-dmac: Add DMA clock handling Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-22 10:04 ` Pavel Machek 2021-12-20 13:31 ` [PATCH 5.10.y-cip 21/22] arm64: dts: renesas: r9a07g044: Add DMAC support Lad Prabhakar ` (3 subsequent siblings) 23 siblings, 1 reply; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Colin Ian King <colin.king@canonical.com> commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream. Don't populate the read-only array ds_lut on the stack but instead it static. Also makes the object code smaller by 163 bytes: Before: text data bss dec hex filename 23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o After: text data bss dec hex filename 23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o (gcc version 11.2.0) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210915112038.12407-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/dma/sh/rz-dmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index d9f2cfef878e..ee2872e7d64c 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan *chan) static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds) { u8 i; - const enum dma_slave_buswidth ds_lut[] = { + static const enum dma_slave_buswidth ds_lut[] = { DMA_SLAVE_BUSWIDTH_1_BYTE, DMA_SLAVE_BUSWIDTH_2_BYTES, DMA_SLAVE_BUSWIDTH_4_BYTES, -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static 2021-12-20 13:31 ` [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static Lad Prabhakar @ 2021-12-22 10:04 ` Pavel Machek 2021-12-22 10:26 ` Prabhakar Mahadev Lad 2022-01-04 10:39 ` Biju Das 0 siblings, 2 replies; 36+ messages in thread From: Pavel Machek @ 2021-12-22 10:04 UTC (permalink / raw) To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das [-- Attachment #1: Type: text/plain, Size: 1289 bytes --] Hi! > commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream. > > Don't populate the read-only array ds_lut on the stack but instead it > static. Also makes the object code smaller by 163 bytes: > > Before: > text data bss dec hex filename > 23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o > > After: > text data bss dec hex filename > 23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o Heh. > @@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan *chan) > static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth ds) > { > u8 i; > - const enum dma_slave_buswidth ds_lut[] = { > + static const enum dma_slave_buswidth ds_lut[] = { > DMA_SLAVE_BUSWIDTH_1_BYTE, > DMA_SLAVE_BUSWIDTH_2_BYTES, > DMA_SLAVE_BUSWIDTH_4_BYTES, Array could be avoided altogether; you could check for power of two and then count bits. That would give even shorter code, but I'm not sure about readability. I'd also not mind using usual convention here: return int, >= 0 success, < 0 errno. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static 2021-12-22 10:04 ` Pavel Machek @ 2021-12-22 10:26 ` Prabhakar Mahadev Lad 2022-01-04 10:39 ` Biju Das 1 sibling, 0 replies; 36+ messages in thread From: Prabhakar Mahadev Lad @ 2021-12-22 10:26 UTC (permalink / raw) To: Pavel Machek, Biju Das; +Cc: cip-dev, Nobuhiro Iwamatsu Hi Pavel, Thank you for the review. > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: 22 December 2021 10:05 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static > > Hi! > > > commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream. > > > > Don't populate the read-only array ds_lut on the stack but instead it > > static. Also makes the object code smaller by 163 bytes: > > > > Before: > > text data bss dec hex filename > > 23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o > > > > After: > > text data bss dec hex filename > > 23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o > > Heh. > > > @@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan > > *chan) static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth > > ds) { > > u8 i; > > - const enum dma_slave_buswidth ds_lut[] = { > > + static const enum dma_slave_buswidth ds_lut[] = { > > DMA_SLAVE_BUSWIDTH_1_BYTE, > > DMA_SLAVE_BUSWIDTH_2_BYTES, > > DMA_SLAVE_BUSWIDTH_4_BYTES, > > Array could be avoided altogether; you could check for power of two and then count bits. That would > give even shorter code, but I'm not sure about readability. > We might loose readability, Ill let Biju decide on this. > I'd also not mind using usual convention here: return int, >= 0 success, < 0 errno. > Agreed. Cheers, Prabhakar > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static 2021-12-22 10:04 ` Pavel Machek 2021-12-22 10:26 ` Prabhakar Mahadev Lad @ 2022-01-04 10:39 ` Biju Das 1 sibling, 0 replies; 36+ messages in thread From: Biju Das @ 2022-01-04 10:39 UTC (permalink / raw) To: Pavel Machek, Prabhakar Mahadev Lad; +Cc: cip-dev, Nobuhiro Iwamatsu Hi Pavel, > Subject: Re: [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut > static > > Hi! > > > commit 4c0eee50658746b0333d35a75d3db6e0aac08ef9 upstream. > > > > Don't populate the read-only array ds_lut on the stack but instead it > > static. Also makes the object code smaller by 163 bytes: > > > > Before: > > text data bss dec hex filename > > 23508 4796 0 28304 6e90 ./drivers/dma/sh/rz-dmac.o > > > > After: > > text data bss dec hex filename > > 23281 4860 0 28141 6ded ./drivers/dma/sh/rz-dmac.o > > Heh. > > > @@ -574,7 +574,7 @@ static void rz_dmac_issue_pending(struct dma_chan > > *chan) static u8 rz_dmac_ds_to_val_mapping(enum dma_slave_buswidth > > ds) { > > u8 i; > > - const enum dma_slave_buswidth ds_lut[] = { > > + static const enum dma_slave_buswidth ds_lut[] = { > > DMA_SLAVE_BUSWIDTH_1_BYTE, > > DMA_SLAVE_BUSWIDTH_2_BYTES, > > DMA_SLAVE_BUSWIDTH_4_BYTES, > > Array could be avoided altogether; you could check for power of two and > then count bits. That would give even shorter code, but I'm not sure about > readability. > > I'd also not mind using usual convention here: return int, >= 0 success, < > 0 errno. Readability is ok with current implementation and moreover it is faster. Otherwise, you need to check whether it is power of 2, then do count bits to make sure it is bounded between DMA_SLAVE_BUSWIDTH_1_BYTE and DMA_SLAVE_BUSWIDTH_128_BYTES and then return the index. Regards, Biju ^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 21/22] arm64: dts: renesas: r9a07g044: Add DMAC support 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (19 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 22/22] arm64: defconfig: Enable RZ_DMAC Lad Prabhakar ` (2 subsequent siblings) 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit bcd5e5173740087515bf3a05894917d0d8f5779f upstream. Add DMAC support to RZ/G2L SoC DT. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210719092535.4474-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6e9643c36229..7c83a8d39351 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -212,6 +212,42 @@ <&cpg R9A07G044_GPIO_SPARE_RESETN>; }; + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g044-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_DMAC_ARESETN>, + <&cpg R9A07G044_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5.10.y-cip 22/22] arm64: defconfig: Enable RZ_DMAC 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (20 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 21/22] arm64: dts: renesas: r9a07g044: Add DMAC support Lad Prabhakar @ 2021-12-20 13:31 ` Lad Prabhakar 2021-12-21 9:42 ` [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Pavel Machek 2021-12-22 10:06 ` Pavel Machek 23 siblings, 0 replies; 36+ messages in thread From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das From: Biju Das <biju.das.jz@bp.renesas.com> commit 7e2aa15f5ec3a8294127673f186c83b4d87cde13 upstream. Enable DMAC driver support for Renesas RZ/G2L based platforms. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210920093605.8906-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e022d807c6d8..2604bcd75baa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -850,6 +850,7 @@ CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=m +CONFIG_RZ_DMAC=y CONFIG_TI_K3_UDMA=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y CONFIG_VFIO=y -- 2.17.1 ^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (21 preceding siblings ...) 2021-12-20 13:31 ` [PATCH 5.10.y-cip 22/22] arm64: defconfig: Enable RZ_DMAC Lad Prabhakar @ 2021-12-21 9:42 ` Pavel Machek 2021-12-22 10:06 ` Pavel Machek 23 siblings, 0 replies; 36+ messages in thread From: Pavel Machek @ 2021-12-21 9:42 UTC (permalink / raw) To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das [-- Attachment #1: Type: text/plain, Size: 650 bytes --] Hi! > This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. > > All the patches have been cherry picked from v5.16-rc5. > > I have created a MR [0] for cip-kernel-config (for testing purpose), which > can later be merged once this patches have been merged. Series looks okay to me. All I could find are whitespaces/comments/documentation issues. I'll proceed with testing; I can apply it if it passes and there are no other comments. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar ` (22 preceding siblings ...) 2021-12-21 9:42 ` [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Pavel Machek @ 2021-12-22 10:06 ` Pavel Machek 2021-12-22 10:19 ` Prabhakar Mahadev Lad 23 siblings, 1 reply; 36+ messages in thread From: Pavel Machek @ 2021-12-22 10:06 UTC (permalink / raw) To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das [-- Attachment #1: Type: text/plain, Size: 4312 bytes --] Hi! > This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. > > All the patches have been cherry picked from v5.16-rc5. > > I have created a MR [0] for cip-kernel-config (for testing purpose), which > can later be merged once this patches have been merged. And these are various minor nits I noticed while reviewing the code. Best regards, Pavel diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index ef68dabcf4dc3..dacf43ed6d040 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/G2L combined pin and GPIO controller maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ee2872e7d64c6..6946dd0d0485d 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -25,7 +25,7 @@ #include "../dmaengine.h" #include "../virt-dma.h" -enum rz_dmac_prep_type { +enum rz_dmac_prep_type { RZ_DMAC_DESC_MEMCPY, RZ_DMAC_DESC_SLAVE_SG, }; diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 20b2af889ca96..08d0bf139ba3a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, psel_val[i] = MUX_FUNC(value); } - /* Register a single pin group listing all the pins we read from DT */ + /* Register a single pin group, listing all the pins we read from DT */ gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); if (gsel < 0) { ret = gsel; @@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, if (ret) return ret; - /* Check config matching between to pin */ + /* Check config matching between the pins */ if (i && prev_config != *config) return -EOPNOTSUPP; @@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { +static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, @@ -1109,7 +1109,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) pctrl->clk = devm_clk_get(pctrl->dev, NULL); if (IS_ERR(pctrl->clk)) { ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); + dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret); return ret; } @@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) pctrl->clk); if (ret) { dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", + "failed to register GPIO clk disable action: %i\n", ret); return ret; } @@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void) core_initcall(rzg2l_pinctrl_init); MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); -MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); +MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family"); MODULE_LICENSE("GPL v2"); -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply related [flat|nested] 36+ messages in thread
* RE: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic 2021-12-22 10:06 ` Pavel Machek @ 2021-12-22 10:19 ` Prabhakar Mahadev Lad 2021-12-22 10:23 ` [cip-dev] " Pavel Machek 0 siblings, 1 reply; 36+ messages in thread From: Prabhakar Mahadev Lad @ 2021-12-22 10:19 UTC (permalink / raw) To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das Hi Pavel, > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: 22 December 2021 10:06 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic > > Hi! > > > This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. > > > > All the patches have been cherry picked from v5.16-rc5. > > > > I have created a MR [0] for cip-kernel-config (for testing purpose), > > which can later be merged once this patches have been merged. > > And these are various minor nits I noticed while reviewing the code. > Thank you for the review. Do you want me to collate the changes and submit or do you plan to submit them? Cheers, Prabhakar > Best regards, > Pavel > > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > index ef68dabcf4dc3..dacf43ed6d040 100644 > --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya > +++ ml > @@ -4,14 +4,14 @@ > $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Renesas RZ/G2L combined Pin and GPIO controller > +title: Renesas RZ/G2L combined pin and GPIO controller > > maintainers: > - Geert Uytterhoeven <geert+renesas@glider.be> > - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > description: > - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO > + The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO > controller. > Pin multiplexing and GPIO configuration is performed on a per-pin basis. > Each port features up to 8 pins, each of them configurable for GPIO function diff --git > a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ee2872e7d64c6..6946dd0d0485d 100644 > --- a/drivers/dma/sh/rz-dmac.c > +++ b/drivers/dma/sh/rz-dmac.c > @@ -25,7 +25,7 @@ > #include "../dmaengine.h" > #include "../virt-dma.h" > > -enum rz_dmac_prep_type { > +enum rz_dmac_prep_type { > RZ_DMAC_DESC_MEMCPY, > RZ_DMAC_DESC_SLAVE_SG, > }; > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 20b2af889ca96..08d0bf139ba3a 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, > psel_val[i] = MUX_FUNC(value); > } > > - /* Register a single pin group listing all the pins we read from DT */ > + /* Register a single pin group, listing all the pins we read from DT > +*/ > gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); > if (gsel < 0) { > ret = gsel; > @@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, > if (ret) > return ret; > > - /* Check config matching between to pin */ > + /* Check config matching between the pins */ > if (i && prev_config != *config) > return -EOPNOTSUPP; > > @@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = { > RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; > > -static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { > +static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { > { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, > (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, > { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, @@ -1109,7 +1109,7 @@ static int > rzg2l_pinctrl_probe(struct platform_device *pdev) > pctrl->clk = devm_clk_get(pctrl->dev, NULL); > if (IS_ERR(pctrl->clk)) { > ret = PTR_ERR(pctrl->clk); > - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); > + dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret); > return ret; > } > > @@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) > pctrl->clk); > if (ret) { > dev_err(pctrl->dev, > - "failed to register GPIO clk disable action, %i\n", > + "failed to register GPIO clk disable action: %i\n", > ret); > return ret; > } > @@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void) core_initcall(rzg2l_pinctrl_init); > > MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); > -MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); > +MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family"); > MODULE_LICENSE("GPL v2"); > > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [cip-dev] [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic 2021-12-22 10:19 ` Prabhakar Mahadev Lad @ 2021-12-22 10:23 ` Pavel Machek 0 siblings, 0 replies; 36+ messages in thread From: Pavel Machek @ 2021-12-22 10:23 UTC (permalink / raw) To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das [-- Attachment #1: Type: text/plain, Size: 728 bytes --] Hi! > > > This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. > > > > > > All the patches have been cherry picked from v5.16-rc5. > > > > > > I have created a MR [0] for cip-kernel-config (for testing purpose), > > > which can later be merged once this patches have been merged. > > > > And these are various minor nits I noticed while reviewing the code. > > > Thank you for the review. Do you want me to collate the changes and >submit or do you plan to submit them? I'd preffer you to submit them. Thank you, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic @ 2021-12-22 1:22 nobuhiro1.iwamatsu 2021-12-22 9:41 ` Pavel Machek 0 siblings, 1 reply; 36+ messages in thread From: nobuhiro1.iwamatsu @ 2021-12-22 1:22 UTC (permalink / raw) To: pavel, prabhakar.mahadev-lad.rj; +Cc: cip-dev, biju.das.jz Hi all, Hi! >> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. >> >> All the patches have been cherry picked from v5.16-rc5. >> >> I have created a MR [0] for cip-kernel-config (for testing purpose), which >> can later be merged once this patches have been merged. > >Series looks okay to me. All I could find are >whitespaces/comments/documentation issues. > >I'll proceed with testing; I can apply it if it passes and there are >no other comments. I reviewed this series, there was no issue. And build test was all green. https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/433945722 Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Best regards, Nobuhiro ________________________________________ 差出人: Pavel Machek 送信: 2021 12 月 21 日 (火曜日) 18:42 宛先: Lad Prabhakar Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek; Biju Das 件名: Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Hi! > This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. > > All the patches have been cherry picked from v5.16-rc5. > > I have created a MR [0] for cip-kernel-config (for testing purpose), which > can later be merged once this patches have been merged. Series looks okay to me. All I could find are whitespaces/comments/documentation issues. I'll proceed with testing; I can apply it if it passes and there are no other comments. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic 2021-12-22 1:22 nobuhiro1.iwamatsu @ 2021-12-22 9:41 ` Pavel Machek 0 siblings, 0 replies; 36+ messages in thread From: Pavel Machek @ 2021-12-22 9:41 UTC (permalink / raw) To: nobuhiro1.iwamatsu; +Cc: pavel, prabhakar.mahadev-lad.rj, cip-dev, biju.das.jz [-- Attachment #1: Type: text/plain, Size: 1029 bytes --] On Wed 2021-12-22 01:22:09, nobuhiro1.iwamatsu@toshiba.co.jp wrote: > Hi all, > > Hi! > > >> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC. > >> > >> All the patches have been cherry picked from v5.16-rc5. > >> > >> I have created a MR [0] for cip-kernel-config (for testing purpose), which > >> can later be merged once this patches have been merged. > > > >Series looks okay to me. All I could find are > >whitespaces/comments/documentation issues. > > > >I'll proceed with testing; I can apply it if it passes and there are > >no other comments. > > I reviewed this series, there was no issue. > And build test was all green. > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/433945722 > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Thank you, applied. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-01-04 10:39 UTC | newest] Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-20 13:31 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 01/22] mm: slab: provide krealloc_array() Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 02/22] clk: renesas: r9a07g044: Add GPIO clock and reset entries Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 03/22] dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl Lad Prabhakar 2021-12-22 9:45 ` Pavel Machek 2021-12-22 11:05 ` Prabhakar Mahadev Lad 2021-12-20 13:31 ` [PATCH 5.10.y-cip 04/22] pinctrl: renesas: Add RZ/G2L pin and gpio controller driver Lad Prabhakar 2021-12-22 9:48 ` Pavel Machek 2021-12-22 10:54 ` Prabhakar Mahadev Lad 2021-12-20 13:31 ` [PATCH 5.10.y-cip 05/22] pinctrl: renesas: rzg2l: Fix missing port register 21h Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 06/22] arm64: dts: renesas: rzg2l-smarc: Add scif0 pins Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 07/22] arm64: dts: renesas: r9a07g044: Add pinctrl node Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 08/22] clk: renesas: r9a07g044: Add I2C clocks/resets Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 09/22] dt-bindings: i2c: renesas,riic: Convert to json-schema Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 10/22] dt-bindings: i2c: renesas,riic: Document RZ/G2L I2C controller Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 11/22] arm64: dts: renesas: r9a07g044: Add I2C nodes Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 12/22] arm64: dts: renesas: r9a07g044: Add I2C interrupt-names Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 13/22] clk: renesas: r9a07g044: Add DMAC clocks/resets Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 14/22] dt-bindings: dma: Document RZ/G2L bindings Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 15/22] dmaengine: Extend the dma_slave_width for 128 bytes Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 16/22] dmaengine: sh: Add DMAC driver for RZ/G2L SoC Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 17/22] dmaengine: sh: Fix unused initialization of pointer lmdesc Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 18/22] dmaengine: sh: fix some NULL dereferences Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 19/22] dmaengine: sh: rz-dmac: Add DMA clock handling Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 20/22] dmaengine: sh: make array ds_lut static Lad Prabhakar 2021-12-22 10:04 ` Pavel Machek 2021-12-22 10:26 ` Prabhakar Mahadev Lad 2022-01-04 10:39 ` Biju Das 2021-12-20 13:31 ` [PATCH 5.10.y-cip 21/22] arm64: dts: renesas: r9a07g044: Add DMAC support Lad Prabhakar 2021-12-20 13:31 ` [PATCH 5.10.y-cip 22/22] arm64: defconfig: Enable RZ_DMAC Lad Prabhakar 2021-12-21 9:42 ` [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic Pavel Machek 2021-12-22 10:06 ` Pavel Machek 2021-12-22 10:19 ` Prabhakar Mahadev Lad 2021-12-22 10:23 ` [cip-dev] " Pavel Machek 2021-12-22 1:22 nobuhiro1.iwamatsu 2021-12-22 9:41 ` Pavel Machek
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