* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
@ 2021-12-22 1:22 nobuhiro1.iwamatsu
2021-12-22 9:41 ` Pavel Machek
0 siblings, 1 reply; 6+ messages in thread
From: nobuhiro1.iwamatsu @ 2021-12-22 1:22 UTC (permalink / raw)
To: pavel, prabhakar.mahadev-lad.rj; +Cc: cip-dev, biju.das.jz
Hi all,
Hi!
>> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
>>
>> All the patches have been cherry picked from v5.16-rc5.
>>
>> I have created a MR [0] for cip-kernel-config (for testing purpose), which
>> can later be merged once this patches have been merged.
>
>Series looks okay to me. All I could find are
>whitespaces/comments/documentation issues.
>
>I'll proceed with testing; I can apply it if it passes and there are
>no other comments.
I reviewed this series, there was no issue.
And build test was all green.
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/433945722
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Best regards,
Nobuhiro
________________________________________
差出人: Pavel Machek
送信: 2021 12 月 21 日 (火曜日) 18:42
宛先: Lad Prabhakar
Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ); Pavel Machek; Biju Das
件名: Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
Hi!
> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
>
> All the patches have been cherry picked from v5.16-rc5.
>
> I have created a MR [0] for cip-kernel-config (for testing purpose), which
> can later be merged once this patches have been merged.
Series looks okay to me. All I could find are
whitespaces/comments/documentation issues.
I'll proceed with testing; I can apply it if it passes and there are
no other comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
2021-12-22 1:22 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic nobuhiro1.iwamatsu
@ 2021-12-22 9:41 ` Pavel Machek
0 siblings, 0 replies; 6+ messages in thread
From: Pavel Machek @ 2021-12-22 9:41 UTC (permalink / raw)
To: nobuhiro1.iwamatsu; +Cc: pavel, prabhakar.mahadev-lad.rj, cip-dev, biju.das.jz
[-- Attachment #1: Type: text/plain, Size: 1029 bytes --]
On Wed 2021-12-22 01:22:09, nobuhiro1.iwamatsu@toshiba.co.jp wrote:
> Hi all,
>
> Hi!
>
> >> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
> >>
> >> All the patches have been cherry picked from v5.16-rc5.
> >>
> >> I have created a MR [0] for cip-kernel-config (for testing purpose), which
> >> can later be merged once this patches have been merged.
> >
> >Series looks okay to me. All I could find are
> >whitespaces/comments/documentation issues.
> >
> >I'll proceed with testing; I can apply it if it passes and there are
> >no other comments.
>
> I reviewed this series, there was no issue.
> And build test was all green.
> https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/433945722
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Thank you, applied.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
2021-12-22 10:06 ` Pavel Machek
@ 2021-12-22 10:19 ` Prabhakar Mahadev Lad
0 siblings, 0 replies; 6+ messages in thread
From: Prabhakar Mahadev Lad @ 2021-12-22 10:19 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das
Hi Pavel,
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 22 December 2021 10:06
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
>
> Hi!
>
> > This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
> >
> > All the patches have been cherry picked from v5.16-rc5.
> >
> > I have created a MR [0] for cip-kernel-config (for testing purpose),
> > which can later be merged once this patches have been merged.
>
> And these are various minor nits I noticed while reviewing the code.
>
Thank you for the review. Do you want me to collate the changes and submit or do you plan to submit them?
Cheers,
Prabhakar
> Best regards,
> Pavel
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> index ef68dabcf4dc3..dacf43ed6d040 100644
> --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya
> +++ ml
> @@ -4,14 +4,14 @@
> $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Renesas RZ/G2L combined Pin and GPIO controller
> +title: Renesas RZ/G2L combined pin and GPIO controller
>
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> description:
> - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
> + The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO
> controller.
> Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> Each port features up to 8 pins, each of them configurable for GPIO function diff --git
> a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ee2872e7d64c6..6946dd0d0485d 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -25,7 +25,7 @@
> #include "../dmaengine.h"
> #include "../virt-dma.h"
>
> -enum rz_dmac_prep_type {
> +enum rz_dmac_prep_type {
> RZ_DMAC_DESC_MEMCPY,
> RZ_DMAC_DESC_SLAVE_SG,
> };
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 20b2af889ca96..08d0bf139ba3a 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> psel_val[i] = MUX_FUNC(value);
> }
>
> - /* Register a single pin group listing all the pins we read from DT */
> + /* Register a single pin group, listing all the pins we read from DT
> +*/
> gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
> if (gsel < 0) {
> ret = gsel;
> @@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
> if (ret)
> return ret;
>
> - /* Check config matching between to pin */
> + /* Check config matching between the pins */
> if (i && prev_config != *config)
> return -EOPNOTSUPP;
>
> @@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = {
> RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), };
>
> -static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
> +static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
> { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
> (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
> { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, @@ -1109,7 +1109,7 @@ static int
> rzg2l_pinctrl_probe(struct platform_device *pdev)
> pctrl->clk = devm_clk_get(pctrl->dev, NULL);
> if (IS_ERR(pctrl->clk)) {
> ret = PTR_ERR(pctrl->clk);
> - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
> + dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret);
> return ret;
> }
>
> @@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
> pctrl->clk);
> if (ret) {
> dev_err(pctrl->dev,
> - "failed to register GPIO clk disable action, %i\n",
> + "failed to register GPIO clk disable action: %i\n",
> ret);
> return ret;
> }
> @@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void) core_initcall(rzg2l_pinctrl_init);
>
> MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
> -MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
> +MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family");
> MODULE_LICENSE("GPL v2");
>
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
2021-12-20 13:31 Lad Prabhakar
2021-12-21 9:42 ` Pavel Machek
@ 2021-12-22 10:06 ` Pavel Machek
2021-12-22 10:19 ` Prabhakar Mahadev Lad
1 sibling, 1 reply; 6+ messages in thread
From: Pavel Machek @ 2021-12-22 10:06 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 4312 bytes --]
Hi!
> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
>
> All the patches have been cherry picked from v5.16-rc5.
>
> I have created a MR [0] for cip-kernel-config (for testing purpose), which
> can later be merged once this patches have been merged.
And these are various minor nits I noticed while reviewing the code.
Best regards,
Pavel
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index ef68dabcf4dc3..dacf43ed6d040 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/G2L combined pin and GPIO controller
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
- The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+ The Renesas SoCs of the RZ/G2L series feature a combined pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index ee2872e7d64c6..6946dd0d0485d 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -25,7 +25,7 @@
#include "../dmaengine.h"
#include "../virt-dma.h"
-enum rz_dmac_prep_type {
+enum rz_dmac_prep_type {
RZ_DMAC_DESC_MEMCPY,
RZ_DMAC_DESC_SLAVE_SG,
};
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 20b2af889ca96..08d0bf139ba3a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -328,7 +328,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
psel_val[i] = MUX_FUNC(value);
}
- /* Register a single pin group listing all the pins we read from DT */
+ /* Register a single pin group, listing all the pins we read from DT */
gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
if (gsel < 0) {
ret = gsel;
@@ -612,7 +612,7 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
if (ret)
return ret;
- /* Check config matching between to pin */
+ /* Check config matching between the pins */
if (i && prev_config != *config)
return -EOPNOTSUPP;
@@ -886,7 +886,7 @@ static const u32 rzg2l_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
};
-static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
+static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
@@ -1109,7 +1109,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
pctrl->clk = devm_clk_get(pctrl->dev, NULL);
if (IS_ERR(pctrl->clk)) {
ret = PTR_ERR(pctrl->clk);
- dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
+ dev_err(pctrl->dev, "failed to get GPIO clk: %i\n", ret);
return ret;
}
@@ -1127,7 +1127,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
pctrl->clk);
if (ret) {
dev_err(pctrl->dev,
- "failed to register GPIO clk disable action, %i\n",
+ "failed to register GPIO clk disable action: %i\n",
ret);
return ret;
}
@@ -1171,5 +1171,5 @@ static int __init rzg2l_pinctrl_init(void)
core_initcall(rzg2l_pinctrl_init);
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
-MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
+MODULE_DESCRIPTION("Pin and GPIO controller driver for RZ/G2L family");
MODULE_LICENSE("GPL v2");
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
2021-12-20 13:31 Lad Prabhakar
@ 2021-12-21 9:42 ` Pavel Machek
2021-12-22 10:06 ` Pavel Machek
1 sibling, 0 replies; 6+ messages in thread
From: Pavel Machek @ 2021-12-21 9:42 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 650 bytes --]
Hi!
> This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
>
> All the patches have been cherry picked from v5.16-rc5.
>
> I have created a MR [0] for cip-kernel-config (for testing purpose), which
> can later be merged once this patches have been merged.
Series looks okay to me. All I could find are
whitespaces/comments/documentation issues.
I'll proceed with testing; I can apply it if it passes and there are
no other comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic
@ 2021-12-20 13:31 Lad Prabhakar
2021-12-21 9:42 ` Pavel Machek
2021-12-22 10:06 ` Pavel Machek
0 siblings, 2 replies; 6+ messages in thread
From: Lad Prabhakar @ 2021-12-20 13:31 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
Hi All,
This patch series adds Pinctrl/DMAC/IIC support for Renesas RZ/G2L SoC.
All the patches have been cherry picked from v5.16-rc5.
I have created a MR [0] for cip-kernel-config (for testing purpose), which
can later be merged once this patches have been merged.
[0] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/merge_requests/53
Cheers,
Prabhakar
Bartosz Golaszewski (1):
mm: slab: provide krealloc_array()
Biju Das (11):
pinctrl: renesas: rzg2l: Fix missing port register 21h
clk: renesas: r9a07g044: Add I2C clocks/resets
dt-bindings: i2c: renesas,riic: Document RZ/G2L I2C controller
arm64: dts: renesas: r9a07g044: Add I2C nodes
clk: renesas: r9a07g044: Add DMAC clocks/resets
dt-bindings: dma: Document RZ/G2L bindings
dmaengine: Extend the dma_slave_width for 128 bytes
dmaengine: sh: Add DMAC driver for RZ/G2L SoC
dmaengine: sh: rz-dmac: Add DMA clock handling
arm64: dts: renesas: r9a07g044: Add DMAC support
arm64: defconfig: Enable RZ_DMAC
Colin Ian King (2):
dmaengine: sh: Fix unused initialization of pointer lmdesc
dmaengine: sh: make array ds_lut static
Dan Carpenter (1):
dmaengine: sh: fix some NULL dereferences
Geert Uytterhoeven (2):
dt-bindings: i2c: renesas,riic: Convert to json-schema
arm64: dts: renesas: r9a07g044: Add I2C interrupt-names
Lad Prabhakar (5):
clk: renesas: r9a07g044: Add GPIO clock and reset entries
dt-bindings: pinctrl: renesas: Add DT bindings for RZ/G2L pinctrl
pinctrl: renesas: Add RZ/G2L pin and gpio controller driver
arm64: dts: renesas: rzg2l-smarc: Add scif0 pins
arm64: dts: renesas: r9a07g044: Add pinctrl node
Documentation/core-api/memory-allocation.rst | 4 +
.../bindings/dma/renesas,rz-dmac.yaml | 130 ++
.../devicetree/bindings/i2c/renesas,riic.txt | 32 -
.../devicetree/bindings/i2c/renesas,riic.yaml | 93 ++
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 155 +++
MAINTAINERS | 2 +-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 137 ++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 25 +
drivers/dma/sh/Kconfig | 9 +
drivers/dma/sh/Makefile | 1 +
drivers/dma/sh/rz-dmac.c | 983 ++++++++++++++
drivers/pinctrl/renesas/Kconfig | 11 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1175 +++++++++++++++++
include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 +
include/linux/dmaengine.h | 3 +-
include/linux/slab.h | 18 +
19 files changed, 2779 insertions(+), 34 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
delete mode 100644 Documentation/devicetree/bindings/i2c/renesas,riic.txt
create mode 100644 Documentation/devicetree/bindings/i2c/renesas,riic.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
create mode 100644 drivers/dma/sh/rz-dmac.c
create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c
create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-12-22 10:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2021-12-22 1:22 [PATCH 5.10.y-cip 00/22] RZ/G2L: Add support for pinctrl/dmac/iic nobuhiro1.iwamatsu
2021-12-22 9:41 ` Pavel Machek
-- strict thread matches above, loose matches on Subject: below --
2021-12-20 13:31 Lad Prabhakar
2021-12-21 9:42 ` Pavel Machek
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