From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, Daniel Palmer <daniel@0x0f.com>, Alexander Lobakin <alobakin@pm.me>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v3 11/17] mtd: spinand: Allow enabling/disabling Octal DTR mode in the core Date: Sat, 1 Jan 2022 13:12:44 +0530 [thread overview] Message-ID: <20220101074250.14443-12-a-nandan@ti.com> (raw) In-Reply-To: <20220101074250.14443-1-a-nandan@ti.com> Enable Octal DTR SPI mode, i.e. 8D-8D-8D mode, if the SPI NAND flash device supports it. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes (1S-1D-8D), etc. aren't supported yet. The method to switch to Octal DTR SPI mode may vary across manufacturers. For example, for Winbond, it is enabled by writing values to the volatile configuration register. So, let the manufacturer's code have their own implementation for switching to Octal DTR SPI mode. Check for the SPI NAND device's support for Octal DTR mode using spinand flags, and if the data_ops and ctrl_ops are 8D-8D-8D, call change_mode() manufacturer op. If the SPI controller doesn't supports these modes, the selected data_ops and ctrl_ops will prevent switching to the Octal DTR mode. And finally update the spinand protocol and ctrl_ops on success. Similarly, for disabling Octal DTR mode, call change_mode(), and update protocol and ctrl_ops. Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 79 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 80 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 1a602e4dd6bd..2fd08085db6f 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1067,6 +1067,81 @@ spinand_select_ctrl_ops_variant(struct spinand_device *spinand, return NULL; } +static bool spinand_op_is_octal_dtr(const struct spi_mem_op *op) +{ + return op->cmd.buswidth == 8 && op->cmd.dtr && + op->addr.buswidth == 8 && op->addr.dtr && + op->data.buswidth == 8 && op->data.dtr; +} + +static int spinand_init_octal_dtr_enable(struct spinand_device *spinand) +{ + struct device *dev = &spinand->spimem->spi->dev; + const struct spinand_ctrl_ops *octal_dtr_ctrl_ops; + int ret; + + if (!(spinand->flags & SPINAND_HAS_OCTAL_DTR_BIT)) + return 0; + + if (!(spinand_op_is_octal_dtr(spinand->data_ops.read_cache) && + spinand_op_is_octal_dtr(spinand->data_ops.write_cache) && + spinand_op_is_octal_dtr(spinand->data_ops.update_cache))) + return 0; + + octal_dtr_ctrl_ops = spinand_select_ctrl_ops_variant(spinand, + spinand->desc_entry->ctrl_ops_variants, + SPINAND_8D_8D_8D); + + if (!octal_dtr_ctrl_ops) + return 0; + + if (!spinand->manufacturer->ops->change_mode) { + dev_dbg(dev, + "Missing ->change_mode(), unable to switch mode\n"); + return -EINVAL; + } + + ret = spinand->manufacturer->ops->change_mode(spinand, + SPINAND_8D_8D_8D); + if (ret) { + dev_err(dev, + "Failed to enable Octal DTR SPI mode (err = %d)\n", + ret); + return ret; + } + + spinand->protocol = SPINAND_8D_8D_8D; + spinand->ctrl_ops = octal_dtr_ctrl_ops; + + dev_dbg(dev, + "%s SPI NAND switched to Octal DTR SPI (8D-8D-8D) mode\n", + spinand->manufacturer->name); + return 0; +} + +static int spinand_init_octal_dtr_disable(struct spinand_device *spinand) +{ + struct device *dev = &spinand->spimem->spi->dev; + int ret; + + if (!spinand->manufacturer->ops->change_mode) + return -EINVAL; + + ret = spinand->manufacturer->ops->change_mode(spinand, + SPINAND_1S_1S_1S); + + if (ret) { + dev_err(dev, + "Failed to disable Octal DTR SPI mode (err = %d)\n", + ret); + return ret; + } + + spinand->protocol = SPINAND_1S_1S_1S; + spinand->ctrl_ops = &spinand_default_ctrl_ops; + return 0; +} + /** * spinand_match_and_init() - Try to find a match between a device ID and an * entry in a spinand_info table @@ -1203,6 +1278,10 @@ static int spinand_init_flash(struct spinand_device *spinand) break; } + ret = spinand_init_octal_dtr_enable(spinand); + if (ret) + return ret; + if (ret) spinand_manufacturer_cleanup(spinand); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index a8c071983a27..f12aa4516fab 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -417,6 +417,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) +#define SPINAND_HAS_OCTAL_DTR_BIT BIT(2) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, Daniel Palmer <daniel@0x0f.com>, Alexander Lobakin <alobakin@pm.me>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v3 11/17] mtd: spinand: Allow enabling/disabling Octal DTR mode in the core Date: Sat, 1 Jan 2022 13:12:44 +0530 [thread overview] Message-ID: <20220101074250.14443-12-a-nandan@ti.com> (raw) In-Reply-To: <20220101074250.14443-1-a-nandan@ti.com> Enable Octal DTR SPI mode, i.e. 8D-8D-8D mode, if the SPI NAND flash device supports it. Mixed OSPI (1S-1S-8S & 1S-8S-8S), mixed DTR modes (1S-1D-8D), etc. aren't supported yet. The method to switch to Octal DTR SPI mode may vary across manufacturers. For example, for Winbond, it is enabled by writing values to the volatile configuration register. So, let the manufacturer's code have their own implementation for switching to Octal DTR SPI mode. Check for the SPI NAND device's support for Octal DTR mode using spinand flags, and if the data_ops and ctrl_ops are 8D-8D-8D, call change_mode() manufacturer op. If the SPI controller doesn't supports these modes, the selected data_ops and ctrl_ops will prevent switching to the Octal DTR mode. And finally update the spinand protocol and ctrl_ops on success. Similarly, for disabling Octal DTR mode, call change_mode(), and update protocol and ctrl_ops. Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 79 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 80 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 1a602e4dd6bd..2fd08085db6f 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1067,6 +1067,81 @@ spinand_select_ctrl_ops_variant(struct spinand_device *spinand, return NULL; } +static bool spinand_op_is_octal_dtr(const struct spi_mem_op *op) +{ + return op->cmd.buswidth == 8 && op->cmd.dtr && + op->addr.buswidth == 8 && op->addr.dtr && + op->data.buswidth == 8 && op->data.dtr; +} + +static int spinand_init_octal_dtr_enable(struct spinand_device *spinand) +{ + struct device *dev = &spinand->spimem->spi->dev; + const struct spinand_ctrl_ops *octal_dtr_ctrl_ops; + int ret; + + if (!(spinand->flags & SPINAND_HAS_OCTAL_DTR_BIT)) + return 0; + + if (!(spinand_op_is_octal_dtr(spinand->data_ops.read_cache) && + spinand_op_is_octal_dtr(spinand->data_ops.write_cache) && + spinand_op_is_octal_dtr(spinand->data_ops.update_cache))) + return 0; + + octal_dtr_ctrl_ops = spinand_select_ctrl_ops_variant(spinand, + spinand->desc_entry->ctrl_ops_variants, + SPINAND_8D_8D_8D); + + if (!octal_dtr_ctrl_ops) + return 0; + + if (!spinand->manufacturer->ops->change_mode) { + dev_dbg(dev, + "Missing ->change_mode(), unable to switch mode\n"); + return -EINVAL; + } + + ret = spinand->manufacturer->ops->change_mode(spinand, + SPINAND_8D_8D_8D); + if (ret) { + dev_err(dev, + "Failed to enable Octal DTR SPI mode (err = %d)\n", + ret); + return ret; + } + + spinand->protocol = SPINAND_8D_8D_8D; + spinand->ctrl_ops = octal_dtr_ctrl_ops; + + dev_dbg(dev, + "%s SPI NAND switched to Octal DTR SPI (8D-8D-8D) mode\n", + spinand->manufacturer->name); + return 0; +} + +static int spinand_init_octal_dtr_disable(struct spinand_device *spinand) +{ + struct device *dev = &spinand->spimem->spi->dev; + int ret; + + if (!spinand->manufacturer->ops->change_mode) + return -EINVAL; + + ret = spinand->manufacturer->ops->change_mode(spinand, + SPINAND_1S_1S_1S); + + if (ret) { + dev_err(dev, + "Failed to disable Octal DTR SPI mode (err = %d)\n", + ret); + return ret; + } + + spinand->protocol = SPINAND_1S_1S_1S; + spinand->ctrl_ops = &spinand_default_ctrl_ops; + return 0; +} + /** * spinand_match_and_init() - Try to find a match between a device ID and an * entry in a spinand_info table @@ -1203,6 +1278,10 @@ static int spinand_init_flash(struct spinand_device *spinand) break; } + ret = spinand_init_octal_dtr_enable(spinand); + if (ret) + return ret; + if (ret) spinand_manufacturer_cleanup(spinand); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index a8c071983a27..f12aa4516fab 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -417,6 +417,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) +#define SPINAND_HAS_OCTAL_DTR_BIT BIT(2) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2022-01-01 7:44 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-01 7:42 [PATCH v3 00/17] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 01/17] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-04 14:52 ` Mark Brown 2022-01-04 14:52 ` Mark Brown 2022-01-04 15:31 ` Boris Brezillon 2022-01-04 15:31 ` Boris Brezillon 2022-01-05 5:50 ` Pratyush Yadav 2022-01-05 5:50 ` Pratyush Yadav 2022-01-05 7:36 ` Boris Brezillon 2022-01-05 7:36 ` Boris Brezillon 2022-01-05 8:24 ` Tudor.Ambarus 2022-01-05 8:24 ` Tudor.Ambarus 2022-01-01 7:42 ` [PATCH v3 02/17] mtd: spinand: Define macros for Octal DTR ops Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 03/17] mtd: spinand: Add enum spinand_protocol to indicate current SPI IO mode Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-03 10:05 ` Boris Brezillon 2022-01-03 10:05 ` Boris Brezillon 2022-01-01 7:42 ` [PATCH v3 04/17] mtd: spinand: Rename 'op_templates' to 'data_ops' Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-03 9:48 ` Boris Brezillon 2022-01-03 9:48 ` Boris Brezillon 2022-01-01 7:42 ` [PATCH v3 05/17] mtd: spinand: Define ctrl_ops for non-page read/write op templates Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-03 10:01 ` Boris Brezillon 2022-01-03 10:01 ` Boris Brezillon 2022-01-03 10:36 ` Boris Brezillon 2022-01-03 10:36 ` Boris Brezillon 2022-02-15 15:33 ` Apurva Nandan 2022-02-15 15:33 ` Apurva Nandan 2022-02-15 17:37 ` Boris Brezillon 2022-02-15 17:37 ` Boris Brezillon 2022-03-02 15:30 ` Apurva Nandan 2022-03-02 15:30 ` Apurva Nandan 2022-03-02 20:05 ` Boris Brezillon 2022-03-02 20:05 ` Boris Brezillon 2022-03-10 7:57 ` Apurva Nandan 2022-03-10 7:57 ` Apurva Nandan 2022-03-10 8:40 ` Boris Brezillon 2022-03-10 8:40 ` Boris Brezillon 2022-03-14 11:47 ` Apurva Nandan 2022-03-14 11:47 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 06/17] mtd: spinand: Define default ctrl_ops in the core Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 07/17] mtd: spinand: Switch from op macros usage to 'ctrl_ops' " Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 08/17] mtd: spinand: Add support for manufacturer-based ctrl_ops variations Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 09/17] mtd: spinand: Add change_mode() in manufacturer_ops Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-05 9:52 ` Boris Brezillon 2022-01-05 9:52 ` Boris Brezillon 2022-01-01 7:42 ` [PATCH v3 10/17] mtd: spinand: Add pointer to probed flash's spinand_info Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan [this message] 2022-01-01 7:42 ` [PATCH v3 11/17] mtd: spinand: Allow enabling/disabling Octal DTR mode in the core Apurva Nandan 2022-01-03 10:14 ` Boris Brezillon 2022-01-03 10:14 ` Boris Brezillon 2022-01-01 7:42 ` [PATCH v3 12/17] mtd: spinand: Add mtd_suspend() to disable Octal DTR mode at suspend Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-03 10:17 ` Boris Brezillon 2022-01-03 10:17 ` Boris Brezillon 2022-01-01 7:42 ` [PATCH v3 13/17] mtd: spinand: winbond: Add support for write volatile configuration register op Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 14/17] mtd: spinand: winbond: Add octal_dtr_enable/disable() in manufacturer_ops Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 15/17] mtd: spianand: winbond: Add change_mode() manufacturer_ops Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-03 10:27 ` Boris Brezillon 2022-01-03 10:27 ` Boris Brezillon 2022-01-01 7:42 ` [PATCH v3 16/17] mtd: spinand: winbond: Rename cache op_variants struct variable Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan 2022-01-01 7:42 ` [PATCH v3 17/17] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan 2022-01-01 7:42 ` Apurva Nandan
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