* [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions
@ 2022-01-08 4:40 Matt Roper
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
` (10 more replies)
0 siblings, 11 replies; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Let's start splitting up and cleaning up parts of i915_reg.h. Rather
than starting with dead code removal as we did in v1, this time we'll
switch a few macros to parameterized style, and then move a few types of
registers (engine registers, SNPS PHY registers) off to their own header
files.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Matt Roper (7):
drm/i915: Use parameterized GPR register definitions everywhere
drm/i915: Parameterize PWRCTX_MAXCNT
drm/i915: Parameterize ECOSKPD
drm/i915: Use RING_PSMI_CTL rather than per-engine macros
drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
drm/i915/gt: Move engine registers to their own header
drm/i915: Move SNPS PHY registers to their own header
drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
.../drm/i915/display/intel_snps_phy_regs.h | 73 ++++
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 197 ++++++++++
.../drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 15 -
drivers/gpu/drm/i915/gt/intel_rc6.c | 9 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/gt/intel_ring.c | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 11 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 1 +
drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 5 +-
drivers/gpu/drm/i915/gvt/mmio_context.h | 1 +
drivers/gpu/drm/i915/i915_cmd_parser.c | 69 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 354 +-----------------
drivers/gpu/drm/i915/i915_reg_defs.h | 98 +++++
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 11 +-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
35 files changed, 459 insertions(+), 420 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_regs.h
create mode 100644 drivers/gpu/drm/i915/i915_reg_defs.h
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 11:20 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
` (9 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
Since we have an engine-parameterized macro GEN8_RING_CS_GPR, let's use
that in place of the HSW_CS_GPR and BCS_GPR register definitions.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 68 ++++++++++++++------------
drivers/gpu/drm/i915/i915_reg.h | 8 ---
2 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index e0403ce9ce69..20191a32478a 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -591,6 +591,10 @@ struct drm_i915_reg_descriptor {
{ .addr = _reg(idx) }, \
{ .addr = _reg ## _UDW(idx) }
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
+
static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(GPGPU_THREADS_DISPATCHED),
REG64(HS_INVOCATION_COUNT),
@@ -636,22 +640,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
};
static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
- REG64_IDX(HSW_CS_GPR, 0),
- REG64_IDX(HSW_CS_GPR, 1),
- REG64_IDX(HSW_CS_GPR, 2),
- REG64_IDX(HSW_CS_GPR, 3),
- REG64_IDX(HSW_CS_GPR, 4),
- REG64_IDX(HSW_CS_GPR, 5),
- REG64_IDX(HSW_CS_GPR, 6),
- REG64_IDX(HSW_CS_GPR, 7),
- REG64_IDX(HSW_CS_GPR, 8),
- REG64_IDX(HSW_CS_GPR, 9),
- REG64_IDX(HSW_CS_GPR, 10),
- REG64_IDX(HSW_CS_GPR, 11),
- REG64_IDX(HSW_CS_GPR, 12),
- REG64_IDX(HSW_CS_GPR, 13),
- REG64_IDX(HSW_CS_GPR, 14),
- REG64_IDX(HSW_CS_GPR, 15),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
REG32(HSW_SCRATCH1,
.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
.value = 0),
@@ -674,22 +678,22 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
REG32(BCS_SWCTRL),
REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
- REG64_IDX(BCS_GPR, 0),
- REG64_IDX(BCS_GPR, 1),
- REG64_IDX(BCS_GPR, 2),
- REG64_IDX(BCS_GPR, 3),
- REG64_IDX(BCS_GPR, 4),
- REG64_IDX(BCS_GPR, 5),
- REG64_IDX(BCS_GPR, 6),
- REG64_IDX(BCS_GPR, 7),
- REG64_IDX(BCS_GPR, 8),
- REG64_IDX(BCS_GPR, 9),
- REG64_IDX(BCS_GPR, 10),
- REG64_IDX(BCS_GPR, 11),
- REG64_IDX(BCS_GPR, 12),
- REG64_IDX(BCS_GPR, 13),
- REG64_IDX(BCS_GPR, 14),
- REG64_IDX(BCS_GPR, 15),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
};
#undef REG64
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e20e832162b4..86e459010465 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -599,10 +599,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define BCS_SRC_Y REG_BIT(0)
#define BCS_DST_Y REG_BIT(1)
-/* There are 16 GPR registers */
-#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
-#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
-
#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
#define HS_INVOCATION_COUNT _MMIO(0x2300)
@@ -646,10 +642,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
-/* There are the 16 64-bit CS General Purpose Registers */
-#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
-#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
-
#define GEN7_OACONTROL _MMIO(0x2360)
#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 11:06 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD Matt Roper
` (8 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
Rather than having separate definitions for each engine, create a single
parameterized macro that takes the engine base offset. This will also
ensure we get to the proper offset if we ever need to use these
registers on newer platforms (where the media engine offsets have
changed).
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 6 +-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index c3155ee58689..45891e6f0b98 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
enable_rc6 = false;
}
- if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+ if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
drm_dbg(&i915->drm,
"Engine Idle wait time not set properly.\n");
enable_rc6 = false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86e459010465..23330faecf07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9297,11 +9297,7 @@ enum {
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
-#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
-#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
-#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
-#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 11:10 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
` (7 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
Combine the separate render and blitter register definitions into a
single definition. We already know we have some workarounds on an
upcoming platform that will need to update the ECOSKPD register for
other engines too, so this helps pave the way for that.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 14 ++++++--------
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ab3277a3d593..2d87dc81cd63 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2536,7 +2536,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* they are already accustomed to from before contexts were
* enabled.
*/
- wa_add(wal, ECOSKPD,
+ wa_add(wal, ECOSKPD(RENDER_RING_BASE),
0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
0 /* XXX bit doesn't stick on Broadwater */,
true);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3938df0db188..329d30a36f4f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2877,9 +2877,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0x3c), D_ALL);
MMIO_D(_MMIO(0x860), D_ALL);
- MMIO_D(ECOSKPD, D_ALL);
+ MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
MMIO_D(_MMIO(0x121d0), D_ALL);
- MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
+ MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
MMIO_D(_MMIO(0x41d0), D_ALL);
MMIO_D(GAC_ECO_BITS, D_ALL);
MMIO_D(_MMIO(0x6200), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 23330faecf07..5b1f93112001 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3107,10 +3107,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
-#define ECOSKPD _MMIO(0x21d0)
-#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
-#define ECO_GATING_CX_ONLY (1 << 3)
-#define ECO_FLIP_DONE (1 << 0)
+#define ECOSKPD(base) _MMIO((base) + 0x1d0)
+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
+#define ECO_GATING_CX_ONLY REG_BIT(3)
+#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
+#define ECO_FLIP_DONE REG_BIT(0)
+#define GEN6_BLITTER_LOCK_SHIFT 16
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -3120,10 +3122,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
-#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
-#define GEN6_BLITTER_LOCK_SHIFT 16
-#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
-
#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b357ec35a4a..2d0955d13776 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7868,10 +7868,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
if (IS_PINEVIEW(dev_priv))
- intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
/* IIR "flip pending" means done if this bit is set */
- intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
/* interrupts should cause a wake up from C3 */
intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (2 preceding siblings ...)
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 11:14 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
` (6 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
We have a parameterized macro for RING_PSMI_CTL; let's use that instead
of the per-engine definitions where possible.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 10 +++++-----
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 19 +++++++------------
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
4 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3e6fac0340ef..56c009ecfdf2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1002,15 +1002,15 @@ static void gen6_bsd_submit_request(struct i915_request *request)
/* Disable notification that the ring is IDLE. The GT
* will then assume that it is busy and bring it out of rc6.
*/
- intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
/* Clear the context id. Here be magic! */
intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
/* Wait for the ring not to be idle, i.e. for it to wake up. */
if (__intel_wait_for_register_fw(uncore,
- GEN6_BSD_SLEEP_PSMI_CONTROL,
+ RING_PSMI_CTL(GEN6_BSD_RING_BASE),
GEN6_BSD_SLEEP_INDICATOR,
0,
1000, 0, NULL))
@@ -1023,8 +1023,8 @@ static void gen6_bsd_submit_request(struct i915_request *request)
/* Let the ring send IDLE messages to the GT again,
* and so let it sleep to conserve power when idle.
*/
- intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2d87dc81cd63..977619ea839a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2208,7 +2208,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* For DG1 this only applies to A0.
*/
wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
+ RING_PSMI_CTL(RENDER_RING_BASE),
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b1f93112001..b227a1e58f9b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2563,6 +2563,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
#define GEN6_NOSYNC INVALID_MMIO_REG
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
+#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
+#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
+#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
#define RING_ID(base) _MMIO((base) + 0x8c)
@@ -3122,12 +3129,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
-#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
-#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
-#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
-
#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
@@ -3213,12 +3214,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define XEHP_EU_ENABLE _MMIO(0x9134)
#define XEHP_EU_ENA_MASK 0xFF
-#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
-#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
-#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
-#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
-#define GEN6_BSD_GO_INDICATOR (1 << 4)
-
/* On modern GEN architectures interrupt control consists of two sets
* of registers. The first set pertains to the ring generating the
* interrupt. The second control is for the functional block generating the
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d0955d13776..710dee28a014 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7654,7 +7654,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
- intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableSDEUnitClockGating:bdw */
@@ -7795,7 +7795,7 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
/* WaDisableSemaphoreAndSyncFlipWait:chv */
- intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableCSUnitClockGating:chv */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (3 preceding siblings ...)
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 11:15 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header Matt Roper
` (5 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
It's preferable to use parameterized register macros where possible.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 -
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 977619ea839a..895939a941d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2423,7 +2423,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (GRAPHICS_VER(i915) == 7) {
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
wa_masked_en(wal,
- GFX_MODE_GEN7,
+ RING_MODE_GEN7(RENDER_RING_BASE),
GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
/* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index f776c470914d..abc81cdc9e5d 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -44,7 +44,7 @@
/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
- {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
@@ -76,7 +76,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
};
static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
- {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b227a1e58f9b..7f0168ba55f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2918,7 +2918,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
#define GFX_MODE _MMIO(0x2520)
-#define GFX_MODE_GEN7 _MMIO(0x229c)
#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
#define GFX_RUN_LIST_ENABLE (1 << 15)
#define GFX_INTERRUPT_STEERING (1 << 14)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (4 preceding siblings ...)
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 10:59 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY " Matt Roper
` (4 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
Let's start breaking up and cleaning up the massive i915_reg.h file.
We'll start by moving all registers that are defined in relation to an
engine base to their own header.
There are probably a bunch of other "engine registers" that we haven't
moved yet (especially those that belong to the render engine in the
0x2??? range), but this is a relatively straightforward first step.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 197 +++++++++++++
.../drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 15 -
drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/gt/intel_ring.c | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 1 +
drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
drivers/gpu/drm/i915/gvt/mmio_context.h | 1 +
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 267 +-----------------
drivers/gpu/drm/i915/i915_reg_defs.h | 98 +++++++
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
32 files changed, 327 insertions(+), 281 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_regs.h
create mode 100644 drivers/gpu/drm/i915/i915_reg_defs.h
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 61383830505e..e0e8d228b31f 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -6,6 +6,7 @@
#include "gen2_engine_cs.h"
#include "i915_drv.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
index b388ceeeb1c9..5e65550b4dfb 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -5,6 +5,7 @@
#include "gen6_engine_cs.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 6e9292918bfc..56999186830b 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -9,6 +9,7 @@
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
/* Write pde (index) from the page directory @pd to the page table @pt */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 352254e001b4..32bf81da50ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -13,6 +13,7 @@
#include "intel_context.h"
#include "intel_engine.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_engine_user.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
new file mode 100644
index 000000000000..60511f310767
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_ENGINE_REGS__
+#define __INTEL_ENGINE_REGS__
+
+#include "i915_reg_defs.h"
+
+#define RING_TAIL(base) _MMIO((base) + 0x30)
+#define TAIL_ADDR 0x001FFFF8
+#define RING_HEAD(base) _MMIO((base) + 0x34)
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START(base) _MMIO((base) + 0x38)
+#define RING_CTL(base) _MMIO((base) + 0x3c)
+#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
+#define RING_NR_PAGES 0x001FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
+#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
+#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
+#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
+#define RING_SYNC_0(base) _MMIO((base) + 0x40)
+#define RING_SYNC_1(base) _MMIO((base) + 0x44)
+#define RING_SYNC_2(base) _MMIO((base) + 0x48)
+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
+#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
+#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
+#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
+#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
+#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
+#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
+#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
+#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
+#define IDLE_TIME_MASK 0xFFFFF
+#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
+#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
+#define RING_IPEIR(base) _MMIO((base) + 0x64)
+#define RING_IPEHR(base) _MMIO((base) + 0x68)
+#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
+#define RING_INSTPS(base) _MMIO((base) + 0x70)
+#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
+#define RING_ACTHD(base) _MMIO((base) + 0x74)
+#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
+#define IPEIR(base) _MMIO((base) + 0x88)
+#define IPEHR(base) _MMIO((base) + 0x8c)
+#define RING_ID(base) _MMIO((base) + 0x8c)
+#define RING_NOPID(base) _MMIO((base) + 0x94)
+#define RING_HWSTAM(base) _MMIO((base) + 0x98)
+#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
+#define RING_IMR(base) _MMIO((base) + 0xa8)
+#define RING_EIR(base) _MMIO((base) + 0xb0)
+#define RING_EMR(base) _MMIO((base) + 0xb4)
+#define RING_ESR(base) _MMIO((base) + 0xb8)
+#define RING_INSTPM(base) _MMIO((base) + 0xc0)
+#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
+#define ACTHD(base) _MMIO((base) + 0xc8)
+#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
+#define RESET_CTL_CAT_ERROR REG_BIT(2)
+#define RESET_CTL_READY_TO_RESET REG_BIT(1)
+#define RESET_CTL_REQUEST_RESET REG_BIT(0)
+#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
+#define RING_BBSTATE(base) _MMIO((base) + 0x110)
+#define RING_BB_PPGTT (1 << 5)
+#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
+#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
+#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
+#define RING_BBADDR(base) _MMIO((base) + 0x140)
+#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
+#define CCID(base) _MMIO((base) + 0x180)
+#define CCID_EN BIT(0)
+#define CCID_EXTENDED_STATE_RESTORE BIT(2)
+#define CCID_EXTENDED_STATE_SAVE BIT(3)
+#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
+#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
+#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
+#define ECOSKPD(base) _MMIO((base) + 0x1d0)
+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
+#define ECO_GATING_CX_ONLY REG_BIT(3)
+#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
+#define ECO_FLIP_DONE REG_BIT(0)
+#define GEN6_BLITTER_LOCK_SHIFT 16
+
+#define BLIT_CCTL(base) _MMIO((base) + 0x204)
+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
+#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
+ BLIT_CCTL_SRC_MOCS_MASK)
+#define BLIT_CCTL_MOCS(dst, src) \
+ (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
+
+/*
+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
+ * The lsb of each can be considered a separate enabling bit for encryption.
+ * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
+ * 15:14 == Reserved => 31:30 are set to 0.
+ */
+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
+#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
+ CMD_CCTL_READ_OVERRIDE_MASK)
+#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
+ (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
+ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+
+#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
+#define PP_DIR_DCLV_2G 0xffffffff
+#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
+#define RING_ELSP(base) _MMIO((base) + 0x230)
+#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
+#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
+#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
+#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
+#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
+#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
+#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
+#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
+#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
+#define GFX_RUN_LIST_ENABLE (1 << 15)
+#define GFX_INTERRUPT_STEERING (1 << 14)
+#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
+#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
+#define GFX_REPLAY_MODE (1 << 11)
+#define GFX_PSMI_GRANULARITY (1 << 10)
+#define GFX_PPGTT_ENABLE (1 << 9)
+#define GEN8_GFX_PPGTT_48B (1 << 7)
+#define GFX_FORWARD_VBLANK_MASK (3 << 5)
+#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
+#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
+#define GFX_FORWARD_VBLANK_COND (2 << 5)
+#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
+#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
+#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
+#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
+#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
+#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
+#define RING_FORCE_TO_NONPRIV_MASK_VALID \
+ (RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
+#define RING_MAX_NONPRIV_SLOTS 12
+
+#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
+#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
+#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
+#define EL_CTRL_LOAD REG_BIT(0)
+
+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
+#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
+#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
+
+#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
+
+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
+#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
+
+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
+
+
+#endif /* __INTEL_ENGINE_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index be56d0b41892..960a9aaf4f3a 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -116,6 +116,7 @@
#include "intel_context.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_engine_stats.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 298ff32c8d0c..622cdfed8a8b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -11,6 +11,7 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "intel_context.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_buffer_pool.h"
#include "intel_gt_clock_utils.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 84456ffeb4cd..89a95a125fc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "i915_perf.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_lrc.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index f785d0ed238f..304000c7e345 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -53,21 +53,6 @@
#define GEN8_EXECLISTS_STATUS_BUF 0x370
#define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
-/* Execlists regs */
-#define RING_ELSP(base) _MMIO((base) + 0x230)
-#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
-#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
-#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
-#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
-#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
-#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
-#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
-#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
-#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
-#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
-#define EL_CTRL_LOAD REG_BIT(0)
-
/*
* The docs specify that the write pointer wraps around after 5h, "After status
* is written out to the last available status QW at offset 5h, this pointer
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 45891e6f0b98..31ebe3f1765d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "i915_vgpu.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_pcode.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7be0002d9d70..bd0591400b2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -16,6 +16,7 @@
#include "i915_irq.h"
#include "intel_breadcrumbs.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 2fdd52b62092..723055340c9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "i915_vma.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_ring.h"
#include "intel_timeline.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 56c009ecfdf2..a2b7be1d4f5c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -11,6 +11,7 @@
#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "intel_reset.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 895939a941d6..6a4372c3a3c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 8af261831470..0dcb3ed44a73 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -6,6 +6,7 @@
#include <linux/sort.h>
#include "i915_selftest.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt_clock_utils.h"
#include "selftest_engine.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 8bf62a5826cc..be94f863bdef 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -5,6 +5,7 @@
#include <linux/sort.h>
+#include "intel_engine_regs.h"
#include "intel_gt_clock_utils.h"
#include "selftest_llc.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 7ee2513e15f9..bd170ba1cf00 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -8,6 +8,7 @@
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e2eb686a9763..0410c402f2a3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -8,6 +8,7 @@
#include "intel_context.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 1a1edae67e4e..93a975597b4d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -5,6 +5,7 @@
#include <linux/bsearch.h>
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_lrc.h"
#include "gt/shmem_utils.h"
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9989d121127d..c4f9f051a695 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -9,8 +9,9 @@
#include "gt/gen8_engine_cs.h"
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_context.h"
-#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_clock_utils.h"
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index c4118b808268..733e68ea210a 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -37,6 +37,7 @@
#include <linux/slab.h>
#include "i915_drv.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_lrc.h"
#include "gt/intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index abc81cdc9e5d..99d3534d2bd8 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -35,6 +35,7 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
#include "gvt.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h b/drivers/gpu/drm/i915/gvt/mmio_context.h
index b6b69777af49..128fd7f4d509 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.h
@@ -38,6 +38,7 @@
#include <linux/types.h>
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 20191a32478a..35dde940a5e2 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -26,6 +26,7 @@
*/
#include "gt/intel_engine.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5ae812d60abe..edcc2ae6d66c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -41,6 +41,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 298857b69180..14bf1b67aa43 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_execlists_submission.h"
#include "gt/intel_gpu_commands.h"
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ea655161793e..bf93f9720e0a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,7 @@
#include "gt/intel_engine.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f0168ba55f2..8ead30b47c69 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,8 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
-#include <linux/bitfield.h>
-#include <linux/bits.h>
+#include "i915_reg_defs.h"
/**
* DOC: The i915 register macro definition style guide
@@ -116,91 +115,6 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
-/**
- * REG_BIT() - Prepare a u32 bit value
- * @__n: 0-based bit number
- *
- * Local wrapper for BIT() to force u32, with compile time checks.
- *
- * @return: Value with bit @__n set.
- */
-#define REG_BIT(__n) \
- ((u32)(BIT(__n) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
- ((__n) < 0 || (__n) > 31))))
-
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low) \
- ((u32)(GENMASK(__high, __low) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
- __is_constexpr(__low) && \
- ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-
-/*
- * Local integer constant expression version of is_power_of_2().
- */
-#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-
-/**
- * REG_FIELD_PREP() - Prepare a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to put in the field
- *
- * Local copy of FIELD_PREP() to generate an integer constant expression, force
- * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
- *
- * @return: @__val masked and shifted into the field defined by @__mask.
- */
-#define REG_FIELD_PREP(__mask, __val) \
- ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
- BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
- BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
- BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
- BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-
-/**
- * REG_FIELD_GET() - Extract a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to extract the bitfield value from
- *
- * Local wrapper for FIELD_GET() to force u32 and for consistency with
- * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
- *
- * @return: Masked and shifted value of the field defined by @__mask in @__val.
- */
-#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
-
-typedef struct {
- u32 reg;
-} i915_reg_t;
-
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-
-#define INVALID_MMIO_REG _MMIO(0)
-
-static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
-
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
-
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
-
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000
@@ -436,14 +350,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
#define GEN12_SFC_DONE_MAX 4
-#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
-#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
-#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
-#define PP_DIR_DCLV_2G 0xffffffff
-
-#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
-#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
-
#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
#define GEN8_RPCS_ENABLE (1 << 31)
#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
@@ -2541,71 +2447,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
#define BLT_RING_BASE 0x22000
-#define RING_TAIL(base) _MMIO((base) + 0x30)
-#define RING_HEAD(base) _MMIO((base) + 0x34)
-#define RING_START(base) _MMIO((base) + 0x38)
-#define RING_CTL(base) _MMIO((base) + 0x3c)
-#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
-#define RING_SYNC_0(base) _MMIO((base) + 0x40)
-#define RING_SYNC_1(base) _MMIO((base) + 0x44)
-#define RING_SYNC_2(base) _MMIO((base) + 0x48)
-#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
-#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
-#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
-#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
-#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
-#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
-#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
-#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
-#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
-#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
-#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
-#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
-#define GEN6_NOSYNC INVALID_MMIO_REG
-#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
-#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
-#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
-#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
-#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
-#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
-#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
-#define RING_ID(base) _MMIO((base) + 0x8c)
-#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
-
-#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
-/*
- * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
- * The lsb of each can be considered a separate enabling bit for encryption.
- * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
- * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
- * 15:14 == Reserved => 31:30 are set to 0.
- */
-#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
-#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
-#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
- CMD_CCTL_READ_OVERRIDE_MASK)
-#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
- (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
- REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
-
-#define BLIT_CCTL(base) _MMIO((base) + 0x204)
-#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
-#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
-#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
- BLIT_CCTL_SRC_MOCS_MASK)
-#define BLIT_CCTL_MOCS(dst, src) \
- (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
- REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
-
-#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
-#define RESET_CTL_CAT_ERROR REG_BIT(2)
-#define RESET_CTL_READY_TO_RESET REG_BIT(1)
-#define RESET_CTL_REQUEST_RESET REG_BIT(0)
-
-#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+
+
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
#define GTT_CACHE_EN_ALL 0xF0007FFF
@@ -2660,52 +2503,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
-#define RING_ACTHD(base) _MMIO((base) + 0x74)
-#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
-#define RING_NOPID(base) _MMIO((base) + 0x94)
-#define RING_IMR(base) _MMIO((base) + 0xa8)
-#define RING_HWSTAM(base) _MMIO((base) + 0x98)
-#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
-#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
-#define TAIL_ADDR 0x001FFFF8
-#define HEAD_WRAP_COUNT 0xFFE00000
-#define HEAD_WRAP_ONE 0x00200000
-#define HEAD_ADDR 0x001FFFFC
-#define RING_NR_PAGES 0x001FF000
-#define RING_REPORT_MASK 0x00000006
-#define RING_REPORT_64K 0x00000002
-#define RING_REPORT_128K 0x00000004
-#define RING_NO_REPORT 0x00000000
-#define RING_VALID_MASK 0x00000001
-#define RING_VALID 0x00000001
-#define RING_INVALID 0x00000000
-#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
-#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
-#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
#define GUCPMTIMESTAMP _MMIO(0xC3E8)
-/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
-#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
-#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
-
-#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
-#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
-#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
-#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
-#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
-#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
-#define RING_FORCE_TO_NONPRIV_MASK_VALID \
- (RING_FORCE_TO_NONPRIV_RANGE_MASK \
- | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
-#define RING_MAX_NONPRIV_SLOTS 12
-
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
@@ -2749,23 +2549,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
-#define RING_IPEIR(base) _MMIO((base) + 0x64)
-#define RING_IPEHR(base) _MMIO((base) + 0x68)
-#define RING_EIR(base) _MMIO((base) + 0xb0)
-#define RING_EMR(base) _MMIO((base) + 0xb4)
-#define RING_ESR(base) _MMIO((base) + 0xb8)
/*
* On GEN4, only the render ring INSTDONE exists and has a different
* layout than the GEN7+ version.
* The GEN2 counterpart of this register is GEN2_INSTDONE.
*/
-#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
-#define RING_INSTPS(base) _MMIO((base) + 0x70)
-#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
-#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
-#define RING_INSTPM(base) _MMIO((base) + 0xc0)
-#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
-#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
#define INSTPS _MMIO(0x2070) /* 965+ only */
#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
#define ACTHD_I965 _MMIO(0x2074)
@@ -2774,29 +2562,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define HWS_START_ADDRESS_SHIFT 4
#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
#define PWRCTX_EN (1 << 0)
-#define IPEIR(base) _MMIO((base) + 0x88)
-#define IPEHR(base) _MMIO((base) + 0x8c)
#define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094)
#define HWSTAM _MMIO(0x2098)
-#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
-#define RING_BBSTATE(base) _MMIO((base) + 0x110)
-#define RING_BB_PPGTT (1 << 5)
-#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
-#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
-#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
-#define RING_BBADDR(base) _MMIO((base) + 0x140)
-#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
-#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
-#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
-#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
-#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
-
-#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
-#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
-
-#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
-#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
#define ERROR_GEN6 _MMIO(0x40a0)
#define GEN7_ERR_INT _MMIO(0x44040)
@@ -2918,22 +2686,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
#define GFX_MODE _MMIO(0x2520)
-#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
-#define GFX_RUN_LIST_ENABLE (1 << 15)
-#define GFX_INTERRUPT_STEERING (1 << 14)
-#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
-#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
-#define GFX_REPLAY_MODE (1 << 11)
-#define GFX_PSMI_GRANULARITY (1 << 10)
-#define GFX_PPGTT_ENABLE (1 << 9)
-#define GEN8_GFX_PPGTT_48B (1 << 7)
-
-#define GFX_FORWARD_VBLANK_MASK (3 << 5)
-#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
-#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
-#define GFX_FORWARD_VBLANK_COND (2 << 5)
-
-#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
@@ -2974,7 +2726,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
#define INSTPM_TLB_INVALIDATE (1 << 9)
#define INSTPM_SYNC_FLUSH (1 << 5)
-#define ACTHD(base) _MMIO((base) + 0xc8)
#define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@ -3113,12 +2864,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
-#define ECOSKPD(base) _MMIO((base) + 0x1d0)
-#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
-#define ECO_GATING_CX_ONLY REG_BIT(3)
-#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
-#define ECO_FLIP_DONE REG_BIT(0)
-#define GEN6_BLITTER_LOCK_SHIFT 16
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -4181,10 +3926,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/*
* Logical Context regs
*/
-#define CCID(base) _MMIO((base) + 0x180)
-#define CCID_EN BIT(0)
-#define CCID_EXTENDED_STATE_RESTORE BIT(2)
-#define CCID_EXTENDED_STATE_SAVE BIT(3)
/*
* Notes on SNB/IVB/VLV context size:
* - Power context is saved elsewhere (LLC or stolen)
@@ -9289,8 +9030,6 @@ enum {
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
-#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
new file mode 100644
index 000000000000..5f64aa086ace
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_REG_DEFS__
+#define __I915_REG_DEFS__
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+
+/*
+ * Local integer constant expression version of is_power_of_2().
+ */
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
+
+/**
+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
+/**
+ * REG_FIELD_GET() - Extract a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+
+typedef struct {
+ u32 reg;
+} i915_reg_t;
+
+#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+
+#define INVALID_MMIO_REG _MMIO(0)
+
+static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
+{
+ return reg.reg;
+}
+
+static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
+{
+ return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
+}
+
+static inline bool i915_mmio_reg_valid(i915_reg_t reg)
+{
+ return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
+}
+
+
+#endif /* __I915_REG_DEFS__ */
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 76cf5ac91e94..5d94f86940f7 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -36,6 +36,7 @@
#include "gt/intel_context.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_reset.h"
#include "gt/intel_ring.h"
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 710dee28a014..4ecd995c5cc7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "display/intel_sprite.h"
#include "display/skl_universal_plane.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_llc.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index fc25ebf1a593..41d082213e81 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -23,7 +23,7 @@
#include <linux/pm_runtime.h>
-#include "gt/intel_lrc_reg.h" /* for shadow reg list */
+#include "gt/intel_engine_regs.h"
#include "i915_drv.h"
#include "i915_iosf_mbi.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY registers to their own header
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (5 preceding siblings ...)
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header Matt Roper
@ 2022-01-08 4:40 ` Matt Roper
2022-01-10 11:02 ` Jani Nikula
2022-01-08 5:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev2) Patchwork
` (3 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2022-01-08 4:40 UTC (permalink / raw)
To: intel-gfx
These registers are only needed in a couple files and on specific
platforms; let's keep them separate from the general register pool.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
.../drm/i915/display/intel_snps_phy_regs.h | 73 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 67 -----------------
3 files changed, 74 insertions(+), 67 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 09f405e4d363..718bfdbae9c8 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -10,6 +10,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_snps_phy.h"
+#include "intel_snps_phy_regs.h"
/**
* DOC: Synopsis PHY support
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
new file mode 100644
index 000000000000..484d3d204012
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_SNPS_REGS__
+#define __INTEL_SNPS_REGS__
+
+#define _SNPS_PHY_A_BASE 0x168000
+#define _SNPS_PHY_B_BASE 0x169000
+#define _SNPS_PHY(phy) _PHY(phy, \
+ _SNPS_PHY_A_BASE, \
+ _SNPS_PHY_B_BASE)
+#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
+ _SNPS_PHY_A_BASE + (reg))
+#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
+#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
+ (reg) + (ln) * 0x10))
+
+#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
+#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
+#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
+#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
+#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
+
+#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
+#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
+#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
+#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
+#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
+#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
+#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
+#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
+#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
+#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
+#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
+
+#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
+#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
+#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
+
+#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
+#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
+#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
+
+#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
+#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
+#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
+
+#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
+#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
+
+#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
+#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
+#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
+#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
+#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
+
+#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
+#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
+
+#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
+#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
+
+#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
+#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
+#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
+#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
+
+#endif /* __INTEL_SNPS_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ead30b47c69..5be5d0c28445 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2132,73 +2132,6 @@
#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
-/*
- * DG2 SNPS PHY registers (TC1 = PHY_E)
- */
-#define _SNPS_PHY_A_BASE 0x168000
-#define _SNPS_PHY_B_BASE 0x169000
-#define _SNPS_PHY(phy) _PHY(phy, \
- _SNPS_PHY_A_BASE, \
- _SNPS_PHY_B_BASE)
-#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
- _SNPS_PHY_A_BASE + (reg))
-#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
-#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
- (reg) + (ln) * 0x10))
-
-#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
-#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
-#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
-#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
-#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
-
-#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
-#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
-#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
-#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
-#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
-#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
-#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
-#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
-#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
-#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
-#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
-
-#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
-#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
-#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
-
-#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
-#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
-#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
-
-#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
-#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
-#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
-
-#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
-#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
-
-#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
-#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
-#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
-#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
-#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
-
-#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
-#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
-
-#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
-#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
-
-#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
-#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
-#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
-#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
-
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev2)
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (6 preceding siblings ...)
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY " Matt Roper
@ 2022-01-08 5:12 ` Patchwork
2022-01-08 5:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-01-08 5:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Start cleaning up register definitions (rev2)
URL : https://patchwork.freedesktop.org/series/98575/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bfe375c8c917 drm/i915: Use parameterized GPR register definitions everywhere
-:21: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#21: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:594:
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:594:
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'idx' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:594:
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
total: 1 errors, 0 warnings, 2 checks, 106 lines checked
2c2b1ae834c8 drm/i915: Parameterize PWRCTX_MAXCNT
f92aa7a2d6f3 drm/i915: Parameterize ECOSKPD
6013a2b958f8 drm/i915: Use RING_PSMI_CTL rather than per-engine macros
-:113: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:7658:
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-:122: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#122: FILE: drivers/gpu/drm/i915/intel_pm.c:7799:
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
total: 0 errors, 0 warnings, 2 checks, 89 lines checked
5fb66c826401 drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
10edc645bd23 drm/i915/gt: Move engine registers to their own header
-:66: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#66:
new file mode 100644
-:266: CHECK:LINE_SPACING: Please don't use multiple blank lines
#266: FILE: drivers/gpu/drm/i915/gt/intel_engine_regs.h:196:
+
+
-:740: CHECK:LINE_SPACING: Please don't use multiple blank lines
#740: FILE: drivers/gpu/drm/i915/i915_reg.h:2451:
+
+
-:940: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#940: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:20:
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
-:954: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#954: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:34:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:954: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#954: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:34:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:963: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__x' - possible side-effects?
#963: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:43:
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-:975: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#975: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:55:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:975: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#975: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:55:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:980: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#980: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:60:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:994: WARNING:NEW_TYPEDEFS: do not add new typedefs
#994: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:74:
+typedef struct {
-:1017: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1017: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:97:
+
+
total: 0 errors, 3 warnings, 9 checks, 866 lines checked
0a9e3b790fbc drm/i915: Move SNPS PHY registers to their own header
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#25:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 153 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Start cleaning up register definitions (rev2)
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (7 preceding siblings ...)
2022-01-08 5:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev2) Patchwork
@ 2022-01-08 5:13 ` Patchwork
2022-01-08 5:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-08 7:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-01-08 5:13 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Start cleaning up register definitions (rev2)
URL : https://patchwork.freedesktop.org/series/98575/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Start cleaning up register definitions (rev2)
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (8 preceding siblings ...)
2022-01-08 5:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-08 5:40 ` Patchwork
2022-01-08 7:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-01-08 5:40 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8345 bytes --]
== Series Details ==
Series: Start cleaning up register definitions (rev2)
URL : https://patchwork.freedesktop.org/series/98575/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11056 -> Patchwork_21945
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/index.html
Participating hosts (44 -> 36)
------------------------------
Additional (1): fi-icl-u2
Missing (9): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21945 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271]) +18 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-skl-6600u/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-snb-2520m/igt@amdgpu/amd_prime@i915-to-amd.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][7] -> [INCOMPLETE][8] ([i915#4785])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([i915#3301])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#1436] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [DMESG-FAIL][14] ([i915#3987]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][16] ([i915#3921]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-snb-2520m: [DMESG-FAIL][18] ([i915#4610]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-snb-2520m/igt@i915_selftest@live@requests.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-snb-2520m/igt@i915_selftest@live@requests.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][20] ([i915#4269]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][22] ([i915#295]) -> [PASS][23] +12 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [INCOMPLETE][24] ([i915#4547] / [i915#4838]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3970]: https://gitlab.freedesktop.org/drm/intel/issues/3970
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4610]: https://gitlab.freedesktop.org/drm/intel/issues/4610
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4838]: https://gitlab.freedesktop.org/drm/intel/issues/4838
Build changes
-------------
* Linux: CI_DRM_11056 -> Patchwork_21945
CI-20190529: 20190529
CI_DRM_11056: 3b0b6dd0cab7092febf204805d85700891a702fd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6325: ac29e097d4ff0f2e269a955ca86c5eb23908467a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21945: 0a9e3b790fbcd6f514050dbe1d94555cbdce96cc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0a9e3b790fbc drm/i915: Move SNPS PHY registers to their own header
10edc645bd23 drm/i915/gt: Move engine registers to their own header
5fb66c826401 drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
6013a2b958f8 drm/i915: Use RING_PSMI_CTL rather than per-engine macros
f92aa7a2d6f3 drm/i915: Parameterize ECOSKPD
2c2b1ae834c8 drm/i915: Parameterize PWRCTX_MAXCNT
bfe375c8c917 drm/i915: Use parameterized GPR register definitions everywhere
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/index.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Start cleaning up register definitions (rev2)
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
` (9 preceding siblings ...)
2022-01-08 5:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-08 7:00 ` Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-01-08 7:00 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30268 bytes --]
== Series Details ==
Series: Start cleaning up register definitions (rev2)
URL : https://patchwork.freedesktop.org/series/98575/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11056_full -> Patchwork_21945_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21945_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21945_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21945_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_workarounds@suspend-resume:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl4/igt@gem_workarounds@suspend-resume.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl3/igt@gem_workarounds@suspend-resume.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_create@create-massive:
- {shard-rkl}: [DMESG-WARN][5] ([i915#3002]) -> ([FAIL][6], [DMESG-WARN][7]) ([i915#3002])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@gem_create@create-massive.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@gem_create@create-massive.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-4/igt@gem_create@create-massive.html
* igt@gem_ctx_shared@q-smoketest@rcs0:
- {shard-rkl}: NOTRUN -> [INCOMPLETE][8] +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@gem_ctx_shared@q-smoketest@rcs0.html
* igt@gem_exec_flush@basic-wb-ro-before-default:
- {shard-rkl}: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@gem_exec_flush@basic-wb-ro-before-default.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@gem_exec_flush@basic-wb-ro-before-default.html
* igt@gem_exec_schedule@smoketest@bcs0:
- {shard-rkl}: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@gem_exec_schedule@smoketest@bcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@gem_exec_schedule@smoketest@bcs0.html
* igt@gem_flink_race@flink_close:
- {shard-rkl}: ([PASS][13], [PASS][14]) -> [INCOMPLETE][15]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@gem_flink_race@flink_close.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@gem_flink_race@flink_close.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@gem_flink_race@flink_close.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- {shard-rkl}: [SKIP][16] ([fdo#111827]) -> ([FAIL][17], [SKIP][18]) ([fdo#111827])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-4/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- {shard-rkl}: [SKIP][19] ([i915#4098]) -> ([FAIL][20], [SKIP][21]) ([i915#4098])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- {shard-rkl}: NOTRUN -> [FAIL][22] +7 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
Known issues
------------
Here are the changes found in Patchwork_21945_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_sseu@invalid-args:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271]) +69 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl6/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][24] -> [SKIP][25] ([i915#4525])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][26] -> [INCOMPLETE][27] ([i915#4547])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl1/igt@gem_exec_capture@pi@bcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl9/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][28] ([i915#2846])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#2846])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-glk3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][31] -> [FAIL][32] ([i915#2842])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#2842])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-apl: [PASS][35] -> [FAIL][36] ([i915#2842])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@heavy-random:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#4613]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@gem_lmem_swapping@heavy-random.html
* igt@gen9_exec_parse@unaligned-access:
- shard-iclb: NOTRUN -> [SKIP][38] ([i915#2856])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb7/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_pm_sseu@full-enable:
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#3650])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl10/igt@i915_pm_sseu@full-enable.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl9/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109303])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb5/igt@i915_query@query-topology-known-pci-ids.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][42] -> [DMESG-WARN][43] ([i915#118]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][44] ([i915#3743]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][45] ([i915#3763])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3777]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3777])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +11 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl8/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-kbl7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl6/igt@kms_chamelium@dp-edid-change-during-suspend.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-kbl6/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb5/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +20 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109274] / [fdo#109278])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#2346]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][58] -> [FAIL][59] ([i915#2122])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#79])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][62] -> [DMESG-WARN][63] ([i915#180]) +4 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][64] -> [INCOMPLETE][65] ([i915#4839])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl9/igt@kms_flip@flip-vs-suspend@b-edp1.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl10/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][66] ([i915#3701])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271]) +297 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109280] / [fdo#111825]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch:
- shard-skl: NOTRUN -> [FAIL][69] ([i915#1188])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [PASS][70] -> [DMESG-WARN][71] ([i915#180])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-apl2/igt@kms_hdr@bpc-switch-suspend.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl10/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: NOTRUN -> [DMESG-WARN][73] ([i915#180])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][75] ([i915#265])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][76] -> [FAIL][77] ([fdo#108145] / [i915#265])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][79] ([i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-b-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#3536])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb5/igt@kms_plane_lowres@pipe-b-tiling-x.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271]) +27 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-kbl7/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping:
- shard-skl: [PASS][82] -> [DMESG-WARN][83] ([i915#1982])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-skl9/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl10/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-scaler-with-clipping-clamping.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl7/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#109441])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][87] -> [SKIP][88] ([fdo#109441]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2437])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl8/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@blocking:
- shard-skl: NOTRUN -> [FAIL][90] ([i915#1542])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@perf@blocking.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109291])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb5/igt@prime_nv_pcopy@test3_2.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994]) +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-skl4/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][93] ([i915#2582]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@fbdev@unaligned-read.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: ([FAIL][95], [PASS][96]) ([i915#2410]) -> [PASS][97]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-6/igt@gem_ctx_persistence@many-contexts.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@gem_ctx_persistence@many-contexts.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-2/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][98] ([i915#3063] / [i915#3648]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-tglb6/igt@gem_eio@unwedge-stress.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb6/igt@gem_eio@unwedge-stress.html
- {shard-tglu}: [TIMEOUT][100] ([i915#3063] / [i915#3648]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-tglu-1/igt@gem_eio@unwedge-stress.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglu-5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@bonded-pair:
- {shard-tglu}: [FAIL][102] ([i915#1888]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-tglu-2/igt@gem_exec_balancer@bonded-pair.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglu-5/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@nop:
- {shard-rkl}: [INCOMPLETE][104] -> [PASS][105] +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-5/igt@gem_exec_balancer@nop.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-2/igt@gem_exec_balancer@nop.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][106] ([i915#4525]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][108] ([i915#2842]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-apl: [FAIL][110] ([i915#2842]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-apl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][112] ([i915#2842]) -> [PASS][113] +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][114] ([i915#2849]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@smoketest@rcs0:
- {shard-rkl}: ([PASS][116], [INCOMPLETE][117]) -> [PASS][118]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@gem_exec_schedule@smoketest@rcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-5/igt@gem_exec_schedule@smoketest@rcs0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-5/igt@gem_exec_schedule@smoketest@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][119] ([i915#2190]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-tglb2/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][121] ([i915#454]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][123] ([i915#4281]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
- {shard-rkl}: [SKIP][125] ([i915#1845]) -> [PASS][126] +16 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- {shard-rkl}: ([SKIP][127], [SKIP][128]) ([i915#1845] / [i915#4098]) -> [PASS][129] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-5/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][130] ([i915#1845] / [i915#4098]) -> [PASS][131] +3 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- {shard-rkl}: [SKIP][132] ([i915#1149] / [i915#4098]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@kms_color@pipe-a-ctm-red-to-blue.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_color@pipe-b-ctm-0-25:
- {shard-rkl}: [SKIP][134] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-25.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_color@pipe-b-ctm-0-75:
- {shard-rkl}: [SKIP][136] ([i915#1149] / [i915#1849]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-5/igt@kms_color@pipe-b-ctm-0-75.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_concurrent@pipe-b:
- {shard-rkl}: [SKIP][138] ([i915#1845] / [i915#4070]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@kms_concurrent@pipe-b.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_concurrent@pipe-b.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-random:
- {shard-rkl}: ([SKIP][140], [SKIP][141]) ([fdo#112022] / [i915#4070]) -> [PASS][142]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-random:
- {shard-rkl}: [SKIP][143] ([fdo#112022] / [i915#4070]) -> [PASS][144] +3 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-snb: [SKIP][145] ([fdo#109271]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11056/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21945/index.html
[-- Attachment #2: Type: text/html, Size: 33240 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header Matt Roper
@ 2022-01-10 10:59 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 10:59 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> Let's start breaking up and cleaning up the massive i915_reg.h file.
> We'll start by moving all registers that are defined in relation to an
> engine base to their own header.
>
> There are probably a bunch of other "engine registers" that we haven't
> moved yet (especially those that belong to the render engine in the
> 0x2??? range), but this is a relatively straightforward first step.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 +
> drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 1 +
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 197 +++++++++++++
> .../drm/i915/gt/intel_execlists_submission.c | 1 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 15 -
> drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
> drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
> drivers/gpu/drm/i915/gt/intel_ring.c | 1 +
> .../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_rps.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
> drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
> drivers/gpu/drm/i915/gvt/mmio_context.h | 1 +
> drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
> drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
> drivers/gpu/drm/i915/i915_perf.c | 1 +
> drivers/gpu/drm/i915/i915_pmu.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 267 +-----------------
> drivers/gpu/drm/i915/i915_reg_defs.h | 98 +++++++
I think I would've liked to see this file split up as a separate prep
patch.
BR,
Jani.
> drivers/gpu/drm/i915/i915_request.c | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 32 files changed, 327 insertions(+), 281 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_regs.h
> create mode 100644 drivers/gpu/drm/i915/i915_reg_defs.h
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY registers to their own header
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY " Matt Roper
@ 2022-01-10 11:02 ` Jani Nikula
2022-01-10 11:03 ` Jani Nikula
0 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:02 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> These registers are only needed in a couple files and on specific
> platforms; let's keep them separate from the general register pool.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
> .../drm/i915/display/intel_snps_phy_regs.h | 73 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 67 -----------------
> 3 files changed, 74 insertions(+), 67 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 09f405e4d363..718bfdbae9c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -10,6 +10,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_snps_phy.h"
> +#include "intel_snps_phy_regs.h"
>
> /**
> * DOC: Synopsis PHY support
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
> new file mode 100644
> index 000000000000..484d3d204012
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_SNPS_REGS__
> +#define __INTEL_SNPS_REGS__
#include "i915_reg_defs.h"
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +
> +#define _SNPS_PHY_A_BASE 0x168000
> +#define _SNPS_PHY_B_BASE 0x169000
> +#define _SNPS_PHY(phy) _PHY(phy, \
> + _SNPS_PHY_A_BASE, \
> + _SNPS_PHY_B_BASE)
> +#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
> + _SNPS_PHY_A_BASE + (reg))
> +#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
> +#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
> + (reg) + (ln) * 0x10))
> +
> +#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
> +#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
> +#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
> +#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
> +#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
> +
> +#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
> +#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
> +#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
> +#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
> +#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
> +#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
> +#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
> +#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
> +#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
> +#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
> +#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
> +#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
> +
> +#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
> +#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
> +#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
> +#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
> +
> +#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
> +#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
> +#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
> +
> +#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
> +#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
> +#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
> +#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
> +
> +#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
> +#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
> +
> +#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
> +#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
> +#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
> +#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
> +#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
> +
> +#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
> +#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
> +
> +#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
> +#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
> +
> +#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
> +#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
> +#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
> +#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
> +
> +#endif /* __INTEL_SNPS_REGS__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8ead30b47c69..5be5d0c28445 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2132,73 +2132,6 @@
> #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
>
> -/*
> - * DG2 SNPS PHY registers (TC1 = PHY_E)
> - */
> -#define _SNPS_PHY_A_BASE 0x168000
> -#define _SNPS_PHY_B_BASE 0x169000
> -#define _SNPS_PHY(phy) _PHY(phy, \
> - _SNPS_PHY_A_BASE, \
> - _SNPS_PHY_B_BASE)
> -#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
> - _SNPS_PHY_A_BASE + (reg))
> -#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
> -#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
> - (reg) + (ln) * 0x10))
> -
> -#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
> -#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
> -#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
> -#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
> -#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
> -
> -#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
> -#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
> -#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
> -#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
> -#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
> -#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
> -#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
> -#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
> -#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
> -#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
> -#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
> -#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
> -
> -#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
> -#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
> -#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
> -#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
> -
> -#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
> -#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
> -#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
> -
> -#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
> -#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
> -#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
> -#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
> -
> -#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
> -#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
> -
> -#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
> -#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
> -#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
> -#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
> -#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
> -
> -#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
> -#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
> -
> -#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
> -#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
> -
> -#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
> -#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
> -#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
> -#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
> -
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
> */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY registers to their own header
2022-01-10 11:02 ` Jani Nikula
@ 2022-01-10 11:03 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:03 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Mon, 10 Jan 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
>> These registers are only needed in a couple files and on specific
>> platforms; let's keep them separate from the general register pool.
>>
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
>> .../drm/i915/display/intel_snps_phy_regs.h | 73 +++++++++++++++++++
>> drivers/gpu/drm/i915/i915_reg.h | 67 -----------------
>> 3 files changed, 74 insertions(+), 67 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> index 09f405e4d363..718bfdbae9c8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> @@ -10,6 +10,7 @@
>> #include "intel_de.h"
>> #include "intel_display_types.h"
>> #include "intel_snps_phy.h"
>> +#include "intel_snps_phy_regs.h"
>>
>> /**
>> * DOC: Synopsis PHY support
>> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
>> new file mode 100644
>> index 000000000000..484d3d204012
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
>> @@ -0,0 +1,73 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_SNPS_REGS__
>> +#define __INTEL_SNPS_REGS__
Oh, nitpick, the include guard does not match the file name.
>
> #include "i915_reg_defs.h"
>
> Other than that,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> +
>> +#define _SNPS_PHY_A_BASE 0x168000
>> +#define _SNPS_PHY_B_BASE 0x169000
>> +#define _SNPS_PHY(phy) _PHY(phy, \
>> + _SNPS_PHY_A_BASE, \
>> + _SNPS_PHY_B_BASE)
>> +#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
>> + _SNPS_PHY_A_BASE + (reg))
>> +#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
>> +#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
>> + (reg) + (ln) * 0x10))
>> +
>> +#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
>> +#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
>> +#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
>> +#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
>> +#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
>> +
>> +#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
>> +#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
>> +#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
>> +#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
>> +#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
>> +#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
>> +#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
>> +#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
>> +#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
>> +#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
>> +#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
>> +#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
>> +
>> +#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
>> +#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
>> +#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
>> +#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
>> +
>> +#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
>> +#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
>> +#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
>> +
>> +#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
>> +#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
>> +#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
>> +#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
>> +
>> +#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
>> +#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
>> +
>> +#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
>> +#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
>> +#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
>> +#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
>> +#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
>> +
>> +#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
>> +#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
>> +
>> +#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
>> +#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
>> +
>> +#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
>> +#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
>> +#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
>> +#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
>> +
>> +#endif /* __INTEL_SNPS_REGS__ */
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8ead30b47c69..5be5d0c28445 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2132,73 +2132,6 @@
>> #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
>> #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
>>
>> -/*
>> - * DG2 SNPS PHY registers (TC1 = PHY_E)
>> - */
>> -#define _SNPS_PHY_A_BASE 0x168000
>> -#define _SNPS_PHY_B_BASE 0x169000
>> -#define _SNPS_PHY(phy) _PHY(phy, \
>> - _SNPS_PHY_A_BASE, \
>> - _SNPS_PHY_B_BASE)
>> -#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
>> - _SNPS_PHY_A_BASE + (reg))
>> -#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
>> -#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
>> - (reg) + (ln) * 0x10))
>> -
>> -#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
>> -#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
>> -#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
>> -#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
>> -#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
>> -
>> -#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
>> -#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
>> -#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
>> -#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
>> -#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
>> -#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
>> -#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
>> -#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
>> -#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
>> -#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
>> -#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
>> -#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
>> -
>> -#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
>> -#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
>> -#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
>> -#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
>> -
>> -#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
>> -#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
>> -#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
>> -
>> -#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
>> -#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
>> -#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
>> -#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
>> -
>> -#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
>> -#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
>> -
>> -#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
>> -#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
>> -#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
>> -#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
>> -#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
>> -
>> -#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
>> -#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
>> -
>> -#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
>> -#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
>> -
>> -#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
>> -#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
>> -#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
>> -#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
>> -
>> /* The spec defines this only for BXT PHY0, but lets assume that this
>> * would exist for PHY1 too if it had a second channel.
>> */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
@ 2022-01-10 11:06 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:06 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> Rather than having separate definitions for each engine, create a single
> parameterized macro that takes the engine base offset. This will also
> ensure we get to the proper offset if we ever need to use these
> registers on newer platforms (where the media engine offsets have
> changed).
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++----
> drivers/gpu/drm/i915/i915_reg.h | 6 +-----
> 2 files changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index c3155ee58689..45891e6f0b98 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
> enable_rc6 = false;
> }
>
> - if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
> - (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
> - (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
> - (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
> + if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
> + (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
> + (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
> + (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
> drm_dbg(&i915->drm,
> "Engine Idle wait time not set properly.\n");
> enable_rc6 = false;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 86e459010465..23330faecf07 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9297,11 +9297,7 @@ enum {
> #define RC6_CTX_IN_DRAM (1 << 0)
> #define RC6_CTX_BASE _MMIO(0xD48)
> #define RC6_CTX_BASE_MASK 0xFFFFFFF0
> -#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
> -#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
> -#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
> -#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
> -#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
> +#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
> #define IDLE_TIME_MASK 0xFFFFF
> #define FORCEWAKE _MMIO(0xA18C)
> #define FORCEWAKE_VLV _MMIO(0x1300b0)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD Matt Roper
@ 2022-01-10 11:10 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:10 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> Combine the separate render and blitter register definitions into a
> single definition. We already know we have some workarounds on an
> upcoming platform that will need to update the ECOSKPD register for
> other engines too, so this helps pave the way for that.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 14 ++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> 4 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ab3277a3d593..2d87dc81cd63 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2536,7 +2536,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> * they are already accustomed to from before contexts were
> * enabled.
> */
> - wa_add(wal, ECOSKPD,
> + wa_add(wal, ECOSKPD(RENDER_RING_BASE),
> 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
> 0 /* XXX bit doesn't stick on Broadwater */,
> true);
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 3938df0db188..329d30a36f4f 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2877,9 +2877,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>
> MMIO_D(_MMIO(0x3c), D_ALL);
> MMIO_D(_MMIO(0x860), D_ALL);
> - MMIO_D(ECOSKPD, D_ALL);
> + MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
> MMIO_D(_MMIO(0x121d0), D_ALL);
> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> + MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
> MMIO_D(_MMIO(0x41d0), D_ALL);
> MMIO_D(GAC_ECO_BITS, D_ALL);
> MMIO_D(_MMIO(0x6200), D_ALL);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 23330faecf07..5b1f93112001 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3107,10 +3107,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
> #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
> #define GFX_FLSH_CNTL_EN (1 << 0)
> -#define ECOSKPD _MMIO(0x21d0)
> -#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> -#define ECO_GATING_CX_ONLY (1 << 3)
> -#define ECO_FLIP_DONE (1 << 0)
> +#define ECOSKPD(base) _MMIO((base) + 0x1d0)
> +#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> +#define ECO_GATING_CX_ONLY REG_BIT(3)
> +#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
> +#define ECO_FLIP_DONE REG_BIT(0)
> +#define GEN6_BLITTER_LOCK_SHIFT 16
>
> #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
> #define RC_OP_FLUSH_ENABLE (1 << 0)
> @@ -3120,10 +3122,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
>
> -#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
> -#define GEN6_BLITTER_LOCK_SHIFT 16
> -#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
> -
> #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
> #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8b357ec35a4a..2d0955d13776 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7868,10 +7868,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
> intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
>
> if (IS_PINEVIEW(dev_priv))
> - intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> + intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> + _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
>
> /* IIR "flip pending" means done if this bit is set */
> - intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> + intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> + _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
>
> /* interrupts should cause a wake up from C3 */
> intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
@ 2022-01-10 11:14 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:14 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> We have a parameterized macro for RING_PSMI_CTL; let's use that instead
> of the per-engine definitions where possible.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/gt/intel_ring_submission.c | 10 +++++-----
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 19 +++++++------------
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 4 files changed, 15 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 3e6fac0340ef..56c009ecfdf2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1002,15 +1002,15 @@ static void gen6_bsd_submit_request(struct i915_request *request)
> /* Disable notification that the ring is IDLE. The GT
> * will then assume that it is busy and bring it out of rc6.
> */
> - intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
> - _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
> + intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
> + _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
>
> /* Clear the context id. Here be magic! */
> intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
>
> /* Wait for the ring not to be idle, i.e. for it to wake up. */
> if (__intel_wait_for_register_fw(uncore,
> - GEN6_BSD_SLEEP_PSMI_CONTROL,
> + RING_PSMI_CTL(GEN6_BSD_RING_BASE),
> GEN6_BSD_SLEEP_INDICATOR,
> 0,
> 1000, 0, NULL))
> @@ -1023,8 +1023,8 @@ static void gen6_bsd_submit_request(struct i915_request *request)
> /* Let the ring send IDLE messages to the GT again,
> * and so let it sleep to conserve power when idle.
> */
> - intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
> - _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
> + intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
> + _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
>
> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2d87dc81cd63..977619ea839a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2208,7 +2208,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> * For DG1 this only applies to A0.
> */
> wa_masked_en(wal,
> - GEN6_RC_SLEEP_PSMI_CONTROL,
> + RING_PSMI_CTL(RENDER_RING_BASE),
> GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
> GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b1f93112001..b227a1e58f9b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2563,6 +2563,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
> #define GEN6_NOSYNC INVALID_MMIO_REG
> #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
> +#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
> +#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
> +#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> +#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
> +#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
> +#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
> +#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
> #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
> #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
> #define RING_ID(base) _MMIO((base) + 0x8c)
> @@ -3122,12 +3129,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
>
> -#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
> -#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
> -#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> -#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
> -#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
> -
> #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
> #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
>
> @@ -3213,12 +3214,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define XEHP_EU_ENABLE _MMIO(0x9134)
> #define XEHP_EU_ENA_MASK 0xFF
>
> -#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
> -#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
> -#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
> -#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
> -#define GEN6_BSD_GO_INDICATOR (1 << 4)
> -
> /* On modern GEN architectures interrupt control consists of two sets
> * of registers. The first set pertains to the ring generating the
> * interrupt. The second control is for the functional block generating the
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d0955d13776..710dee28a014 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7654,7 +7654,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
> intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
> ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
>
> - intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
> + intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
> _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>
> /* WaDisableSDEUnitClockGating:bdw */
> @@ -7795,7 +7795,7 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
> ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
>
> /* WaDisableSemaphoreAndSyncFlipWait:chv */
> - intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
> + intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
> _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>
> /* WaDisableCSUnitClockGating:chv */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
@ 2022-01-10 11:15 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:15 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> It's preferable to use parameterized register macros where possible.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 977619ea839a..895939a941d6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2423,7 +2423,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (GRAPHICS_VER(i915) == 7) {
> /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> wa_masked_en(wal,
> - GFX_MODE_GEN7,
> + RING_MODE_GEN7(RENDER_RING_BASE),
> GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
>
> /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index f776c470914d..abc81cdc9e5d 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -44,7 +44,7 @@
>
> /* Raw offset is appened to each line for convenience. */
> static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
> - {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
> + {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
> {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
> {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
> {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
> @@ -76,7 +76,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
> };
>
> static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> - {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
> + {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
> {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
> {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
> {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b227a1e58f9b..7f0168ba55f2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2918,7 +2918,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
>
> #define GFX_MODE _MMIO(0x2520)
> -#define GFX_MODE_GEN7 _MMIO(0x229c)
> #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
> #define GFX_RUN_LIST_ENABLE (1 << 15)
> #define GFX_INTERRUPT_STEERING (1 << 14)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
@ 2022-01-10 11:20 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-01-10 11:20 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> Since we have an engine-parameterized macro GEN8_RING_CS_GPR, let's use
> that in place of the HSW_CS_GPR and BCS_GPR register definitions.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 68 ++++++++++++++------------
> drivers/gpu/drm/i915/i915_reg.h | 8 ---
> 2 files changed, 36 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index e0403ce9ce69..20191a32478a 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -591,6 +591,10 @@ struct drm_i915_reg_descriptor {
> { .addr = _reg(idx) }, \
> { .addr = _reg ## _UDW(idx) }
>
> +#define REG64_BASE_IDX(_reg, base, idx) \
> + { .addr = _reg(base, idx) }, \
> + { .addr = _reg ## _UDW(base, idx) }
> +
> static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> REG64(GPGPU_THREADS_DISPATCHED),
> REG64(HS_INVOCATION_COUNT),
> @@ -636,22 +640,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> };
>
> static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
> - REG64_IDX(HSW_CS_GPR, 0),
> - REG64_IDX(HSW_CS_GPR, 1),
> - REG64_IDX(HSW_CS_GPR, 2),
> - REG64_IDX(HSW_CS_GPR, 3),
> - REG64_IDX(HSW_CS_GPR, 4),
> - REG64_IDX(HSW_CS_GPR, 5),
> - REG64_IDX(HSW_CS_GPR, 6),
> - REG64_IDX(HSW_CS_GPR, 7),
> - REG64_IDX(HSW_CS_GPR, 8),
> - REG64_IDX(HSW_CS_GPR, 9),
> - REG64_IDX(HSW_CS_GPR, 10),
> - REG64_IDX(HSW_CS_GPR, 11),
> - REG64_IDX(HSW_CS_GPR, 12),
> - REG64_IDX(HSW_CS_GPR, 13),
> - REG64_IDX(HSW_CS_GPR, 14),
> - REG64_IDX(HSW_CS_GPR, 15),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
> REG32(HSW_SCRATCH1,
> .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
> .value = 0),
> @@ -674,22 +678,22 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
> REG32(BCS_SWCTRL),
> REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
> REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
> - REG64_IDX(BCS_GPR, 0),
> - REG64_IDX(BCS_GPR, 1),
> - REG64_IDX(BCS_GPR, 2),
> - REG64_IDX(BCS_GPR, 3),
> - REG64_IDX(BCS_GPR, 4),
> - REG64_IDX(BCS_GPR, 5),
> - REG64_IDX(BCS_GPR, 6),
> - REG64_IDX(BCS_GPR, 7),
> - REG64_IDX(BCS_GPR, 8),
> - REG64_IDX(BCS_GPR, 9),
> - REG64_IDX(BCS_GPR, 10),
> - REG64_IDX(BCS_GPR, 11),
> - REG64_IDX(BCS_GPR, 12),
> - REG64_IDX(BCS_GPR, 13),
> - REG64_IDX(BCS_GPR, 14),
> - REG64_IDX(BCS_GPR, 15),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
> + REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
> };
>
> #undef REG64
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e20e832162b4..86e459010465 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -599,10 +599,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define BCS_SRC_Y REG_BIT(0)
> #define BCS_DST_Y REG_BIT(1)
>
> -/* There are 16 GPR registers */
> -#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
> -#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
> -
> #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
> #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
> #define HS_INVOCATION_COUNT _MMIO(0x2300)
> @@ -646,10 +642,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
> #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
>
> -/* There are the 16 64-bit CS General Purpose Registers */
> -#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
> -#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
> -
> #define GEN7_OACONTROL _MMIO(0x2360)
> #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
> #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-01-10 11:20 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-08 4:40 [Intel-gfx] [PATCH v2 0/7] Start cleaning up register definitions Matt Roper
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-10 11:20 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
2022-01-10 11:06 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Parameterize ECOSKPD Matt Roper
2022-01-10 11:10 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
2022-01-10 11:14 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
2022-01-10 11:15 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 6/7] drm/i915/gt: Move engine registers to their own header Matt Roper
2022-01-10 10:59 ` Jani Nikula
2022-01-08 4:40 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Move SNPS PHY " Matt Roper
2022-01-10 11:02 ` Jani Nikula
2022-01-10 11:03 ` Jani Nikula
2022-01-08 5:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev2) Patchwork
2022-01-08 5:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-08 5:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-08 7:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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