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From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
	<libvir-list@redhat.com>, <anup@brainfault.org>,
	<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
	<bin.meng@windriver.com>, <fanliang@huawei.com>,
	<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
	<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
	Mingwang Li <limingwang@huawei.com>,
	Anup Patel <anup.patel@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v4 12/12] target/riscv: Support virtual time context synchronization
Date: Mon, 10 Jan 2022 09:38:31 +0800	[thread overview]
Message-ID: <20220110013831.1594-13-jiangyifei@huawei.com> (raw)
In-Reply-To: <20220110013831.1594-1-jiangyifei@huawei.com>

Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ad8248ebfd..95eb82792a 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,6 +164,35 @@ static const VMStateDescription vmstate_pointermasking = {
     }
 };
 
+static bool kvmtimer_needed(void *opaque)
+{
+    return kvm_enabled();
+}
+
+static int cpu_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    env->kvm_timer_dirty = true;
+    return 0;
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+    .name = "cpu/kvmtimer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = kvmtimer_needed,
+    .post_load = cpu_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 3,
@@ -218,6 +247,7 @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_hyper,
         &vmstate_vector,
         &vmstate_pointermasking,
+        &vmstate_kvmtimer,
         NULL
     }
 };
-- 
2.19.1


WARNING: multiple messages have this Message-ID (diff)
From: Yifei Jiang via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
	<libvir-list@redhat.com>, <anup@brainfault.org>,
	<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
	<bin.meng@windriver.com>, <fanliang@huawei.com>,
	<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
	<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
	Mingwang Li <limingwang@huawei.com>,
	Anup Patel <anup.patel@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v4 12/12] target/riscv: Support virtual time context synchronization
Date: Mon, 10 Jan 2022 09:38:31 +0800	[thread overview]
Message-ID: <20220110013831.1594-13-jiangyifei@huawei.com> (raw)
In-Reply-To: <20220110013831.1594-1-jiangyifei@huawei.com>

Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ad8248ebfd..95eb82792a 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,6 +164,35 @@ static const VMStateDescription vmstate_pointermasking = {
     }
 };
 
+static bool kvmtimer_needed(void *opaque)
+{
+    return kvm_enabled();
+}
+
+static int cpu_post_load(void *opaque, int version_id)
+{
+    RISCVCPU *cpu = opaque;
+    CPURISCVState *env = &cpu->env;
+
+    env->kvm_timer_dirty = true;
+    return 0;
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+    .name = "cpu/kvmtimer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = kvmtimer_needed,
+    .post_load = cpu_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+        VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
     .version_id = 3,
@@ -218,6 +247,7 @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_hyper,
         &vmstate_vector,
         &vmstate_pointermasking,
+        &vmstate_kvmtimer,
         NULL
     }
 };
-- 
2.19.1



  parent reply	other threads:[~2022-01-10  1:39 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-10  1:38 [PATCH v4 00/12] Add riscv kvm accel support Yifei Jiang
2022-01-10  1:38 ` Yifei Jiang via
2022-01-10  1:38 ` [PATCH v4 01/12] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  1:38 ` [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10 23:09   ` Alistair Francis
2022-01-10 23:09     ` Alistair Francis
2022-01-12  8:04     ` Jiangyifei
2022-01-12  8:04       ` Jiangyifei via
2022-01-10  1:38 ` [PATCH v4 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  1:38 ` [PATCH v4 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  1:38 ` [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10 23:06   ` Alistair Francis
2022-01-10 23:06     ` Alistair Francis
2022-01-12  8:01     ` Jiangyifei
2022-01-12  8:01       ` Jiangyifei via
2022-01-10  1:38 ` [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-11  0:27   ` Alistair Francis
2022-01-11  0:27     ` Alistair Francis
2022-01-12  8:07     ` Jiangyifei
2022-01-12  8:07       ` Jiangyifei via
2022-01-10  1:38 ` [PATCH v4 07/12] target/riscv: Support setting external interrupt " Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  1:38 ` [PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  6:48   ` Alistair Francis
2022-01-10  6:48     ` Alistair Francis
2022-01-10  1:38 ` [PATCH v4 09/12] target/riscv: Add host cpu type Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  1:38 ` [PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  6:52   ` Alistair Francis
2022-01-10  6:52     ` Alistair Francis
2022-01-10  1:38 ` [PATCH v4 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2022-01-10  1:38   ` Yifei Jiang via
2022-01-10  1:38 ` Yifei Jiang [this message]
2022-01-10  1:38   ` [PATCH v4 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang via

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