* [PATCH v9 01/14] crypto/fsl: Add support for CAAM Job ring driver model
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
` (12 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
added device tree support for job ring driver.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
drivers/crypto/fsl/Kconfig | 1 +
drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++-------------
drivers/crypto/fsl/jr.h | 31 +++-
3 files changed, 241 insertions(+), 114 deletions(-)
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 94ff540111..231eb00b5f 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -2,6 +2,7 @@ config FSL_CAAM
bool "Freescale Crypto Driver Support"
select SHA_HW_ACCEL
# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
+ select MISC if DM
imply SPL_CRYPTO if (ARM && SPL)
imply CMD_HASH
help
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 22b649219e..8103987425 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
* Based on CAAM driver in drivers/crypto/caam in Linux
*/
@@ -11,7 +11,6 @@
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
-#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -21,7 +20,10 @@
#include <asm/cache.h>
#include <asm/fsl_pamu.h>
#endif
+#include <dm.h>
#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
#include <linux/delay.h>
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
@@ -35,20 +37,29 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
#endif
};
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+struct caam_regs caam_st;
+#endif
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+ return (1 << jrid);
+}
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ ccsr_sec_t *sec = caam->sec;
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
+ u32 jrstart = jr_start_reg(caam->jrid);
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -56,23 +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
*/
if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
(scfgr & SEC_SCFGR_VIRT_EN))
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
} else {
/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
}
}
-static inline void jr_reset_liodn(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
@@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
@@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
sec_out32(®s->irs, JR_SIZE);
if (!jr->irq)
- jr_disable_irq(sec_idx);
+ jr_disable_irq(regs);
}
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jobring *jr = &jr0[sec_idx];
+ struct jobring *jr = &caam->jr[sec_idx];
memset(jr, 0, sizeof(struct jobring));
- jr->jq_id = DEFAULT_JR_ID;
+ jr->jq_id = caam->jrid;
jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
@@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
- start_jr0(sec_idx);
-
- jr_initregs(sec_idx);
-
- return 0;
-}
-
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
- struct jobring *jr = &jr0[sec_idx];
-
- jr->head = 0;
- jr->tail = 0;
- jr->read_idx = 0;
- jr->write_idx = 0;
- memset(jr->info, 0, sizeof(jr->info));
- memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
- memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
- return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- uint32_t timeout = 100000;
- uint32_t jrint, jrcr;
-
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrint = sec_in32(®s->jrint);
- } while (((jrint & JRINT_ERR_HALT_MASK) ==
- JRINT_ERR_HALT_INPROGRESS) && --timeout);
-
- jrint = sec_in32(®s->jrint);
- if (((jrint & JRINT_ERR_HALT_MASK) !=
- JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
- return -1;
-
- timeout = 100000;
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrcr = sec_in32(®s->jrcr);
- } while ((jrcr & JRCR_RESET) && --timeout);
-
- if (timeout == 0)
- return -1;
+ start_jr(caam);
+ jr_initregs(sec_idx, caam);
return 0;
}
@@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
void (*callback)(uint32_t status, void *arg),
- void *arg, uint8_t sec_idx)
+ void *arg, uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
uint32_t desc_word;
int length = desc_len(desc_addr);
@@ -263,10 +222,10 @@ static int jr_enqueue(uint32_t *desc_addr,
return 0;
}
-static int jr_dequeue(int sec_idx)
+static int jr_dequeue(int sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
int tail = jr->tail;
int idx, i, found;
@@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
{
struct result *x = arg;
x->status = status;
-#ifndef CONFIG_SPL_BUILD
caam_jr_strstatus(status);
-#endif
x->done = 1;
}
static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
unsigned long long timeval = 0;
unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
struct result op;
@@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
memset(&op, 0, sizeof(op));
- ret = jr_enqueue(desc, desc_done, &op, sec_idx);
+ ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
if (ret) {
debug("Error in SEC enq\n");
ret = JQ_ENQ_ERR;
@@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
udelay(1);
timeval += 1;
- ret = jr_dequeue(sec_idx);
+ ret = jr_dequeue(sec_idx, caam);
if (ret) {
debug("Error in SEC deq\n");
ret = JQ_DEQ_ERR;
@@ -402,13 +365,62 @@ int run_descriptor_jr(uint32_t *desc)
return run_descriptor_jr_idx(desc, 0);
}
+static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
+{
+ struct jobring *jr = &caam->jr[sec_idx];
+
+ jr->head = 0;
+ jr->tail = 0;
+ jr->read_idx = 0;
+ jr->write_idx = 0;
+ memset(jr->info, 0, sizeof(jr->info));
+ memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
+ memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
+
+ return 0;
+}
+
+static int jr_hw_reset(struct jr_regs *regs)
+{
+ uint32_t timeout = 100000;
+ uint32_t jrint, jrcr;
+
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrint = sec_in32(®s->jrint);
+ } while (((jrint & JRINT_ERR_HALT_MASK) ==
+ JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+ jrint = sec_in32(®s->jrint);
+ if (((jrint & JRINT_ERR_HALT_MASK) !=
+ JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+ return -1;
+
+ timeout = 100000;
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrcr = sec_in32(®s->jrcr);
+ } while ((jrcr & JRCR_RESET) && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
static inline int jr_reset_sec(uint8_t sec_idx)
{
- if (jr_hw_reset(sec_idx) < 0)
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ if (jr_hw_reset(caam->regs) < 0)
return -1;
/* Clean up the jobring structure maintained by software */
- jr_sw_cleanup(sec_idx);
+ jr_sw_cleanup(sec_idx, caam);
return 0;
}
@@ -418,9 +430,15 @@ int jr_reset(void)
return jr_reset_sec(0);
}
-static inline int sec_reset_idx(uint8_t sec_idx)
+int sec_reset(void)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
uint32_t mcfgr = sec_in32(&sec->mcfgr);
uint32_t timeout = 100000;
@@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t sec_idx)
return 0;
}
-int sec_reset(void)
-{
- return sec_reset_idx(0);
-}
-#ifndef CONFIG_SPL_BUILD
+
static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
{
u32 *desc;
@@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
return ret;
}
-static int instantiate_rng(u8 sec_idx, int gen_sk)
+static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
{
u32 *desc;
u32 rdsta_val;
int ret = 0, sh_idx, size;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
@@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
return ret;
}
-static u8 get_rng_vid(uint8_t sec_idx)
+static u8 get_rng_vid(ccsr_sec_t *sec)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u8 vid;
if (caam_get_era() < 10) {
@@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
* By default, the TRNG runs for 200 clocks per sample;
* 1200 clocks per sample generates better entropy.
*/
-static void kick_trng(int ent_delay, uint8_t sec_idx)
+static void kick_trng(int ent_delay, ccsr_sec_t *sec)
{
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 val;
@@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
-static int rng_init(uint8_t sec_idx)
+static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
{
int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 inst_handles;
@@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
* the TRNG parameters.
*/
if (!inst_handles) {
- kick_trng(ent_delay, sec_idx);
+ kick_trng(ent_delay, sec);
ent_delay += 400;
}
/*
@@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng(sec_idx, gen_sk);
+ ret = instantiate_rng(sec_idx, sec, gen_sk);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
@@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx)
return ret;
}
-#endif
+
int sec_init_idx(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
-
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ if (!caam_dev) {
+ printf("caam_jr: caam not found\n");
+ return -1;
+ }
+ caam = dev_get_priv(caam_dev);
+#else
+ caam_st.sec = (void *)SEC_ADDR(sec_idx);
+ caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ caam_st.jrid = 0;
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
+ uint32_t mcr = sec_in32(&sec->mcfgr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ uint32_t jrdid_ms = 0;
+#endif
#ifdef CONFIG_FSL_CORENET
uint32_t liodnr;
uint32_t liodn_ns;
@@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
+ sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
+#endif
+ jr_reset();
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SPL_BUILD
@@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
- liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
~(JRNSLIODN_MASK | JRSLIODN_MASK);
liodnr = liodnr |
(liodn_ns << JRNSLIODN_SHIFT) |
(liodn_s << JRSLIODN_SHIFT);
- sec_out32(&sec->jrliodnr[0].ls, liodnr);
+ sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
#else
- liodnr = sec_in32(&sec->jrliodnr[0].ls);
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
#endif
-
- ret = jr_init(sec_idx);
+ ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
@@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
pamu_enable();
#endif
-#ifndef CONFIG_SPL_BUILD
- if (get_rng_vid(sec_idx) >= 4) {
- if (rng_init(sec_idx) < 0) {
+
+ if (get_rng_vid(caam->sec) >= 4) {
+ if (rng_init(sec_idx, caam->sec) < 0) {
printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
@@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
printf("SEC%u: RNG instantiated\n", sec_idx);
}
-#endif
return ret;
}
@@ -743,3 +771,76 @@ int sec_init(void)
{
return sec_init_idx(0);
}
+
+#if CONFIG_IS_ENABLED(DM)
+static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+ if (request != CAAM_JR_RUN_DESC)
+ return -ENOSYS;
+
+ return run_descriptor_jr(buf);
+}
+
+static int caam_jr_probe(struct udevice *dev)
+{
+ struct caam_regs *caam = dev_get_priv(dev);
+ fdt_addr_t addr;
+ ofnode node;
+ unsigned int jr_node = 0;
+
+ caam_dev = dev;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("caam_jr: crypto not found\n");
+ return -EINVAL;
+ }
+ caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
+ caam->regs = (struct jr_regs *)caam->sec;
+
+ /* Check for enabled job ring node */
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ if (!ofnode_is_available(node))
+ continue;
+
+ jr_node = ofnode_read_u32_default(node, "reg", -1);
+ if (jr_node > 0) {
+ caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
+ while (!(jr_node & 0x0F))
+ jr_node = jr_node >> 4;
+
+ caam->jrid = jr_node - 1;
+ break;
+ }
+ }
+
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+
+ return 0;
+}
+
+static int caam_jr_bind(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct misc_ops caam_jr_ops = {
+ .ioctl = caam_jr_ioctl,
+};
+
+static const struct udevice_id caam_jr_match[] = {
+ { .compatible = "fsl,sec-v4.0" },
+ { }
+};
+
+U_BOOT_DRIVER(caam_jr) = {
+ .name = "caam_jr",
+ .id = UCLASS_MISC,
+ .of_match = caam_jr_match,
+ .ops = &caam_jr_ops,
+ .bind = caam_jr_bind,
+ .probe = caam_jr_probe,
+ .priv_auto = sizeof(struct caam_regs),
+};
+#endif
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1047aa772c..3eb7be79da 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
*/
@@ -8,7 +9,9 @@
#define __JR_H
#include <linux/compiler.h>
+#include "fsl_sec.h"
#include "type.h"
+#include <misc.h>
#define JR_SIZE 4
/* Timeout currently defined as 10 sec */
@@ -35,12 +38,21 @@
#define JRSLIODN_SHIFT 0
#define JRSLIODN_MASK 0x00000fff
-#define JQ_DEQ_ERR -1
-#define JQ_DEQ_TO_ERR -2
-#define JQ_ENQ_ERR -3
+#define JRDID_MS_PRIM_DID BIT(0)
+#define JRDID_MS_PRIM_TZ BIT(4)
+#define JRDID_MS_TZ_OWN BIT(15)
+
+#define JQ_DEQ_ERR (-1)
+#define JQ_DEQ_TO_ERR (-2)
+#define JQ_ENQ_ERR (-3)
#define RNG4_MAX_HANDLES 2
+enum {
+ /* Run caam jobring descriptor(in buf) */
+ CAAM_JR_RUN_DESC,
+};
+
struct op_ring {
caam_dma_addr_t desc;
uint32_t status;
@@ -102,6 +114,19 @@ struct result {
uint32_t status;
};
+/*
+ * struct caam_regs - CAAM initialization register interface
+ *
+ * Interface to caam memory map, jobring register, jobring storage.
+ */
+struct caam_regs {
+ ccsr_sec_t *sec; /*caam initialization registers*/
+ struct jr_regs *regs; /*jobring configuration registers*/
+ u8 jrid; /*id to identify a jobring*/
+ /*Private sub-storage for a single JobR*/
+ struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+};
+
void caam_jr_strstatus(u32 status);
int run_descriptor_jr(uint32_t *desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
` (11 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
disabled use of JR0 in SPL and uboot, as JR0 is reserved
for secure boot.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 ++++
4 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 6b459831e7..e5682ca165 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mm-u-boot.dtsi"
@@ -68,6 +68,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 1d3844437d..d8df863083 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
/ {
@@ -104,6 +104,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index ab849ebaac..f3f83ba303 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mp-u-boot.dtsi"
@@ -67,6 +67,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&i2c1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462e..8f1f942215 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -10,3 +10,7 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&sec_jr0 {
+ status = "disabled";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 01/14] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 02/14] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
` (10 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX8MM/MN/MP/MQ - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/imx8m/Kconfig | 13 +++++++++++++
arch/arm/mach-imx/imx8m/soc.c | 10 +++++++++-
board/freescale/imx8mm_evk/spl.c | 9 ++++++++-
board/freescale/imx8mn_evk/spl.c | 8 ++++++--
board/freescale/imx8mp_evk/spl.c | 13 +++++++++++--
board/freescale/imx8mq_evk/spl.c | 9 +++++++--
drivers/crypto/fsl/jr.c | 14 +++++++++++---
scripts/config_whitelist.txt | 1 +
10 files changed, 68 insertions(+), 12 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7264d72bde..67f6805b13 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -820,7 +820,7 @@ config ARCH_IMX8M
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1..ff8de53f67 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -72,6 +72,7 @@
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d6a869068a..f3713529da 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -39,6 +39,9 @@ config TARGET_IMX8MQ_EVK
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@@ -52,6 +55,9 @@ config TARGET_IMX8MM_EVK
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@@ -91,6 +97,8 @@ config TARGET_IMX8MN_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@@ -98,6 +106,8 @@ config TARGET_IMX8MN_DDR4_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select FSL_CAAM
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
@@ -105,6 +115,9 @@ config TARGET_IMX8MP_EVK
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 863508776d..0f9bd77354 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019, 2021 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
@@ -20,6 +20,7 @@
#include <asm/ptrace.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
+#include <dm/device.h>
#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
@@ -1197,6 +1198,13 @@ static void acquire_buildinfo(void)
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
acquire_buildinfo();
return 0;
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 4ef7f6f180..c81128f442 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -51,6 +51,13 @@ static void spl_dram_init(void)
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
puts("Normal Boot\n");
}
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 03f2a56e80..ab19dabf7b 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -49,6 +49,10 @@ void spl_board_init(void)
struct udevice *dev;
int ret;
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index eca42c756e..bcef96caa3 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -20,6 +20,8 @@
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -35,6 +37,13 @@ void spl_dram_init(void)
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 67d069b2b0..8a47dd01a5 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -22,6 +21,7 @@
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
+#include <fsl_sec.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
@@ -199,6 +199,11 @@ int power_init_board(void)
void spl_board_init(void)
{
+#ifdef CONFIG_FSL_CAAM
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+
+#endif
puts("Normal Boot\n");
}
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8103987425..4e7accfb89 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -43,9 +43,17 @@ struct udevice *caam_dev;
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
-#define SEC_JR0_ADDR(idx) \
+#ifndef CONFIG_IMX8M
+#define SEC_JR_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 0
+#else
+#define SEC_JR_ADDR(idx) \
+ (ulong)(SEC_ADDR(idx) + \
+ (CONFIG_SYS_FSL_JR1_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 1
+#endif
struct caam_regs caam_st;
#endif
@@ -669,8 +677,8 @@ int sec_init_idx(uint8_t sec_idx)
caam = dev_get_priv(caam_dev);
#else
caam_st.sec = (void *)SEC_ADDR(sec_idx);
- caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- caam_st.jrid = 0;
+ caam_st.regs = (struct jr_regs *)SEC_JR_ADDR(sec_idx);
+ caam_st.jrid = JR_ID;
caam = &caam_st;
#endif
ccsr_sec_t *sec = caam->sec;
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 79f03d1636..98a4bf5aec 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1273,6 +1273,7 @@ CONFIG_SYS_FSL_IFC_LE
CONFIG_SYS_FSL_ISBC_VER
CONFIG_SYS_FSL_JR0_ADDR
CONFIG_SYS_FSL_JR0_OFFSET
+CONFIG_SYS_FSL_JR1_OFFSET
CONFIG_SYS_FSL_LS1_CLK_ADDR
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
CONFIG_SYS_FSL_MAX_NUM_OF_SEC
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 04/14] mx6sabre: Remove unnecessary SPL configs
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (2 preceding siblings ...)
2022-01-11 11:27 ` [PATCH v9 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
` (9 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean
From: Ye Li <ye.li@nxp.com>
Because we don't use SPL_DM on mx6sabresd and mx6sabreauto, so it is
unnecessary to have SPL DTB related configs and SPL_OF_CONTROL enabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
---
configs/mx6sabreauto_defconfig | 2 --
configs/mx6sabresd_defconfig | 4 ----
2 files changed, 6 deletions(-)
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index e03ac323ee..03e10f0711 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -62,10 +62,8 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 6cb74132d5..2e250397e0 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -65,12 +65,8 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 05/14] i.MX6: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (3 preceding siblings ...)
2022-01-11 11:27 ` [PATCH v9 04/14] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 06/14] i.MX7: " Gaurav Jain
` (8 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX6,i.MX6SX,i.MX6UL - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/mach-imx/mx6/Kconfig | 10 ++++++++++
arch/arm/mach-imx/mx6/soc.c | 12 ++++++++----
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98df4d4e42..3d675fcd73 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -354,6 +354,8 @@ config TARGET_MX6SABREAUTO
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SABRESD
bool "mx6sabresd"
@@ -364,6 +366,8 @@ config TARGET_MX6SABRESD
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SLEVK
bool "mx6slevk"
@@ -386,6 +390,8 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
select SUPPORT_SPL
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
@@ -404,6 +410,8 @@ config TARGET_MX6UL_9X9_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
@@ -413,6 +421,8 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index aacfc854a2..fa6c3778bb 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -4,6 +4,7 @@
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -23,7 +24,6 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
-#include <fsl_sec.h>
#include <imx_thermal.h>
#include <mmc.h>
@@ -734,9 +734,13 @@ static void setup_serial_number(void)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
setup_serial_number();
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 06/14] i.MX7: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (4 preceding siblings ...)
2022-01-11 11:27 ` [PATCH v9 05/14] i.MX6: Enable Job ring driver model Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 07/14] i.MX7ULP: " Gaurav Jain
` (7 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX7D - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-imx/mx7/Kconfig | 1 +
arch/arm/mach-imx/mx7/soc.c | 11 +++++++----
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 67f6805b13..06efe07b1c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -888,7 +888,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 0cad825287..4f9f51c9b0 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -68,6 +68,7 @@ config TARGET_MX7DSABRESD
select DM_THERMAL
select MX7D
imply CMD_DM
+ select FSL_CAAM
config TARGET_PICO_IMX7D
bool "pico-imx7d"
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 21690072e1..6c991a6cb1 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -19,7 +20,6 @@
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
-#include <fsl_sec.h>
#include <asm/setup.h>
#include <linux/delay.h>
@@ -337,6 +337,9 @@ int arch_cpu_init(void)
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
struct tag_serialnr serialnr;
char serial_string[0x20];
@@ -353,9 +356,9 @@ int arch_misc_init(void)
env_set("serial#", serial_string);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 07/14] i.MX7ULP: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (5 preceding siblings ...)
2022-01-11 11:27 ` [PATCH v9 06/14] i.MX7: " Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:27 ` [PATCH v9 08/14] i.MX8: Add crypto node in device tree Gaurav Jain
` (6 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/dts/imx7ulp.dtsi | 24 ++++++++++++++++++++++++
arch/arm/mach-imx/mx7ulp/Kconfig | 2 ++
arch/arm/mach-imx/mx7ulp/soc.c | 16 ++++++++++++++++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 06efe07b1c..5e3c2ed3eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -875,7 +875,7 @@ config ARCH_MX7ULP
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 7bcd2cc346..494b9d98b2 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -198,6 +199,29 @@
};
};
+ crypto: crypto@40240000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40240000 0x10000>;
+ ranges = <0 0x40240000 0x10000>;
+ clocks = <&clks IMX7ULP_CLK_CAAM>,
+ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 2ffac9cf7c..0d238d2557 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -25,6 +25,8 @@ config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
select SYS_ARCH_TIMER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
endchoice
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index c90ce22404..c1e55e7260 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -15,6 +16,7 @@
#include <asm/mach-imx/hab.h>
#include <asm/setup.h>
#include <linux/bitops.h>
+#include <dm.h>
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
@@ -80,6 +82,20 @@ int arch_cpu_init(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 08/14] i.MX8: Add crypto node in device tree
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (6 preceding siblings ...)
2022-01-11 11:27 ` [PATCH v9 07/14] i.MX7ULP: " Gaurav Jain
@ 2022-01-11 11:27 ` Gaurav Jain
2022-01-11 11:28 ` [PATCH v9 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
` (5 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/fsl-imx8dx.dtsi | 61 +++++++++++++++++++++++-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 ++++++++++++-
arch/arm/dts/fsl-imx8qm.dtsi | 61 +++++++++++++++++++++++-
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 ++++++++++++-
4 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7d..63a56699b5 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -261,6 +261,30 @@
power-domains = <&pd_dma>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
@@ -609,6 +633,41 @@
};
};
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A35_0 {
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71..a95209e141 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qm-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b3..517fb13cad 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -235,6 +235,30 @@
wakeup-irq = <349>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
@@ -556,6 +580,41 @@
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A53_0 {
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af4434d..ae037c7550 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qx-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 09/14] crypto/fsl: i.MX8: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (7 preceding siblings ...)
2022-01-11 11:27 ` [PATCH v9 08/14] i.MX8: Add crypto node in device tree Gaurav Jain
@ 2022-01-11 11:28 ` Gaurav Jain
2022-01-11 11:28 ` [PATCH v9 10/14] Layerscape: Add crypto node in device tree Gaurav Jain
` (4 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:28 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 3 ++
arch/arm/include/asm/arch-imx8/imx-regs.h | 5 ++-
arch/arm/mach-imx/cmd_dek.c | 1 +
arch/arm/mach-imx/imx8/Kconfig | 7 ++++
arch/arm/mach-imx/imx8/cpu.c | 16 +++++++-
board/freescale/imx8qm_mek/spl.c | 6 ++-
board/freescale/imx8qxp_mek/spl.c | 6 ++-
drivers/crypto/fsl/Kconfig | 2 +-
drivers/crypto/fsl/jr.c | 47 ++++++++++++++++++++++-
include/fsl_sec.h | 12 +++---
10 files changed, 89 insertions(+), 16 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5e3c2ed3eb..dd01856b3e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -809,6 +809,9 @@ config ARCH_LPC32XX
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e556..2d64b0604b 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
@@ -47,4 +47,7 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 89da89c51d..04c4b20a84 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -9,6 +9,7 @@
#include <command.h>
#include <log.h>
#include <malloc.h>
+#include <memalign.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
#include <fsl_sec.h>
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c6..f969833bab 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -8,6 +8,7 @@ config AHAB_BOOT
config IMX8
bool
+ select HAS_CAAM
config MU_BASE_SPL
hex "MU base address used in SPL"
@@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
@@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
endchoice
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index ee5cc47903..5140c93a37 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <common.h>
@@ -89,6 +89,20 @@ int arch_cpu_init_dm(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 944ba745c0..332a662dee 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -24,6 +24,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index ae6b64ff6e..2fa6840056 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -39,6 +39,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 231eb00b5f..e03fcdd9c7 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -12,7 +12,7 @@ config FSL_CAAM
config CAAM_64BIT
bool
- default y if PHYS_64BIT && !ARCH_IMX8M
+ default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
help
Select Crypto driver for 64 bits CAAM version
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 4e7accfb89..a84440ab10 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
+#include <power-domain.h>
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -121,7 +122,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
struct jobring *jr = &caam->jr[sec_idx];
-
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+#endif
memset(jr, 0, sizeof(struct jobring));
jr->jq_id = caam->jrid;
@@ -146,7 +149,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (!ofnode_valid(scu_node))
+#endif
start_jr(caam);
+
jr_initregs(sec_idx, caam);
return 0;
@@ -681,6 +688,13 @@ int sec_init_idx(uint8_t sec_idx)
caam_st.jrid = JR_ID;
caam = &caam_st;
#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+
+ if (ofnode_valid(scu_node))
+ goto init;
+#endif
+
ccsr_sec_t *sec = caam->sec;
uint32_t mcr = sec_in32(&sec->mcfgr);
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
@@ -742,12 +756,19 @@ int sec_init_idx(uint8_t sec_idx)
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
+#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+init:
#endif
ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (ofnode_valid(scu_node))
+ return ret;
+#endif
#ifdef CONFIG_FSL_CORENET
ret = sec_config_pamu_table(liodn_ns, liodn_s);
@@ -781,6 +802,23 @@ int sec_init(void)
}
#if CONFIG_IS_ENABLED(DM)
+static int jr_power_on(ofnode node)
+{
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct udevice __maybe_unused jr_dev;
+ struct power_domain pd;
+
+ dev_set_ofnode(&jr_dev, node);
+
+ /* Power on Job Ring before access it */
+ if (!power_domain_get(&jr_dev, &pd)) {
+ if (power_domain_on(&pd))
+ return -EINVAL;
+ }
+#endif
+ return 0;
+}
+
static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
{
if (request != CAAM_JR_RUN_DESC)
@@ -793,7 +831,7 @@ static int caam_jr_probe(struct udevice *dev)
{
struct caam_regs *caam = dev_get_priv(dev);
fdt_addr_t addr;
- ofnode node;
+ ofnode node, scu_node;
unsigned int jr_node = 0;
caam_dev = dev;
@@ -818,6 +856,11 @@ static int caam_jr_probe(struct udevice *dev)
jr_node = jr_node >> 4;
caam->jrid = jr_node - 1;
+ scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+ if (ofnode_valid(scu_node)) {
+ if (jr_power_on(node))
+ return -EINVAL;
+ }
break;
}
}
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c4121696f8..7b6e3e2c20 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,7 +3,7 @@
* Common internal memory map for some Freescale SoCs
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __FSL_SEC_H
@@ -194,12 +194,10 @@ typedef struct ccsr_sec {
#define SEC_CHAVID_LS_RNG_SHIFT 16
#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
-#define CONFIG_JRSTARTR_JR0 0x00000001
-
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 irba_l;
u32 irba_h;
#else
@@ -214,7 +212,7 @@ struct jr_regs {
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 orba_l;
u32 orba_h;
#else
@@ -248,7 +246,7 @@ struct jr_regs {
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
@@ -268,7 +266,7 @@ struct sg_entry {
};
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 10/14] Layerscape: Add crypto node in device tree
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (8 preceding siblings ...)
2022-01-11 11:28 ` [PATCH v9 09/14] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
@ 2022-01-11 11:28 ` Gaurav Jain
2022-01-11 11:28 ` [PATCH v9 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
` (3 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:28 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/dts/fsl-ls1012a.dtsi | 46 ++++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1043a.dtsi | 45 +++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1046a.dtsi | 44 +++++++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls1088a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls2080a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-lx2160a.dtsi | 41 ++++++++++++++++++++++++++++++-
arch/arm/dts/ls1021a.dtsi | 40 ++++++++++++++++++++++++++++++
7 files changed, 291 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7..1cdcc99c1e 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -71,6 +71,50 @@
bus-width = <4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638..72877d2ff5 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
@@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc..c655e002aa 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@@ -124,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f73fdfda8b..9b7c54b260 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -174,6 +174,45 @@
dr_mode = "host";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 72ba52594a..a1837454f4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -239,6 +239,45 @@
status = "disabled";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <0 139 0x4>; /* Level high type */
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 140 0x4>; /* Level high type */
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 141 0x4>; /* Level high type */
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 142 0x4>; /* Level high type */
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 143 0x4>; /* Level high type */
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 52e4d7205a..57c7d3ef71 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
*/
@@ -27,6 +27,45 @@
clock-output-names = "sysclk";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f..be330c130f 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -3,6 +3,7 @@
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include "skeleton.dtsi"
@@ -144,6 +145,45 @@
big-endian;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1700000 0x100000>;
+ ranges = <0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (9 preceding siblings ...)
2022-01-11 11:28 ` [PATCH v9 10/14] Layerscape: Add crypto node in device tree Gaurav Jain
@ 2022-01-11 11:28 ` Gaurav Jain
2022-01-11 12:10 ` Michael Walle
2022-01-11 11:28 ` [PATCH v9 12/14] PPC: Add crypto node in device tree Gaurav Jain
` (2 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:28 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.
removed sec_init() call from board files.
removed CONFIG_FSL_CAAM from defconfig files.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/Kconfig | 31 +++++++++++++++++++
arch/arm/cpu/armv7/ls102xa/cpu.c | 16 ++++++++++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +++++-
board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +----
board/freescale/ls1012aqds/ls1012aqds.c | 6 +---
board/freescale/ls1012ardb/ls1012ardb.c | 6 +---
board/freescale/ls1021aiot/ls1021aiot.c | 6 ++--
board/freescale/ls1021aqds/ls1021aqds.c | 6 +---
board/freescale/ls1021atsn/ls1021atsn.c | 7 ++---
board/freescale/ls1021atwr/ls1021atwr.c | 8 ++---
board/freescale/ls1028a/ls1028a.c | 6 +---
board/freescale/ls1043ardb/ls1043ardb.c | 6 +---
board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +----
board/freescale/ls1046aqds/ls1046aqds.c | 7 +----
board/freescale/ls1046ardb/ls1046ardb.c | 6 +---
board/freescale/ls1088a/ls1088a.c | 6 +---
board/freescale/ls2080aqds/ls2080aqds.c | 6 +---
board/freescale/ls2080ardb/ls2080ardb.c | 9 +-----
board/freescale/lx2160a/lx2160a.c | 5 ---
board/kontron/sl28/sl28.c | 3 --
configs/ls1021aiot_qspi_defconfig | 1 -
configs/ls1021aqds_nor_defconfig | 1 -
configs/ls1021aqds_qspi_defconfig | 1 -
configs/ls1021atsn_qspi_defconfig | 1 -
configs/ls1021atwr_nor_defconfig | 1 -
...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1028ardb_tfa_defconfig | 1 -
configs/ls1043ardb_tfa_defconfig | 1 -
configs/ls1046afrwy_tfa_defconfig | 1 -
configs/ls1046aqds_tfa_defconfig | 1 -
configs/ls1046ardb_tfa_defconfig | 1 -
configs/ls2088aqds_tfa_defconfig | 1 -
configs/ls2088ardb_tfa_defconfig | 1 -
configs/lx2160aqds_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_defconfig | 1 -
configs/lx2162aqds_tfa_defconfig | 1 -
36 files changed, 75 insertions(+), 105 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dd01856b3e..aadc915de3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1293,6 +1293,7 @@ config TARGET_LS1088AQDS
select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
+ select FSL_CAAM
help
Support for NXP LS1088AQDS platform.
The LS1088A Development System (QDS) is a high-performance
@@ -1312,6 +1313,7 @@ config TARGET_LS2080AQDS
imply SCSI_AHCI
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
+ select FSL_CAAM
help
Support for Freescale LS2080AQDS platform.
The LS2080A Development System (QDS) is a high-performance
@@ -1329,6 +1331,7 @@ config TARGET_LS2080ARDB
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
imply SCSI
imply SCSI_AHCI
help
@@ -1359,6 +1362,7 @@ config TARGET_LX2160ARDB
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
help
Support for NXP LX2160ARDB platform.
The lx2160ardb (LX2160A Reference design board (RDB)
@@ -1373,6 +1377,7 @@ config TARGET_LX2160AQDS
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
help
Support for NXP LX2160AQDS platform.
The lx2160aqds (LX2160A QorIQ Development System (QDS)
@@ -1388,6 +1393,7 @@ config TARGET_LX2162AQDS
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
help
Support for NXP LX2162AQDS platform.
The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
@@ -1442,6 +1448,8 @@ config TARGET_LS1012AQDS
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
help
Support for Freescale LS1012AQDS platform.
The LS1012A Development System (QDS) is a high-performance
@@ -1455,6 +1463,8 @@ config TARGET_LS1012ARDB
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
imply SCSI_AHCI
help
@@ -1498,6 +1508,8 @@ config TARGET_LS1012AFRDM
select ARM64
select ARCH_SUPPORT_TFABOOT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
help
Support for Freescale LS1012AFRDM platform.
The LS1012A Freedom board (FRDM) is a high-performance
@@ -1512,6 +1524,7 @@ config TARGET_LS1028AQDS
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@@ -1526,6 +1539,7 @@ config TARGET_LS1028ARDB
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
@@ -1542,6 +1556,7 @@ config TARGET_LS1088ARDB
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
help
Support for NXP LS1088ARDB platform.
The LS1088A Reference design board (RDB) is a high-performance
@@ -1564,6 +1579,8 @@ config TARGET_LS1021AQDS
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
config TARGET_LS1021ATWR
@@ -1579,6 +1596,8 @@ config TARGET_LS1021ATWR
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
config TARGET_PG_WCOM_SELI8
@@ -1630,6 +1649,8 @@ config TARGET_LS1021ATSN
select LS1_DEEP_SLEEP
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
config TARGET_LS1021AIOT
@@ -1643,6 +1664,8 @@ config TARGET_LS1021AIOT
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS1021AIOT platform.
@@ -1680,6 +1703,8 @@ config TARGET_LS1043ARDB
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
help
Support for Freescale LS1043ARDB platform.
@@ -1697,6 +1722,8 @@ config TARGET_LS1046AQDS
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DDR_INTERACTIVE if !SPL
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS1046AQDS platform.
@@ -1718,6 +1745,8 @@ config TARGET_LS1046ARDB
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS1046ARDB platform.
@@ -1735,6 +1764,8 @@ config TARGET_LS1046AFRWY
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply SCSI
help
Support for Freescale LS1046AFRWY platform.
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d863c9625a..4904592703 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -20,6 +21,7 @@
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
+#include <dm.h>
#include "fsl_epu.h"
@@ -397,3 +399,17 @@ void arch_preboot_os(void)
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 2ded3e4efc..29aa9a3f10 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -49,6 +49,7 @@
#endif
#endif
#include <linux/mii.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1650,6 +1651,13 @@ __weak int serdes_misc_init(void)
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
serdes_misc_init();
return 0;
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 5dd19cfcd9..bc37c553a5 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
@@ -22,7 +22,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -172,10 +171,6 @@ int board_init(void)
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 68578e81a5..361bd5c582 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -28,7 +29,6 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
@@ -150,10 +150,6 @@ int board_init(void)
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 064fb4d39f..456609d993 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -27,7 +28,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -173,10 +173,6 @@ int board_init(void)
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index bfe6137604..5ab03b3340 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -209,10 +210,7 @@ int misc_init_r(void)
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 0647622cde..2eaad9e742 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -20,7 +20,6 @@
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
@@ -388,9 +387,6 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
#endif
return 0;
}
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index f31e16c419..f016088670 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -238,10 +238,7 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index f0b441db63..a2a87eaf35 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -26,7 +26,6 @@
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
-#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <spl.h>
#include <linux/delay.h>
@@ -555,10 +554,7 @@ int misc_init_r(void)
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 486a544d35..71a086ef67 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -73,10 +73,6 @@ u32 get_lpuart_clk(void)
int board_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index beef26b084..c7f214c236 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -20,7 +21,6 @@
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
@@ -211,10 +211,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index f1c08a13f7..5a298cd311 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -20,7 +20,6 @@
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
-#include <fsl_sec.h>
#include <fsl_dspi.h>
#include "../common/i2c_mux.h"
@@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 8481c45a58..e5b5441e2c 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#include <common.h>
@@ -28,7 +28,6 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include "../common/i2c_mux.h"
@@ -421,10 +420,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
return 0;
}
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 93ef903f29..2e9a6d44eb 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -23,7 +24,6 @@
#include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h>
#include "cpld.h"
-#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -85,10 +85,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index aa548b20d7..db94ee5689 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -13,7 +13,6 @@
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
@@ -820,9 +819,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 297629d5ef..5bdafebb6b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -21,7 +22,6 @@
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -222,10 +222,6 @@ int board_init(void)
#endif
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 1975b0f47d..f5ebb934eb 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -24,7 +24,6 @@
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
-#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -288,9 +287,6 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
@@ -299,9 +295,6 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index bda665624d..c8a47c6bae 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -14,7 +14,6 @@
#include <errno.h>
#include <netdev.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/bitops.h>
@@ -596,10 +595,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index e84b356918..7f2a8aac62 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -28,9 +28,6 @@ int board_early_init_f(void)
int board_init(void)
{
- if (CONFIG_IS_ENABLED(FSL_CAAM))
- sec_init();
-
return 0;
}
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 4705e34e1d..6e5ce2ed92 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index f4e2274fb8..ab3276ca54 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -51,7 +51,6 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index f967619ef9..6c60bb384a 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -50,7 +50,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 5c8cee3ea9..ad199ce482 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -37,7 +37,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 02c25cda7d..e7ed10cbd6 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -45,7 +45,6 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 756e072f9c..8a3233e54a 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SPL_OF_CONTROL=y
# CONFIG_SPL_BLK is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index b58254dc65..dbe2ed37cb 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -49,7 +49,6 @@ CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 99c125731f..262082f893 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -41,7 +41,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index af07b1cd46..548b95a300 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -39,7 +39,6 @@ CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index f706dd6179..3858746d69 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -59,7 +59,6 @@ CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 149091af4a..4c636caf6d 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -44,7 +44,6 @@ CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 61e0fdf113..f652c9860a 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -51,7 +51,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index a28b45b129..5230d7ead8 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x580500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index de8dc553d1..74314c0be2 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -56,7 +56,6 @@ CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 59955eebbe..3af38a68d0 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -55,7 +55,6 @@ CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index 203554b61f..8fa5406678 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -58,7 +58,6 @@ CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
2022-01-11 11:28 ` [PATCH v9 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
@ 2022-01-11 12:10 ` Michael Walle
2022-01-11 12:30 ` [EXT] " Gaurav Jain
0 siblings, 1 reply; 20+ messages in thread
From: Michael Walle @ 2022-01-11 12:10 UTC (permalink / raw)
To: Gaurav Jain
Cc: u-boot, Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean
Hi Gaurav,
Am 2022-01-11 12:28, schrieb Gaurav Jain:
> @@ -1329,6 +1331,7 @@ config TARGET_LS2080ARDB
> select FSL_DDR_BIST
> select FSL_DDR_INTERACTIVE if !SPL
> select GPIO_EXTRA_HEADER
> + select FSL_CAAM
See below.
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 2ded3e4efc..29aa9a3f10 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Copyright 2017-2020 NXP
> + * Copyright 2017-2021 NXP
> * Copyright 2014-2015 Freescale Semiconductor, Inc.
> */
>
> @@ -49,6 +49,7 @@
> #endif
> #endif
> #include <linux/mii.h>
> +#include <dm.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -1650,6 +1651,13 @@ __weak int serdes_misc_init(void)
>
> int arch_misc_init(void)
> {
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> DM_DRIVER_GET(caam_jr), &dev);
> + if (ret)
> + printf("Failed to initialize %s: %d\n", dev->name, ret);
This will fail when the CAAM driver isn't enabled and will then print
this error message. Should be guarded with IS_ENABLED(FSL_CAAM).
> diff --git a/configs/ls2088ardb_tfa_defconfig
> b/configs/ls2088ardb_tfa_defconfig
> index a28b45b129..5230d7ead8 100644
> --- a/configs/ls2088ardb_tfa_defconfig
> +++ b/configs/ls2088ardb_tfa_defconfig
> @@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x580500000
> CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_DM=y
> CONFIG_SATA_CEVA=y
> -CONFIG_FSL_CAAM=y
> CONFIG_DDR_CLK_FREQ=133333333
> CONFIG_DDR_ECC=y
> CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
..
I still don't understand why you make the FSL_CAAM mandatory and remove
the
option here. Same for all other boards.
-michael
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [EXT] Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
2022-01-11 12:10 ` Michael Walle
@ 2022-01-11 12:30 ` Gaurav Jain
2022-01-11 12:34 ` Michael Walle
0 siblings, 1 reply; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 12:30 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta, Varun Sethi,
dl-uboot-imx, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Andy Tang, Adrian Alonso, Vladimir Oltean
Hi Michael
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Tuesday, January 11, 2022 5:41 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: u-boot@lists.denx.de; Stefano Babic <sbabic@denx.de>; Fabio Estevam
> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: [EXT] Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
>
> Caution: EXT Email
>
> Hi Gaurav,
>
> Am 2022-01-11 12:28, schrieb Gaurav Jain:
> > @@ -1329,6 +1331,7 @@ config TARGET_LS2080ARDB
> > select FSL_DDR_BIST
> > select FSL_DDR_INTERACTIVE if !SPL
> > select GPIO_EXTRA_HEADER
> > + select FSL_CAAM
>
> See below.
>
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index 2ded3e4efc..29aa9a3f10 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > - * Copyright 2017-2020 NXP
> > + * Copyright 2017-2021 NXP
> > * Copyright 2014-2015 Freescale Semiconductor, Inc.
> > */
> >
> > @@ -49,6 +49,7 @@
> > #endif
> > #endif
> > #include <linux/mii.h>
> > +#include <dm.h>
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -1650,6 +1651,13 @@ __weak int serdes_misc_init(void)
> >
> > int arch_misc_init(void)
> > {
> > + struct udevice *dev;
> > + int ret;
> > +
> > + ret = uclass_get_device_by_driver(UCLASS_MISC,
> > DM_DRIVER_GET(caam_jr), &dev);
> > + if (ret)
> > + printf("Failed to initialize %s: %d\n", dev->name, ret);
>
> This will fail when the CAAM driver isn't enabled and will then print this error
> message. Should be guarded with IS_ENABLED(FSL_CAAM).
I agree. Will add this.
If you have more comments, please share.
I will check and incorporate the changes in single version.
>
>
> > diff --git a/configs/ls2088ardb_tfa_defconfig
> > b/configs/ls2088ardb_tfa_defconfig
> > index a28b45b129..5230d7ead8 100644
> > --- a/configs/ls2088ardb_tfa_defconfig
> > +++ b/configs/ls2088ardb_tfa_defconfig
> > @@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x580500000
> > CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y
> > -CONFIG_FSL_CAAM=y
> > CONFIG_DDR_CLK_FREQ=133333333
> > CONFIG_DDR_ECC=y
> > CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
> ..
>
> I still don't understand why you make the FSL_CAAM mandatory and remove the
> option here. Same for all other boards.
Instead of enabling FSL_CAAM in every defconfig for a particular board, I moved FSL_CAAM to specific TARGET boards.
this will enable FSL_CAAM to every defconfig for a target board.
Regards
Gaurav Jain
>
> -michael
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [EXT] Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
2022-01-11 12:30 ` [EXT] " Gaurav Jain
@ 2022-01-11 12:34 ` Michael Walle
2022-01-11 12:55 ` Gaurav Jain
0 siblings, 1 reply; 20+ messages in thread
From: Michael Walle @ 2022-01-11 12:34 UTC (permalink / raw)
To: Gaurav Jain
Cc: u-boot, Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta, Varun Sethi,
dl-uboot-imx, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Andy Tang, Adrian Alonso, Vladimir Oltean
Hi Gaurav,
Am 2022-01-11 13:30, schrieb Gaurav Jain:
>> Am 2022-01-11 12:28, schrieb Gaurav Jain:
>> > @@ -1329,6 +1331,7 @@ config TARGET_LS2080ARDB
>> > select FSL_DDR_BIST
>> > select FSL_DDR_INTERACTIVE if !SPL
>> > select GPIO_EXTRA_HEADER
>> > + select FSL_CAAM
>>
>> See below.
>>
>> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> > index 2ded3e4efc..29aa9a3f10 100644
>> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>> > @@ -1,6 +1,6 @@
>> > // SPDX-License-Identifier: GPL-2.0+
>> > /*
>> > - * Copyright 2017-2020 NXP
>> > + * Copyright 2017-2021 NXP
>> > * Copyright 2014-2015 Freescale Semiconductor, Inc.
>> > */
>> >
>> > @@ -49,6 +49,7 @@
>> > #endif
>> > #endif
>> > #include <linux/mii.h>
>> > +#include <dm.h>
>> >
>> > DECLARE_GLOBAL_DATA_PTR;
>> >
>> > @@ -1650,6 +1651,13 @@ __weak int serdes_misc_init(void)
>> >
>> > int arch_misc_init(void)
>> > {
>> > + struct udevice *dev;
>> > + int ret;
>> > +
>> > + ret = uclass_get_device_by_driver(UCLASS_MISC,
>> > DM_DRIVER_GET(caam_jr), &dev);
>> > + if (ret)
>> > + printf("Failed to initialize %s: %d\n", dev->name, ret);
>>
>> This will fail when the CAAM driver isn't enabled and will then print
>> this error
>> message. Should be guarded with IS_ENABLED(FSL_CAAM).
> I agree. Will add this.
> If you have more comments, please share.
> I will check and incorporate the changes in single version.
Sorry, didn't notice that before.
>> > diff --git a/configs/ls2088ardb_tfa_defconfig
>> > b/configs/ls2088ardb_tfa_defconfig
>> > index a28b45b129..5230d7ead8 100644
>> > --- a/configs/ls2088ardb_tfa_defconfig
>> > +++ b/configs/ls2088ardb_tfa_defconfig
>> > @@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x580500000
>> > CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y
>> > -CONFIG_FSL_CAAM=y
>> > CONFIG_DDR_CLK_FREQ=133333333
>> > CONFIG_DDR_ECC=y
>> > CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
>> ..
>>
>> I still don't understand why you make the FSL_CAAM mandatory and
>> remove the
>> option here. Same for all other boards.
> Instead of enabling FSL_CAAM in every defconfig for a particular
> board, I moved FSL_CAAM to specific TARGET boards.
> this will enable FSL_CAAM to every defconfig for a target board.
But a user/developer cannot disable that option anymore in this case.
-michael
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [EXT] Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
2022-01-11 12:34 ` Michael Walle
@ 2022-01-11 12:55 ` Gaurav Jain
2022-01-11 13:02 ` Michael Walle
0 siblings, 1 reply; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 12:55 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta, Varun Sethi,
dl-uboot-imx, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Andy Tang, Adrian Alonso, Vladimir Oltean
Hi Michael
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Tuesday, January 11, 2022 6:04 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: u-boot@lists.denx.de; Stefano Babic <sbabic@denx.de>; Fabio Estevam
> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: Re: [EXT] Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver
> model.
>
> Caution: EXT Email
>
> Hi Gaurav,
>
> Am 2022-01-11 13:30, schrieb Gaurav Jain:
> >> Am 2022-01-11 12:28, schrieb Gaurav Jain:
> >> > @@ -1329,6 +1331,7 @@ config TARGET_LS2080ARDB
> >> > select FSL_DDR_BIST
> >> > select FSL_DDR_INTERACTIVE if !SPL
> >> > select GPIO_EXTRA_HEADER
> >> > + select FSL_CAAM
> >>
> >> See below.
> >>
> >> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> > index 2ded3e4efc..29aa9a3f10 100644
> >> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> > @@ -1,6 +1,6 @@
> >> > // SPDX-License-Identifier: GPL-2.0+
> >> > /*
> >> > - * Copyright 2017-2020 NXP
> >> > + * Copyright 2017-2021 NXP
> >> > * Copyright 2014-2015 Freescale Semiconductor, Inc.
> >> > */
> >> >
> >> > @@ -49,6 +49,7 @@
> >> > #endif
> >> > #endif
> >> > #include <linux/mii.h>
> >> > +#include <dm.h>
> >> >
> >> > DECLARE_GLOBAL_DATA_PTR;
> >> >
> >> > @@ -1650,6 +1651,13 @@ __weak int serdes_misc_init(void)
> >> >
> >> > int arch_misc_init(void)
> >> > {
> >> > + struct udevice *dev;
> >> > + int ret;
> >> > +
> >> > + ret = uclass_get_device_by_driver(UCLASS_MISC,
> >> > DM_DRIVER_GET(caam_jr), &dev);
> >> > + if (ret)
> >> > + printf("Failed to initialize %s: %d\n", dev->name,
> >> > + ret);
> >>
> >> This will fail when the CAAM driver isn't enabled and will then print
> >> this error message. Should be guarded with IS_ENABLED(FSL_CAAM).
> > I agree. Will add this.
> > If you have more comments, please share.
> > I will check and incorporate the changes in single version.
>
> Sorry, didn't notice that before.
>
> >> > diff --git a/configs/ls2088ardb_tfa_defconfig
> >> > b/configs/ls2088ardb_tfa_defconfig
> >> > index a28b45b129..5230d7ead8 100644
> >> > --- a/configs/ls2088ardb_tfa_defconfig
> >> > +++ b/configs/ls2088ardb_tfa_defconfig
> >> > @@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x580500000
> >> > CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y
> CONFIG_SATA_CEVA=y
> >> > -CONFIG_FSL_CAAM=y
> >> > CONFIG_DDR_CLK_FREQ=133333333
> >> > CONFIG_DDR_ECC=y
> >> > CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
> >> ..
> >>
> >> I still don't understand why you make the FSL_CAAM mandatory and
> >> remove the option here. Same for all other boards.
> > Instead of enabling FSL_CAAM in every defconfig for a particular
> > board, I moved FSL_CAAM to specific TARGET boards.
> > this will enable FSL_CAAM to every defconfig for a target board.
>
> But a user/developer cannot disable that option anymore in this case.
I have enabled FSL_CAAM only for the boards that are enabling CAAM previously as well.
Current change make it easy, else I have to make change in each defconfig for all target boards.
Regards
Gaurav Jain
>
> -michael
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [EXT] Re: [PATCH v9 11/14] Layerscape: Enable Job ring driver model.
2022-01-11 12:55 ` Gaurav Jain
@ 2022-01-11 13:02 ` Michael Walle
0 siblings, 0 replies; 20+ messages in thread
From: Michael Walle @ 2022-01-11 13:02 UTC (permalink / raw)
To: Gaurav Jain
Cc: u-boot, Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta, Varun Sethi,
dl-uboot-imx, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Andy Tang, Adrian Alonso, Vladimir Oltean
Hi,
Am 2022-01-11 13:55, schrieb Gaurav Jain:
>> >> > diff --git a/configs/ls2088ardb_tfa_defconfig
>> >> > b/configs/ls2088ardb_tfa_defconfig
>> >> > index a28b45b129..5230d7ead8 100644
>> >> > --- a/configs/ls2088ardb_tfa_defconfig
>> >> > +++ b/configs/ls2088ardb_tfa_defconfig
>> >> > @@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x580500000
>> >> > CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y
>> CONFIG_SATA_CEVA=y
>> >> > -CONFIG_FSL_CAAM=y
>> >> > CONFIG_DDR_CLK_FREQ=133333333
>> >> > CONFIG_DDR_ECC=y
>> >> > CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
>> >> ..
>> >>
>> >> I still don't understand why you make the FSL_CAAM mandatory and
>> >> remove the option here. Same for all other boards.
>> > Instead of enabling FSL_CAAM in every defconfig for a particular
>> > board, I moved FSL_CAAM to specific TARGET boards.
>> > this will enable FSL_CAAM to every defconfig for a target board.
>>
>> But a user/developer cannot disable that option anymore in this case.
> I have enabled FSL_CAAM only for the boards that are enabling CAAM
> previously as well.
> Current change make it easy, else I have to make change in each
> defconfig for all target boards.
But a defconfig is, as the name says, just the default config. A user
can still disable the CAAM driver. If you instead add it as a
"select FSL_CAAM" to the TARGET_ symbol, the user cannot disable
it anymore.
-michael
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v9 12/14] PPC: Add crypto node in device tree
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (10 preceding siblings ...)
2022-01-11 11:28 ` [PATCH v9 11/14] Layerscape: Enable Job ring driver model Gaurav Jain
@ 2022-01-11 11:28 ` Gaurav Jain
2022-01-11 11:28 ` [PATCH v9 13/14] PPC: Enable Job ring driver model Gaurav Jain
2022-01-11 11:28 ` [PATCH v9 14/14] update CAAM MAINTAINER Gaurav Jain
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:28 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
device tree imported from linux kernel.
c500bee1c5b2 (tag: v5.14-rc4) Linux 5.14-rc4
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/powerpc/dts/p2041si-post.dtsi | 1 +
arch/powerpc/dts/p3041si-post.dtsi | 1 +
arch/powerpc/dts/p4080si-post.dtsi | 1 +
arch/powerpc/dts/p5040si-post.dtsi | 1 +
arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++++++++++++++++++++++
arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +++++++++++++++++++++++++
arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 ++++++++++++++++++++++++++++
arch/powerpc/dts/t1023si-post.dtsi | 1 +
arch/powerpc/dts/t1042si-post.dtsi | 1 +
arch/powerpc/dts/t2080si-post.dtsi | 1 +
arch/powerpc/dts/t4240si-post.dtsi | 1 +
11 files changed, 257 insertions(+)
create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi
index 01ab395950..8819199646 100644
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ b/arch/powerpc/dts/p2041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi
index 21f322f06f..a3e8088d25 100644
--- a/arch/powerpc/dts/p3041si-post.dtsi
+++ b/arch/powerpc/dts/p3041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p4080si-post.dtsi b/arch/powerpc/dts/p4080si-post.dtsi
index 7c3f2fb92e..56b79b14f4 100644
--- a/arch/powerpc/dts/p4080si-post.dtsi
+++ b/arch/powerpc/dts/p4080si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p5040si-post.dtsi b/arch/powerpc/dts/p5040si-post.dtsi
index 1efad2d017..fae3ed31a5 100644
--- a/arch/powerpc/dts/p5040si-post.dtsi
+++ b/arch/powerpc/dts/p5040si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/qoriq-sec4.0-0.dtsi b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
new file mode 100644
index 0000000000..ff348d70f1
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec4.2-0.dtsi b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
new file mode 100644
index 0000000000..57a0bc5c56
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec5.2-0.dtsi b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
new file mode 100644
index 0000000000..e5f87effd3
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.2-rtic",
+ "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi
index 7284eb9791..6f666a1554 100644
--- a/arch/powerpc/dts/t1023si-post.dtsi
+++ b/arch/powerpc/dts/t1023si-post.dtsi
@@ -14,6 +14,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman3l-0.dtsi"
diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi
index 5c60944e60..eebbbaf0e1 100644
--- a/arch/powerpc/dts/t1042si-post.dtsi
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi
index d8ef579cb7..c06526b3db 100644
--- a/arch/powerpc/dts/t2080si-post.dtsi
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -13,6 +13,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi
index a596f48b54..9fa99ae771 100644
--- a/arch/powerpc/dts/t4240si-post.dtsi
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 13/14] PPC: Enable Job ring driver model.
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (11 preceding siblings ...)
2022-01-11 11:28 ` [PATCH v9 12/14] PPC: Add crypto node in device tree Gaurav Jain
@ 2022-01-11 11:28 ` Gaurav Jain
2022-01-11 11:28 ` [PATCH v9 14/14] update CAAM MAINTAINER Gaurav Jain
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:28 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
removed sec_init() call and CONFIG_FSL_CAAM from defconfig.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 22 ++++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++--
arch/powerpc/include/asm/u-boot-ppc.h | 17 +++++++++++++++++
arch/powerpc/include/asm/u-boot.h | 1 +
configs/P2041RDB_defconfig | 1 -
configs/P3041DS_defconfig | 1 -
configs/P4080DS_defconfig | 1 -
configs/P5040DS_defconfig | 1 -
configs/T1024RDB_defconfig | 1 -
configs/T1042D4RDB_defconfig | 1 -
configs/T2080QDS_defconfig | 1 -
configs/T2080RDB_defconfig | 1 -
configs/T2080RDB_revD_defconfig | 1 -
configs/T4240RDB_defconfig | 1 -
14 files changed, 55 insertions(+), 12 deletions(-)
create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 4471754d02..6a30b91026 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -25,6 +25,8 @@ config TARGET_P3041DS
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -33,6 +35,8 @@ config TARGET_P4080DS
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -41,6 +45,8 @@ config TARGET_P5040DS
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -102,6 +108,8 @@ config TARGET_P2041RDB
select ARCH_P2041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
imply FSL_SATA
@@ -118,6 +126,8 @@ config TARGET_T1024RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_EEPROM
imply PANIC_HANG
@@ -127,6 +137,8 @@ config TARGET_T1042RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select ARCH_MISC_INIT
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -134,6 +146,8 @@ config TARGET_T1042D4RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -142,6 +156,8 @@ config TARGET_T1042RDB_PI
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T2080QDS
@@ -152,6 +168,8 @@ config TARGET_T2080QDS
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
config TARGET_T2080RDB
@@ -160,6 +178,8 @@ config TARGET_T2080RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -169,6 +189,8 @@ config TARGET_T4240RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ select FSL_CAAM
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e920e01b25..728c6447a8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -56,6 +56,7 @@
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
+#include <dm.h>
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
@@ -974,8 +975,6 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FSL_CAAM
- sec_init();
-
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
@@ -1014,6 +1013,20 @@ int cpu_init_r(void)
return 0;
}
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
void arch_preboot_os(void)
{
u32 msr;
diff --git a/arch/powerpc/include/asm/u-boot-ppc.h b/arch/powerpc/include/asm/u-boot-ppc.h
new file mode 100644
index 0000000000..372ca3e037
--- /dev/null
+++ b/arch/powerpc/include/asm/u-boot-ppc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2021 NXP
+ *
+ * Gaurav Jain <gaurav.jain@nxp.com>
+ */
+
+#ifndef _U_BOOT_PPC_H_
+#define _U_BOOT_PPC_H_
+
+#ifndef __ASSEMBLY__
+
+int arch_misc_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _U_BOOT_PPC_H_ */
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 19b3c0db5f..36af8e5403 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -21,5 +21,6 @@
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/ppc.h>
+#include <asm/u-boot-ppc.h>
#endif /* __U_BOOT_H__ */
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 53130ccf82..20bbb9b20e 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -37,7 +37,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 39dd70888c..834523633c 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 43f16d45e2..e0a9eacffe 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index d614917385..e1e0cbfc67 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 98f1d6c794..1cc1d6141e 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -46,7 +46,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 4797f2907f..88fe9e6d02 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -37,7 +37,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index db9e970e64..8af552f5b8 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -40,7 +40,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 6b076405d6..f53564e478 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -44,7 +44,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index 472463fabb..a5b632e2f5 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -45,7 +45,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index bbaab35fd8..e1544ea25d 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -36,7 +36,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v9 14/14] update CAAM MAINTAINER
2022-01-11 11:27 [PATCH v9 00/14] Add CAAM driver model support Gaurav Jain
` (12 preceding siblings ...)
2022-01-11 11:28 ` [PATCH v9 13/14] PPC: Enable Job ring driver model Gaurav Jain
@ 2022-01-11 11:28 ` Gaurav Jain
13 siblings, 0 replies; 20+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:28 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Michael Walle, Priyanka Jain, Ye Li, Horia Geanta, Ji Luo,
Franck Lenormand, Silvano Di Ninno, Sahil malhotra, Pankaj Gupta,
Varun Sethi, NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu,
Rajesh Bhagat, Meenakshi Aggarwal, Wasim Khan, Alison Wang,
Pramod Kumar, Tang Yuantian, Adrian Alonso, Vladimir Oltean,
Gaurav Jain
updated CAAM driver files maintainer.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f4bd3d79e2..1c912b2c65 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1334,3 +1334,9 @@ T: git https://source.denx.de/u-boot/u-boot.git
F: configs/tools-only_defconfig
F: *
F: */
+
+CAAM
+M: Gaurav Jain <gaurav.jain@nxp.com>
+S: Maintained
+F: drivers/crypto/fsl/
+F: include/fsl_sec.h
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread