From: Mark Rutland <mark.rutland@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: andre.przywara@arm.com, Jaxson.Han@arm.com, mark.rutland@arm.com,
robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com
Subject: [bootwrapper PATCH v2 10/13] aarch32: move the bulk of Secure PL1 initialization to C
Date: Fri, 14 Jan 2022 10:56:50 +0000 [thread overview]
Message-ID: <20220114105653.3003399-11-mark.rutland@arm.com> (raw)
In-Reply-To: <20220114105653.3003399-1-mark.rutland@arm.com>
The majority of state that we initialize at Secure PL1 is necessary for
code at lower PLs to function, but isnt' necessary for the boot-wrapper
itself. Given that, it would be better to write this in C where it can
be written mode clearly, and where it will be possible to add
logging/debug logic.
This patch migrates the AArch32 Secure PL1 initialization to C.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/aarch32/boot.S | 11 +----------
arch/aarch32/include/asm/cpu.h | 9 +++++++++
arch/aarch32/init.c | 12 ++++++++++++
3 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S
index ee073ea..820957b 100644
--- a/arch/aarch32/boot.S
+++ b/arch/aarch32/boot.S
@@ -63,16 +63,7 @@ _monitor:
/* Move the stack to Monitor mode*/
mrs sp, sp_svc
- /* Setup secure registers and devices */
- mov r0, #1 @ Non-secure lower level
- orr r0, #(1 << 8) @ HVC enable
- mcr p15, 0, r0, c1, c1, 0 @ SCR
-
- mov r0, #(1 << 10 | 1 << 11) @ Enable NS access to CPACR
- mcr p15, 0, r0, c1, c1, 2 @ NSACR
-
- ldr r0, =COUNTER_FREQ
- mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ
+ bl cpu_init_secure_pl1
bl cpu_init_bootwrapper
diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h
index aa72204..c1bce9a 100644
--- a/arch/aarch32/include/asm/cpu.h
+++ b/arch/aarch32/include/asm/cpu.h
@@ -30,6 +30,11 @@
#define PSR_I (1 << 7)
#define PSR_A (1 << 8)
+#define SCR_NS BIT(0)
+#define SCR_HCE BIT(8)
+
+#define NSACR_CP10 BIT(10)
+#define NSACR_CP11 BIT(11)
#define SPSR_KERNEL (PSR_A | PSR_I | PSR_F | PSR_HYP)
@@ -55,11 +60,15 @@ static inline unsigned long read_cpsr(void)
#define MPIDR "p15, 0, %0, c0, c0, 5"
#define ID_PFR1 "p15, 0, %0, c0, c1, 1"
+#define SCR "p15, 0, %0, c1, c1, 0"
+#define NSACR "p15, 0, %0, c1, c1, 2"
#define ICIALLU "p15, 0, %0, c7, c5, 0"
#define ICC_SRE "p15, 6, %0, c12, c12, 5"
#define ICC_CTLR "p15, 6, %0, c12, c12, 4"
+#define CNTFRQ "p15, 0, %0, c14, c0, 0"
+
#define mrc(reg) \
({ \
unsigned long __mrc_val; \
diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c
index b29ebb4..5b69dcd 100644
--- a/arch/aarch32/init.c
+++ b/arch/aarch32/init.c
@@ -28,3 +28,15 @@ void announce_arch(void)
print_string(mode_string());
print_string("\r\n");
}
+
+void cpu_init_secure_pl1(void)
+{
+ unsigned long scr = SCR_NS | SCR_HCE;
+ unsigned long nsacr = NSACR_CP10 | NSACR_CP11;
+
+ mcr(SCR, scr);
+
+ mcr(NSACR, nsacr);
+
+ mcr(CNTFRQ, COUNTER_FREQ);
+}
--
2.30.2
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next prev parent reply other threads:[~2022-01-14 11:01 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-14 10:56 [bootwrapper PATCH v2 00/13] Cleanups and improvements Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 01/13] Document entry requirements Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 02/13] Add bit-field macros Mark Rutland
2022-01-17 12:11 ` Steven Price
2022-01-17 13:28 ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 03/13] aarch64: add system register accessors Mark Rutland
2022-01-14 15:32 ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 04/13] aarch32: add coprocessor accessors Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 05/13] aarch64: add mov_64 macro Mark Rutland
2022-01-14 15:50 ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 06/13] aarch64: initialize SCTLR_ELx for the boot-wrapper Mark Rutland
2022-01-14 18:12 ` Andre Przywara
2022-01-17 12:15 ` Mark Rutland
2022-01-17 13:05 ` Mark Rutland
2022-01-18 12:37 ` Andre Przywara
2022-01-25 13:32 ` Mark Rutland
2022-01-19 12:42 ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 07/13] Rework common init C code Mark Rutland
2022-01-17 16:23 ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 08/13] Announce boot-wrapper mode / exception level Mark Rutland
2022-01-17 14:39 ` Andre Przywara
2022-01-17 15:50 ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 09/13] aarch64: move the bulk of EL3 initialization to C Mark Rutland
2022-01-17 14:31 ` Andre Przywara
2022-01-17 18:08 ` Mark Rutland
2022-01-17 18:31 ` Andre Przywara
2022-01-18 16:50 ` Mark Brown
2022-01-19 15:22 ` Mark Rutland
2022-01-14 10:56 ` Mark Rutland [this message]
2022-01-17 14:52 ` [bootwrapper PATCH v2 10/13] aarch32: move the bulk of Secure PL1 " Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 11/13] Announce locations of memory objects Mark Rutland
2022-01-14 15:30 ` Andre Przywara
2022-01-14 16:04 ` Robin Murphy
2022-01-14 16:30 ` Mark Rutland
2022-01-14 16:21 ` Mark Rutland
2022-01-17 14:59 ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 12/13] Rework bootmethod initialization Mark Rutland
2022-01-17 17:43 ` Andre Przywara
2022-01-25 14:00 ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 13/13] Unify start_el3 & start_no_el3 Mark Rutland
2022-01-17 17:43 ` Andre Przywara
2022-01-14 15:09 ` [bootwrapper PATCH v2 00/13] Cleanups and improvements Andre Przywara
2022-01-14 15:23 ` Mark Rutland
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