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From: Mark Rutland <mark.rutland@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: andre.przywara@arm.com, Jaxson.Han@arm.com, mark.rutland@arm.com,
	robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com
Subject: [bootwrapper PATCH v2 02/13] Add bit-field macros
Date: Fri, 14 Jan 2022 10:56:42 +0000	[thread overview]
Message-ID: <20220114105653.3003399-3-mark.rutland@arm.com> (raw)
In-Reply-To: <20220114105653.3003399-1-mark.rutland@arm.com>

Arm architectural documentation typically defines bit-fields as
`[msb,lsb]` and single-bit fields as `[bit]`. For clarity it would be
helpful if we could define fields in the same way.

Add helpers so that we can do so, along with helper to extract/insert
bit-field values.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 include/bits.h | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 include/bits.h

diff --git a/include/bits.h b/include/bits.h
new file mode 100644
index 0000000..0bf2c67
--- /dev/null
+++ b/include/bits.h
@@ -0,0 +1,79 @@
+/*
+ * include/bits.h - helpers for bit-field definitions.
+ *
+ * Copyright (C) 2021 ARM Limited. All rights reserved.
+ *
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE.txt file.
+ */
+#ifndef __BITS_H
+#define __BITS_H
+
+#ifdef __ASSEMBLY__
+#define UL(x)	x
+#define ULL(x)	x
+#else
+#define UL(x)	x##UL
+#define ULL(x)	x##ULL
+#endif
+
+/*
+ * Define a contiguous mask of bits with `msb` as the most significant bit and
+ * `lsb` as the least significant bit. The `msb` value must be greater than or
+ * equal to `lsb`.
+ *
+ * For example:
+ * - BITS(63, 63) is 0x8000000000000000
+ * - BITS(63, 0)  is 0xFFFFFFFFFFFFFFFF
+ * - BITS(0, 0)   is 0x0000000000000001
+ * - BITS(49, 17) is 0x0001FFFFFFFE0000
+ */
+#define BITS(msb, lsb) \
+	((~ULL(0) >> (63 - msb)) & (~ULL(0) << lsb))
+
+/*
+ * Define a mask of a single set bit `b`.
+ *
+ * For example:
+ * - BIT(63) is 0x8000000000000000
+ * - BIT(0)  is 0x0000000000000001
+ * - BIT(32) is 0x0000000100000000
+ */
+#define BIT(b)	BITS(b, b)
+
+/*
+ * Find the least significant set bit in the contiguous set of bits in `mask`.
+ *
+ * For example:
+ * - BITS_LSB(0x0000000000000001) is 0
+ * - BITS_LSB(0x000000000000ff00) is 8
+ * - BITS_LSB(0x8000000000000000) is 63
+ */
+#define BITS_LSB(mask)	(__builtin_ffsll(mask) - 1)
+
+/*
+ * Extract a bit-field out of `val` described by the contiguous set of bits in
+ * `mask`.
+ *
+ * For example:
+ * - BITS_EXTRACT(0xABCD, BITS(15, 12)) is 0xA
+ * - BITS_EXTRACT(0xABCD, BITS(11, 8))  is 0xB
+ * - BITS_EXTRACT(0xABCD, BIT(7))       is 0x1
+ */
+#define BITS_EXTRACT(val, mask) \
+	(((val) & (mask)) >> BITS_LSB(mask))
+
+/*
+ * Insert the least significant bits of `val` into the bit-field described by
+ * the contiguous set of bits in `mask`.
+ *
+ * For example:
+ * - BITS_INSERT(BITS(3, 0), 0xA)   is 0x000A
+ * - BITS_INSERT(BITS(15, 12), 0xA) is 0xA000
+ * - BITS_INSERT(BIT(15), 0xF)      is 0x1000
+ *
+ */
+#define BITS_INSERT(mask, val) \
+	(((val) << BITS_LSB(mask)) & (mask))
+
+#endif
-- 
2.30.2


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  parent reply	other threads:[~2022-01-14 10:58 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-14 10:56 [bootwrapper PATCH v2 00/13] Cleanups and improvements Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 01/13] Document entry requirements Mark Rutland
2022-01-14 10:56 ` Mark Rutland [this message]
2022-01-17 12:11   ` [bootwrapper PATCH v2 02/13] Add bit-field macros Steven Price
2022-01-17 13:28     ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 03/13] aarch64: add system register accessors Mark Rutland
2022-01-14 15:32   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 04/13] aarch32: add coprocessor accessors Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 05/13] aarch64: add mov_64 macro Mark Rutland
2022-01-14 15:50   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 06/13] aarch64: initialize SCTLR_ELx for the boot-wrapper Mark Rutland
2022-01-14 18:12   ` Andre Przywara
2022-01-17 12:15     ` Mark Rutland
2022-01-17 13:05       ` Mark Rutland
2022-01-18 12:37         ` Andre Przywara
2022-01-25 13:32           ` Mark Rutland
2022-01-19 12:42       ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 07/13] Rework common init C code Mark Rutland
2022-01-17 16:23   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 08/13] Announce boot-wrapper mode / exception level Mark Rutland
2022-01-17 14:39   ` Andre Przywara
2022-01-17 15:50     ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 09/13] aarch64: move the bulk of EL3 initialization to C Mark Rutland
2022-01-17 14:31   ` Andre Przywara
2022-01-17 18:08     ` Mark Rutland
2022-01-17 18:31       ` Andre Przywara
2022-01-18 16:50         ` Mark Brown
2022-01-19 15:22           ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 10/13] aarch32: move the bulk of Secure PL1 " Mark Rutland
2022-01-17 14:52   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 11/13] Announce locations of memory objects Mark Rutland
2022-01-14 15:30   ` Andre Przywara
2022-01-14 16:04     ` Robin Murphy
2022-01-14 16:30       ` Mark Rutland
2022-01-14 16:21     ` Mark Rutland
2022-01-17 14:59   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 12/13] Rework bootmethod initialization Mark Rutland
2022-01-17 17:43   ` Andre Przywara
2022-01-25 14:00     ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 13/13] Unify start_el3 & start_no_el3 Mark Rutland
2022-01-17 17:43   ` Andre Przywara
2022-01-14 15:09 ` [bootwrapper PATCH v2 00/13] Cleanups and improvements Andre Przywara
2022-01-14 15:23   ` Mark Rutland

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