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From: Mark Brown <broonie@kernel.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org, Jaxson.Han@arm.com,
	robin.murphy@arm.com, vladimir.murzin@arm.com, Wei.Chen@arm.com
Subject: Re: [bootwrapper PATCH v2 09/13] aarch64: move the bulk of EL3 initialization to C
Date: Tue, 18 Jan 2022 16:50:12 +0000	[thread overview]
Message-ID: <YebvxEI+cnYMDu1j@sirena.org.uk> (raw)
In-Reply-To: <20220117183117.7f29dc66@donnerap.cambridge.arm.com>


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On Mon, Jan 17, 2022 at 06:31:17PM +0000, Andre Przywara wrote:
> Mark Rutland <mark.rutland@arm.com> wrote:
> > On Mon, Jan 17, 2022 at 02:31:04PM +0000, Andre Przywara wrote:
> > > On Fri, 14 Jan 2022 10:56:49 +0000
> > > Mark Rutland <mark.rutland@arm.com> wrote:

[Out of office this week so replies might be intermittent]

> > > And apart from bit 0 missing from it (as noted above), the existing
> > > code writes 0x1ff into that register, presumable to cover future
> > > vector length extensions beyond 2048 bits (which those RAZ/WI fields
> > > in bits[8:4] seem to suggest).  

> > Hmm... I went and found the SVE supplement and I can't see any rationale
> > for what SW *should* do, nor can I find a description of the register
> > (that seems to have been factored into some XML files I can't convince
> > anything to load on my machine).

...

> > TBH, I'm not sure. In the absence of some documented guidance I'd prefer
> > to go with 0xf, but given we already use 0x1ff, I want to dig into this
> > a bit more.

I'm fairly sure I've seen some explicit discussion of this lurking
somewhere, though I couldn't tell you where - DDI0584 A.i doesn't spell
out the enumeration algorithm unfortunately AFAICT.  The theory is that
the extra bits are reserved for any future extension of the vector
length if needed since it'd be inconvenient to have to split the vector
length field up.

> My impression was that this "[8:4] = RAZ/WI" compared to the "[63:9] =
> RES0" fields suggests this is for a potential extension, but I guess there
> would be more changes needed if SVE ever goes beyond 2048. So chances are
> high we need to adopt the code then anyway, and fixing the number then is
> the least of our problems.

> So I feel we should stick to what's explicitly documented, and put 0xf in
> there.

We shouldn't need particularly many changes if the size of the field
ever gets raised, with everything being dynamically sized already and
the existing code starting off setting the WI bits to 1 the updates that
are needed should just be on input validation.

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  reply	other threads:[~2022-01-18 16:51 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-14 10:56 [bootwrapper PATCH v2 00/13] Cleanups and improvements Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 01/13] Document entry requirements Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 02/13] Add bit-field macros Mark Rutland
2022-01-17 12:11   ` Steven Price
2022-01-17 13:28     ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 03/13] aarch64: add system register accessors Mark Rutland
2022-01-14 15:32   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 04/13] aarch32: add coprocessor accessors Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 05/13] aarch64: add mov_64 macro Mark Rutland
2022-01-14 15:50   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 06/13] aarch64: initialize SCTLR_ELx for the boot-wrapper Mark Rutland
2022-01-14 18:12   ` Andre Przywara
2022-01-17 12:15     ` Mark Rutland
2022-01-17 13:05       ` Mark Rutland
2022-01-18 12:37         ` Andre Przywara
2022-01-25 13:32           ` Mark Rutland
2022-01-19 12:42       ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 07/13] Rework common init C code Mark Rutland
2022-01-17 16:23   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 08/13] Announce boot-wrapper mode / exception level Mark Rutland
2022-01-17 14:39   ` Andre Przywara
2022-01-17 15:50     ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 09/13] aarch64: move the bulk of EL3 initialization to C Mark Rutland
2022-01-17 14:31   ` Andre Przywara
2022-01-17 18:08     ` Mark Rutland
2022-01-17 18:31       ` Andre Przywara
2022-01-18 16:50         ` Mark Brown [this message]
2022-01-19 15:22           ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 10/13] aarch32: move the bulk of Secure PL1 " Mark Rutland
2022-01-17 14:52   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 11/13] Announce locations of memory objects Mark Rutland
2022-01-14 15:30   ` Andre Przywara
2022-01-14 16:04     ` Robin Murphy
2022-01-14 16:30       ` Mark Rutland
2022-01-14 16:21     ` Mark Rutland
2022-01-17 14:59   ` Andre Przywara
2022-01-14 10:56 ` [bootwrapper PATCH v2 12/13] Rework bootmethod initialization Mark Rutland
2022-01-17 17:43   ` Andre Przywara
2022-01-25 14:00     ` Mark Rutland
2022-01-14 10:56 ` [bootwrapper PATCH v2 13/13] Unify start_el3 & start_no_el3 Mark Rutland
2022-01-17 17:43   ` Andre Przywara
2022-01-14 15:09 ` [bootwrapper PATCH v2 00/13] Cleanups and improvements Andre Przywara
2022-01-14 15:23   ` Mark Rutland

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