From: Weiwei Li <liweiwei@iscas.ac.cn> To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>, lazyparser@gmail.com Subject: [PATCH v4 0/4] support subsets of virtual memory extension Date: Sun, 16 Jan 2022 10:59:21 +0800 [thread overview] Message-ID: <20220116025925.29973-1-liweiwei@iscas.ac.cn> (raw) This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. Specification: https://github.com/riscv/virtual-memory/tree/main/specs The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v4 To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'. This implementation can pass the riscv-tests for rv64ssvnapot. v4: * fix encodings for hinval_vvma and hinval_gvma * partition inner PTE check into several steps added in first, second and fourth commits * improve commit messages to describe changes v3: * drop "x-" in exposed properties v2: * add extension check for svnapot and svpbmt Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension target/riscv/cpu.c | 4 ++ target/riscv/cpu.h | 3 + target/riscv/cpu_bits.h | 4 ++ target/riscv/cpu_helper.c | 27 ++++++-- target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ target/riscv/translate.c | 1 + 7 files changed, 117 insertions(+), 4 deletions(-) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: anup@brainfault.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [PATCH v4 0/4] support subsets of virtual memory extension Date: Sun, 16 Jan 2022 10:59:21 +0800 [thread overview] Message-ID: <20220116025925.29973-1-liweiwei@iscas.ac.cn> (raw) This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. Specification: https://github.com/riscv/virtual-memory/tree/main/specs The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v4 To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'. This implementation can pass the riscv-tests for rv64ssvnapot. v4: * fix encodings for hinval_vvma and hinval_gvma * partition inner PTE check into several steps added in first, second and fourth commits * improve commit messages to describe changes v3: * drop "x-" in exposed properties v2: * add extension check for svnapot and svpbmt Weiwei Li (4): target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension target/riscv/cpu.c | 4 ++ target/riscv/cpu.h | 3 + target/riscv/cpu_bits.h | 4 ++ target/riscv/cpu_helper.c | 27 ++++++-- target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ target/riscv/translate.c | 1 + 7 files changed, 117 insertions(+), 4 deletions(-) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc -- 2.17.1
next reply other threads:[~2022-01-16 3:06 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-16 2:59 Weiwei Li [this message] 2022-01-16 2:59 ` [PATCH v4 0/4] support subsets of virtual memory extension Weiwei Li 2022-01-16 2:59 ` [PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 2:59 ` [PATCH v4 2/4] target/riscv: add support for svnapot extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 4:29 ` Anup Patel 2022-01-16 4:29 ` Anup Patel 2022-01-16 2:59 ` [PATCH v4 3/4] target/riscv: add support for svinval extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-16 2:59 ` [PATCH v4 4/4] target/riscv: add support for svpbmt extension Weiwei Li 2022-01-16 2:59 ` Weiwei Li 2022-01-17 7:18 ` Guo Ren 2022-01-17 7:18 ` Guo Ren 2022-01-17 8:28 ` Weiwei Li 2022-01-17 8:28 ` Weiwei Li
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