From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
richard.henderson@linaro.org, palmer@dabbelt.com,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v7 18/22] target/riscv: Fix check range for first fault only
Date: Wed, 19 Jan 2022 13:18:20 +0800 [thread overview]
Message-ID: <20220119051824.17494-19-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220119051824.17494-1-zhiwei_liu@c-sky.com>
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8b7c9ec890..efb3129532 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -500,12 +500,12 @@ vext_ldff(void *vd, void *v0, target_ulong base,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
+ if (page_check_range(addr, offset, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
bin.meng@windriver.com, richard.henderson@linaro.org,
guoren@linux.alibaba.com, LIU Zhiwei <zhiwei_liu@c-sky.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v7 18/22] target/riscv: Fix check range for first fault only
Date: Wed, 19 Jan 2022 13:18:20 +0800 [thread overview]
Message-ID: <20220119051824.17494-19-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220119051824.17494-1-zhiwei_liu@c-sky.com>
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8b7c9ec890..efb3129532 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -500,12 +500,12 @@ vext_ldff(void *vd, void *v0, target_ulong base,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
+ if (page_check_range(addr, offset, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
--
2.25.1
next prev parent reply other threads:[~2022-01-19 5:49 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 5:18 [PATCH v7 00/22] Support UXL filed in xstatus LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 05/22] target/riscv: Create xl field in env LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 07/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 09/22] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 11/22] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 13/22] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 15/22] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei [this message]
2022-01-19 5:18 ` [PATCH v7 18/22] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 19/22] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 21/22] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
2022-01-20 0:35 ` Alistair Francis
2022-01-20 0:35 ` Alistair Francis
2022-01-20 2:12 ` LIU Zhiwei
2022-01-20 2:12 ` LIU Zhiwei
2022-01-20 3:29 ` Alistair Francis
2022-01-20 3:29 ` Alistair Francis
2022-01-20 5:15 ` LIU Zhiwei
2022-01-20 5:15 ` LIU Zhiwei
2022-01-20 2:33 ` LIU Zhiwei
2022-01-20 2:33 ` LIU Zhiwei
2022-01-19 5:18 ` [PATCH v7 22/22] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-19 5:18 ` LIU Zhiwei
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