All of lore.kernel.org
 help / color / mirror / Atom feed
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
	richard.henderson@linaro.org, palmer@dabbelt.com,
	Alistair Francis <alistair.francis@wdc.com>,
	LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v7 02/22] target/riscv: Don't save pc when exception return
Date: Wed, 19 Jan 2022 13:18:04 +0800	[thread overview]
Message-ID: <20220119051824.17494-3-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220119051824.17494-1-zhiwei_liu@c-sky.com>

As pc will be written by the xepc in exception return, just ignore
pc in translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                          | 4 ++--
 target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
 target/riscv/op_helper.c                       | 4 ++--
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6cf6d6ce98..72cc2582f4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -100,8 +100,8 @@ DEF_HELPER_2(csrr_i128, tl, env, int)
 DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
 DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 #ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 75c6ef80a6..6077bbbf11 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
 static bool trans_sret(DisasContext *ctx, arg_sret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
     if (has_ext(ctx, RVS)) {
-        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+        gen_helper_sret(cpu_pc, cpu_env);
         tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
@@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 static bool trans_mret(DisasContext *ctx, arg_mret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+    gen_helper_mret(cpu_pc, cpu_env);
     tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 6f040f2fb9..67693cb42b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -115,7 +115,7 @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
 
 #ifndef CONFIG_USER_ONLY
 
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
     target_ulong prev_priv, prev_virt;
@@ -176,7 +176,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
     return retpc;
 }
 
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
 {
     if (!(env->priv >= PRV_M)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	bin.meng@windriver.com, richard.henderson@linaro.org,
	guoren@linux.alibaba.com, LIU Zhiwei <zhiwei_liu@c-sky.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v7 02/22] target/riscv: Don't save pc when exception return
Date: Wed, 19 Jan 2022 13:18:04 +0800	[thread overview]
Message-ID: <20220119051824.17494-3-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220119051824.17494-1-zhiwei_liu@c-sky.com>

As pc will be written by the xepc in exception return, just ignore
pc in translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                          | 4 ++--
 target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
 target/riscv/op_helper.c                       | 4 ++--
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6cf6d6ce98..72cc2582f4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -100,8 +100,8 @@ DEF_HELPER_2(csrr_i128, tl, env, int)
 DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
 DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 #ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 75c6ef80a6..6077bbbf11 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
 static bool trans_sret(DisasContext *ctx, arg_sret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
     if (has_ext(ctx, RVS)) {
-        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+        gen_helper_sret(cpu_pc, cpu_env);
         tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
@@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 static bool trans_mret(DisasContext *ctx, arg_mret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+    gen_helper_mret(cpu_pc, cpu_env);
     tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 6f040f2fb9..67693cb42b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -115,7 +115,7 @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
 
 #ifndef CONFIG_USER_ONLY
 
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
     target_ulong prev_priv, prev_virt;
@@ -176,7 +176,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
     return retpc;
 }
 
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
 {
     if (!(env->priv >= PRV_M)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-- 
2.25.1



  parent reply	other threads:[~2022-01-19  5:22 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-19  5:18 [PATCH v7 00/22] Support UXL filed in xstatus LIU Zhiwei
2022-01-19  5:18 ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` LIU Zhiwei [this message]
2022-01-19  5:18   ` [PATCH v7 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 05/22] target/riscv: Create xl field in env LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 07/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 09/22] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 11/22] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 13/22] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 15/22] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 18/22] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 19/22] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 21/22] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei
2022-01-20  0:35   ` Alistair Francis
2022-01-20  0:35     ` Alistair Francis
2022-01-20  2:12     ` LIU Zhiwei
2022-01-20  2:12       ` LIU Zhiwei
2022-01-20  3:29       ` Alistair Francis
2022-01-20  3:29         ` Alistair Francis
2022-01-20  5:15         ` LIU Zhiwei
2022-01-20  5:15           ` LIU Zhiwei
2022-01-20  2:33     ` LIU Zhiwei
2022-01-20  2:33       ` LIU Zhiwei
2022-01-19  5:18 ` [PATCH v7 22/22] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-19  5:18   ` LIU Zhiwei

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220119051824.17494-3-zhiwei_liu@c-sky.com \
    --to=zhiwei_liu@c-sky.com \
    --cc=alistair.francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=guoren@linux.alibaba.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.