* [PATCH 0/3] Flush G2H handler during a GT reset
@ 2022-01-19 21:24 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: john.c.harrison
After a small fix to error capture code, we now can flush G2H during a
GT reset which simplifies code and seals some extreme corner case races.
v2:
(CI)
- Don't trigger GT reset from G2H handler
v3:
- Address John Harrison's comments
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (3):
drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL
drm/i915/guc: Add work queue to trigger a GT reset
drm/i915/guc: Flush G2H handler during a GT reset
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++-------
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
3 files changed, 44 insertions(+), 22 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 0/3] Flush G2H handler during a GT reset
@ 2022-01-19 21:24 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx
After a small fix to error capture code, we now can flush G2H during a
GT reset which simplifies code and seals some extreme corner case races.
v2:
(CI)
- Don't trigger GT reset from G2H handler
v3:
- Address John Harrison's comments
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Matthew Brost (3):
drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL
drm/i915/guc: Add work queue to trigger a GT reset
drm/i915/guc: Flush G2H handler during a GT reset
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++-------
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
3 files changed, 44 insertions(+), 22 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
@ 2022-01-19 21:24 ` Matthew Brost
-1 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: john.c.harrison
Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than
GFP_KERNEL to fully decouple the error capture from fence signalling.
v2:
(John Harrison)
- Fix typo in commit message (s/do/to)
Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code")
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 67f3515f07e7..aee42eae4729 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1516,7 +1516,7 @@ capture_engine(struct intel_engine_cs *engine,
struct i915_request *rq = NULL;
unsigned long flags;
- ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
+ ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL);
if (!ee)
return NULL;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL
@ 2022-01-19 21:24 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx
Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than
GFP_KERNEL to fully decouple the error capture from fence signalling.
v2:
(John Harrison)
- Fix typo in commit message (s/do/to)
Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code")
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 67f3515f07e7..aee42eae4729 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1516,7 +1516,7 @@ capture_engine(struct intel_engine_cs *engine,
struct i915_request *rq = NULL;
unsigned long flags;
- ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
+ ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL);
if (!ee)
return NULL;
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
@ 2022-01-19 21:24 ` Matthew Brost
-1 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: john.c.harrison
The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT when an engine reset failure is received to break this
circular dependency.
v2:
(John Harrison)
- Store engine reset mask
- Fix typo in commit message
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++--
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d26a86fe557..c4a9fc7dd246 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -119,6 +119,15 @@ struct intel_guc {
* function as it might be in an atomic context (no sleeping)
*/
struct work_struct destroyed_worker;
+ /**
+ * @reset_worker: worker to trigger a GT reset after an engine
+ * reset fails
+ */
+ struct work_struct reset_worker;
+ /**
+ * @reset_mask: mask of engines that failed to reset
+ */
+ intel_engine_mask_t reset_mask;
} submission_state;
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114f..514b3060b141 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
}
static void destroyed_worker_func(struct work_struct *w);
+static void reset_worker_func(struct work_struct *w);
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
@@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
INIT_WORK(&guc->submission_state.destroyed_worker,
destroyed_worker_func);
+ INIT_WORK(&guc->submission_state.reset_worker,
+ reset_worker_func);
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
@@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
return gt->engine_class[engine_class][instance];
}
+static void reset_worker_func(struct work_struct *w)
+{
+ struct intel_guc *guc = container_of(w, struct intel_guc,
+ submission_state.reset_worker);
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_engine_mask_t reset_mask;
+ unsigned long flags;
+
+ spin_lock_irqsave(&guc->submission_state.lock, flags);
+ reset_mask = guc->submission_state.reset_mask;
+ guc->submission_state.reset_mask = 0;
+ spin_unlock_irqrestore(&guc->submission_state.lock, flags);
+
+ if (likely(reset_mask))
+ intel_gt_handle_error(gt, reset_mask,
+ I915_ERROR_CAPTURE,
+ "GuC failed to reset engine mask=0x%x\n",
+ reset_mask);
+}
+
int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len)
{
@@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
+ unsigned long flags;
if (unlikely(len != 3)) {
drm_err(>->i915->drm, "Invalid length %u", len);
@@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
guc_class, instance, engine->name, reason);
- intel_gt_handle_error(gt, engine->mask,
- I915_ERROR_CAPTURE,
- "GuC failed to reset %s (reason=0x%08x)\n",
- engine->name, reason);
+ spin_lock_irqsave(&guc->submission_state.lock, flags);
+ guc->submission_state.reset_mask |= engine->mask;
+ spin_unlock_irqrestore(&guc->submission_state.lock, flags);
+
+ /*
+ * A GT reset flushes this worker queue (G2H handler) so we must use
+ * another worker to trigger a GT reset.
+ */
+ queue_work(system_unbound_wq, &guc->submission_state.reset_worker);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
@ 2022-01-19 21:24 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx
The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT when an engine reset failure is received to break this
circular dependency.
v2:
(John Harrison)
- Store engine reset mask
- Fix typo in commit message
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++--
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d26a86fe557..c4a9fc7dd246 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -119,6 +119,15 @@ struct intel_guc {
* function as it might be in an atomic context (no sleeping)
*/
struct work_struct destroyed_worker;
+ /**
+ * @reset_worker: worker to trigger a GT reset after an engine
+ * reset fails
+ */
+ struct work_struct reset_worker;
+ /**
+ * @reset_mask: mask of engines that failed to reset
+ */
+ intel_engine_mask_t reset_mask;
} submission_state;
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114f..514b3060b141 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
}
static void destroyed_worker_func(struct work_struct *w);
+static void reset_worker_func(struct work_struct *w);
/*
* Set up the memory resources to be shared with the GuC (via the GGTT)
@@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
INIT_WORK(&guc->submission_state.destroyed_worker,
destroyed_worker_func);
+ INIT_WORK(&guc->submission_state.reset_worker,
+ reset_worker_func);
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
@@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
return gt->engine_class[engine_class][instance];
}
+static void reset_worker_func(struct work_struct *w)
+{
+ struct intel_guc *guc = container_of(w, struct intel_guc,
+ submission_state.reset_worker);
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_engine_mask_t reset_mask;
+ unsigned long flags;
+
+ spin_lock_irqsave(&guc->submission_state.lock, flags);
+ reset_mask = guc->submission_state.reset_mask;
+ guc->submission_state.reset_mask = 0;
+ spin_unlock_irqrestore(&guc->submission_state.lock, flags);
+
+ if (likely(reset_mask))
+ intel_gt_handle_error(gt, reset_mask,
+ I915_ERROR_CAPTURE,
+ "GuC failed to reset engine mask=0x%x\n",
+ reset_mask);
+}
+
int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len)
{
@@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
+ unsigned long flags;
if (unlikely(len != 3)) {
drm_err(>->i915->drm, "Invalid length %u", len);
@@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
guc_class, instance, engine->name, reason);
- intel_gt_handle_error(gt, engine->mask,
- I915_ERROR_CAPTURE,
- "GuC failed to reset %s (reason=0x%08x)\n",
- engine->name, reason);
+ spin_lock_irqsave(&guc->submission_state.lock, flags);
+ guc->submission_state.reset_mask |= engine->mask;
+ spin_unlock_irqrestore(&guc->submission_state.lock, flags);
+
+ /*
+ * A GT reset flushes this worker queue (G2H handler) so we must use
+ * another worker to trigger a GT reset.
+ */
+ queue_work(system_unbound_wq, &guc->submission_state.reset_worker);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
@ 2022-01-19 21:24 ` Matthew Brost
-1 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: john.c.harrison
Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which in turn depends on resets) we
can safely flush the G2H handler during a GT reset. This is eliminates
corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.
v2:
(John Harrison)
- Fix typo in commit message (s/is/in)
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 514b3060b141..406dd2e3f5a9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
void intel_guc_submission_reset_prepare(struct intel_guc *guc)
{
- int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
guc_flush_submissions(guc);
guc_flush_destroyed_contexts(guc);
-
- /*
- * Handle any outstanding G2Hs before reset. Call IRQ handler directly
- * each pass as interrupt have been disabled. We always scrub for
- * outstanding G2H as it is possible for outstanding_submission_g2h to
- * be incremented after the context state update.
- */
- for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
- intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
- intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
- do {
- wait_for_reset(guc, &guc->outstanding_submission_g2h);
- } while (!list_empty(&guc->ct.requests.incoming));
- }
+ flush_work(&guc->ct.requests.worker);
scrub_guc_desc_for_outstanding_g2h(guc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
@ 2022-01-19 21:24 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw)
To: dri-devel, intel-gfx
Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which in turn depends on resets) we
can safely flush the G2H handler during a GT reset. This is eliminates
corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.
v2:
(John Harrison)
- Fix typo in commit message (s/is/in)
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 514b3060b141..406dd2e3f5a9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
void intel_guc_submission_reset_prepare(struct intel_guc *guc)
{
- int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
guc_flush_submissions(guc);
guc_flush_destroyed_contexts(guc);
-
- /*
- * Handle any outstanding G2Hs before reset. Call IRQ handler directly
- * each pass as interrupt have been disabled. We always scrub for
- * outstanding G2H as it is possible for outstanding_submission_g2h to
- * be incremented after the context state update.
- */
- for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
- intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
- intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
- do {
- wait_for_reset(guc, &guc->outstanding_submission_g2h);
- } while (!list_empty(&guc->ct.requests.incoming));
- }
+ flush_work(&guc->ct.requests.worker);
scrub_guc_desc_for_outstanding_g2h(guc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Flush G2H handler during a GT reset (rev3)
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
` (3 preceding siblings ...)
(?)
@ 2022-01-19 23:49 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-19 23:49 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
== Series Details ==
Series: Flush G2H handler during a GT reset (rev3)
URL : https://patchwork.freedesktop.org/series/98855/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Flush G2H handler during a GT reset (rev3)
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
` (4 preceding siblings ...)
(?)
@ 2022-01-20 0:20 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-20 0:20 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5459 bytes --]
== Series Details ==
Series: Flush G2H handler during a GT reset (rev3)
URL : https://patchwork.freedesktop.org/series/98855/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11111 -> Patchwork_22030
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/index.html
Participating hosts (45 -> 42)
------------------------------
Additional (1): fi-kbl-soraka
Missing (4): fi-bsw-cyan fi-icl-u2 fi-bdw-samus fi-pnv-d510
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22030:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_softpin@allocator-basic-reserve:
- {bat-jsl-2}: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/bat-jsl-2/igt@gem_softpin@allocator-basic-reserve.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/bat-jsl-2/igt@gem_softpin@allocator-basic-reserve.html
Known issues
------------
Here are the changes found in Patchwork_22030 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][4] -> [INCOMPLETE][5] ([i915#4547])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][9] -> [DMESG-FAIL][10] ([i915#4494])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Warnings ####
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][13] ([i915#4312]) -> [FAIL][14] ([i915#2722] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/fi-skl-6600u/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/fi-skl-6600u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11111 -> Patchwork_22030
CI-20190529: 20190529
CI_DRM_11111: fe44f8bdb12374a6168cb561834eb714097f5e5f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22030: dd4a9107b83ca4f990d91aeeb9847229009001b4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dd4a9107b83c drm/i915/guc: Flush G2H handler during a GT reset
9296d3ca5cf1 drm/i915/guc: Add work queue to trigger a GT reset
544ae134b0f1 drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/index.html
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Flush G2H handler during a GT reset (rev3)
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
` (5 preceding siblings ...)
(?)
@ 2022-01-20 4:01 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-20 4:01 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30265 bytes --]
== Series Details ==
Series: Flush G2H handler during a GT reset (rev3)
URL : https://patchwork.freedesktop.org/series/98855/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11111_full -> Patchwork_22030_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22030_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22030_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22030_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@fences-dpms:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb7/igt@i915_pm_rpm@fences-dpms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb7/igt@i915_pm_rpm@fences-dpms.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-iclb: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
Known issues
------------
Here are the changes found in Patchwork_22030_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-tglb: NOTRUN -> [DMESG-WARN][5] ([i915#3002] / [i915#4856])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@gem_create@create-massive.html
- shard-skl: NOTRUN -> [DMESG-WARN][6] ([i915#3002])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-snb6/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#232])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-tglb6/igt@gem_eio@kms.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb8/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][10] -> [SKIP][11] ([i915#4525]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb1/igt@gem_exec_balancer@parallel.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb8/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][12] ([i915#2846])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +188 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl10/igt@gem_exec_params@no-vebox.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#112283])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb6/igt@gem_exec_params@secure-non-root.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl4/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#2856])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb6/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][21] ([i915#1886] / [i915#2291])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl1/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][22] ([i915#4272])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@kms_async_flips@crc.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#111614]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][24] -> [DMESG-WARN][25] ([i915#118])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-glk8/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][28] ([i915#3763]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110723])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][30] ([i915#3743])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271]) +51 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl4/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +8 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl10/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109278] / [i915#3886])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][35] ([fdo#111615] / [i915#3689]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl4/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3689] / [i915#3886])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +7 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl2/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +13 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@kms_chamelium@vga-hpd-for-each-pipe.html
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-snb6/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][46] ([i915#1319])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl4/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@type1:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109300] / [fdo#111066])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#3359]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding:
- shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271]) +20 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-snb6/igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#109274] / [fdo#111825]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#79])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#79])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [PASS][56] -> [INCOMPLETE][57] ([i915#3614])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][58] -> [SKIP][59] ([i915#3701])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][60] -> [DMESG-WARN][61] ([i915#180]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271]) +108 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109280]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][64] ([fdo#109280] / [fdo#111825]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][65] -> [DMESG-WARN][66] ([i915#180]) +4 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][69] ([fdo#108145] / [i915#265])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][70] -> [FAIL][71] ([fdo#108145] / [i915#265])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][74] -> [SKIP][75] ([fdo#109441]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb1/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109441])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][77] ([i915#180])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-c-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][80] ([i915#2530])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb6/igt@nouveau_crc@pipe-c-source-outp-inactive.html
* igt@prime_nv_test@i915_import_gtt_mmap:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109291])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@prime_nv_test@i915_import_gtt_mmap.html
* igt@syncobj_basic@bad-destroy-pad:
- shard-iclb: [PASS][82] -> [DMESG-WARN][83] ([i915#4391])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb3/igt@syncobj_basic@bad-destroy-pad.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb7/igt@syncobj_basic@bad-destroy-pad.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2994]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl4/igt@sysfs_clients@create.html
* igt@sysfs_clients@recycle-many:
- shard-skl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2994]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [TIMEOUT][86] ([i915#3063]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-tglb1/igt@gem_eio@in-flight-contexts-immediate.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb2/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][88] ([i915#4525]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][90] ([i915#2842]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][92] ([i915#2842]) -> [PASS][93] +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][94] ([i915#2190]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb5/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][96] ([i915#4281]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][98] ([i915#3921]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-snb6/igt@i915_selftest@live@hangcheck.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@debugfs-reader:
- shard-skl: [INCOMPLETE][100] -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-skl8/igt@i915_suspend@debugfs-reader.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl6/igt@i915_suspend@debugfs-reader.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][102] ([i915#180] / [i915#1982]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][104] ([i915#2122]) -> [PASS][105] +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-suspend@b-vga1:
- shard-snb: [SKIP][108] ([fdo#109271]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-snb6/igt@kms_flip@flip-vs-suspend@b-vga1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-snb4/igt@kms_flip@flip-vs-suspend@b-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-iclb: [SKIP][110] ([i915#3701]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-iclb: [INCOMPLETE][112] -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-apl6/igt@kms_hdr@bpc-switch-suspend.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-apl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +3 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][122] ([i915#232]) -> [TIMEOUT][123] ([i915#3063] / [i915#3648])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-tglb1/igt@gem_eio@unwedge-stress.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][124] ([i915#2842]) -> [FAIL][125] ([i915#2852])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: [FAIL][126] ([i915#2842]) -> [FAIL][127] ([i915#2849])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-tglb1/igt@gem_exec_fair@basic-throttle@rcs0.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][128] ([i915#1804] / [i915#2684]) -> [WARN][129] ([i915#2684])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][130] ([fdo#111068] / [i915#658]) -> [SKIP][131] ([i915#2920])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-iclb8/igt@kms_psr2_sf@cursor-plane-update-sf.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#92]) -> ([FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#602] / [i915#92])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl7/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl4/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11111/shard-kbl7/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/dr
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22030/index.html
[-- Attachment #2: Type: text/html, Size: 33439 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
@ 2022-01-21 1:34 ` John Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John Harrison @ 2022-01-21 1:34 UTC (permalink / raw)
To: Matthew Brost, dri-devel, intel-gfx
On 1/19/2022 13:24, Matthew Brost wrote:
> The G2H handler needs to be flushed during a GT reset but a G2H
> indicating engine reset failure can trigger a GT reset. Add a worker to
> trigger the GT when an engine reset failure is received to break this
trigger the GT reset?
> circular dependency.
>
> v2:
> (John Harrison)
> - Store engine reset mask
> - Fix typo in commit message
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++--
> 2 files changed, 42 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 9d26a86fe557..c4a9fc7dd246 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -119,6 +119,15 @@ struct intel_guc {
> * function as it might be in an atomic context (no sleeping)
> */
> struct work_struct destroyed_worker;
> + /**
> + * @reset_worker: worker to trigger a GT reset after an engine
> + * reset fails
> + */
> + struct work_struct reset_worker;
> + /**
> + * @reset_mask: mask of engines that failed to reset
> + */
> + intel_engine_mask_t reset_mask;
reset_fail_mask might be a less ambiguous name? Same for the worker
struct and function.
John.
> } submission_state;
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 3918f1be114f..514b3060b141 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
> }
>
> static void destroyed_worker_func(struct work_struct *w);
> +static void reset_worker_func(struct work_struct *w);
>
> /*
> * Set up the memory resources to be shared with the GuC (via the GGTT)
> @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
> INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
> INIT_WORK(&guc->submission_state.destroyed_worker,
> destroyed_worker_func);
> + INIT_WORK(&guc->submission_state.reset_worker,
> + reset_worker_func);
>
> guc->submission_state.guc_ids_bitmap =
> bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
> return gt->engine_class[engine_class][instance];
> }
>
> +static void reset_worker_func(struct work_struct *w)
> +{
> + struct intel_guc *guc = container_of(w, struct intel_guc,
> + submission_state.reset_worker);
> + struct intel_gt *gt = guc_to_gt(guc);
> + intel_engine_mask_t reset_mask;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&guc->submission_state.lock, flags);
> + reset_mask = guc->submission_state.reset_mask;
> + guc->submission_state.reset_mask = 0;
> + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> +
> + if (likely(reset_mask))
> + intel_gt_handle_error(gt, reset_mask,
> + I915_ERROR_CAPTURE,
> + "GuC failed to reset engine mask=0x%x\n",
> + reset_mask);
> +}
> +
> int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> const u32 *msg, u32 len)
> {
> @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> struct intel_gt *gt = guc_to_gt(guc);
> u8 guc_class, instance;
> u32 reason;
> + unsigned long flags;
>
> if (unlikely(len != 3)) {
> drm_err(>->i915->drm, "Invalid length %u", len);
> @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
> guc_class, instance, engine->name, reason);
>
> - intel_gt_handle_error(gt, engine->mask,
> - I915_ERROR_CAPTURE,
> - "GuC failed to reset %s (reason=0x%08x)\n",
> - engine->name, reason);
> + spin_lock_irqsave(&guc->submission_state.lock, flags);
> + guc->submission_state.reset_mask |= engine->mask;
> + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> +
> + /*
> + * A GT reset flushes this worker queue (G2H handler) so we must use
> + * another worker to trigger a GT reset.
> + */
> + queue_work(system_unbound_wq, &guc->submission_state.reset_worker);
>
> return 0;
> }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
@ 2022-01-21 1:34 ` John Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John Harrison @ 2022-01-21 1:34 UTC (permalink / raw)
To: Matthew Brost, dri-devel, intel-gfx
On 1/19/2022 13:24, Matthew Brost wrote:
> The G2H handler needs to be flushed during a GT reset but a G2H
> indicating engine reset failure can trigger a GT reset. Add a worker to
> trigger the GT when an engine reset failure is received to break this
trigger the GT reset?
> circular dependency.
>
> v2:
> (John Harrison)
> - Store engine reset mask
> - Fix typo in commit message
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++--
> 2 files changed, 42 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 9d26a86fe557..c4a9fc7dd246 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -119,6 +119,15 @@ struct intel_guc {
> * function as it might be in an atomic context (no sleeping)
> */
> struct work_struct destroyed_worker;
> + /**
> + * @reset_worker: worker to trigger a GT reset after an engine
> + * reset fails
> + */
> + struct work_struct reset_worker;
> + /**
> + * @reset_mask: mask of engines that failed to reset
> + */
> + intel_engine_mask_t reset_mask;
reset_fail_mask might be a less ambiguous name? Same for the worker
struct and function.
John.
> } submission_state;
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 3918f1be114f..514b3060b141 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
> }
>
> static void destroyed_worker_func(struct work_struct *w);
> +static void reset_worker_func(struct work_struct *w);
>
> /*
> * Set up the memory resources to be shared with the GuC (via the GGTT)
> @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
> INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
> INIT_WORK(&guc->submission_state.destroyed_worker,
> destroyed_worker_func);
> + INIT_WORK(&guc->submission_state.reset_worker,
> + reset_worker_func);
>
> guc->submission_state.guc_ids_bitmap =
> bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
> return gt->engine_class[engine_class][instance];
> }
>
> +static void reset_worker_func(struct work_struct *w)
> +{
> + struct intel_guc *guc = container_of(w, struct intel_guc,
> + submission_state.reset_worker);
> + struct intel_gt *gt = guc_to_gt(guc);
> + intel_engine_mask_t reset_mask;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&guc->submission_state.lock, flags);
> + reset_mask = guc->submission_state.reset_mask;
> + guc->submission_state.reset_mask = 0;
> + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> +
> + if (likely(reset_mask))
> + intel_gt_handle_error(gt, reset_mask,
> + I915_ERROR_CAPTURE,
> + "GuC failed to reset engine mask=0x%x\n",
> + reset_mask);
> +}
> +
> int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> const u32 *msg, u32 len)
> {
> @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> struct intel_gt *gt = guc_to_gt(guc);
> u8 guc_class, instance;
> u32 reason;
> + unsigned long flags;
>
> if (unlikely(len != 3)) {
> drm_err(>->i915->drm, "Invalid length %u", len);
> @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
> guc_class, instance, engine->name, reason);
>
> - intel_gt_handle_error(gt, engine->mask,
> - I915_ERROR_CAPTURE,
> - "GuC failed to reset %s (reason=0x%08x)\n",
> - engine->name, reason);
> + spin_lock_irqsave(&guc->submission_state.lock, flags);
> + guc->submission_state.reset_mask |= engine->mask;
> + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> +
> + /*
> + * A GT reset flushes this worker queue (G2H handler) so we must use
> + * another worker to trigger a GT reset.
> + */
> + queue_work(system_unbound_wq, &guc->submission_state.reset_worker);
>
> return 0;
> }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
@ 2022-01-21 1:36 ` John Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John Harrison @ 2022-01-21 1:36 UTC (permalink / raw)
To: Matthew Brost, dri-devel, intel-gfx
On 1/19/2022 13:24, Matthew Brost wrote:
> Now that the error capture is fully decoupled from fence signalling
> (request retirement to free memory, which in turn depends on resets) we
> can safely flush the G2H handler during a GT reset. This is eliminates
This eliminates
John.
> corner cases where GuC generated G2H (e.g. engine resets) race with a GT
> reset.
>
> v2:
> (John Harrison)
> - Fix typo in commit message (s/is/in)
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
> 1 file changed, 1 insertion(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 514b3060b141..406dd2e3f5a9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
>
> void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> {
> - int i;
> -
> if (unlikely(!guc_submission_initialized(guc))) {
> /* Reset called during driver load? GuC not yet initialised! */
> return;
> @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
>
> guc_flush_submissions(guc);
> guc_flush_destroyed_contexts(guc);
> -
> - /*
> - * Handle any outstanding G2Hs before reset. Call IRQ handler directly
> - * each pass as interrupt have been disabled. We always scrub for
> - * outstanding G2H as it is possible for outstanding_submission_g2h to
> - * be incremented after the context state update.
> - */
> - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
> - intel_guc_to_host_event_handler(guc);
> -#define wait_for_reset(guc, wait_var) \
> - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
> - do {
> - wait_for_reset(guc, &guc->outstanding_submission_g2h);
> - } while (!list_empty(&guc->ct.requests.incoming));
> - }
> + flush_work(&guc->ct.requests.worker);
>
> scrub_guc_desc_for_outstanding_g2h(guc);
> }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
@ 2022-01-21 1:36 ` John Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John Harrison @ 2022-01-21 1:36 UTC (permalink / raw)
To: Matthew Brost, dri-devel, intel-gfx
On 1/19/2022 13:24, Matthew Brost wrote:
> Now that the error capture is fully decoupled from fence signalling
> (request retirement to free memory, which in turn depends on resets) we
> can safely flush the G2H handler during a GT reset. This is eliminates
This eliminates
John.
> corner cases where GuC generated G2H (e.g. engine resets) race with a GT
> reset.
>
> v2:
> (John Harrison)
> - Fix typo in commit message (s/is/in)
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
> 1 file changed, 1 insertion(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 514b3060b141..406dd2e3f5a9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
>
> void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> {
> - int i;
> -
> if (unlikely(!guc_submission_initialized(guc))) {
> /* Reset called during driver load? GuC not yet initialised! */
> return;
> @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
>
> guc_flush_submissions(guc);
> guc_flush_destroyed_contexts(guc);
> -
> - /*
> - * Handle any outstanding G2Hs before reset. Call IRQ handler directly
> - * each pass as interrupt have been disabled. We always scrub for
> - * outstanding G2H as it is possible for outstanding_submission_g2h to
> - * be incremented after the context state update.
> - */
> - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
> - intel_guc_to_host_event_handler(guc);
> -#define wait_for_reset(guc, wait_var) \
> - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
> - do {
> - wait_for_reset(guc, &guc->outstanding_submission_g2h);
> - } while (!list_empty(&guc->ct.requests.incoming));
> - }
> + flush_work(&guc->ct.requests.worker);
>
> scrub_guc_desc_for_outstanding_g2h(guc);
> }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
2022-01-21 1:34 ` [Intel-gfx] " John Harrison
@ 2022-01-21 4:04 ` Matthew Brost
-1 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-21 4:04 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel
On Thu, Jan 20, 2022 at 05:34:54PM -0800, John Harrison wrote:
> On 1/19/2022 13:24, Matthew Brost wrote:
> > The G2H handler needs to be flushed during a GT reset but a G2H
> > indicating engine reset failure can trigger a GT reset. Add a worker to
> > trigger the GT when an engine reset failure is received to break this
> trigger the GT reset?
>
Yes.
> > circular dependency.
> >
> > v2:
> > (John Harrison)
> > - Store engine reset mask
> > - Fix typo in commit message
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++--
> > 2 files changed, 42 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 9d26a86fe557..c4a9fc7dd246 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -119,6 +119,15 @@ struct intel_guc {
> > * function as it might be in an atomic context (no sleeping)
> > */
> > struct work_struct destroyed_worker;
> > + /**
> > + * @reset_worker: worker to trigger a GT reset after an engine
> > + * reset fails
> > + */
> > + struct work_struct reset_worker;
> > + /**
> > + * @reset_mask: mask of engines that failed to reset
> > + */
> > + intel_engine_mask_t reset_mask;
> reset_fail_mask might be a less ambiguous name? Same for the worker struct
> and function.
>
How about:
struct {
worker;
mask;
} engine_reset_fail;
Matt
> John.
>
> > } submission_state;
> > /**
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 3918f1be114f..514b3060b141 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
> > }
> > static void destroyed_worker_func(struct work_struct *w);
> > +static void reset_worker_func(struct work_struct *w);
> > /*
> > * Set up the memory resources to be shared with the GuC (via the GGTT)
> > @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
> > INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
> > INIT_WORK(&guc->submission_state.destroyed_worker,
> > destroyed_worker_func);
> > + INIT_WORK(&guc->submission_state.reset_worker,
> > + reset_worker_func);
> > guc->submission_state.guc_ids_bitmap =
> > bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> > @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
> > return gt->engine_class[engine_class][instance];
> > }
> > +static void reset_worker_func(struct work_struct *w)
> > +{
> > + struct intel_guc *guc = container_of(w, struct intel_guc,
> > + submission_state.reset_worker);
> > + struct intel_gt *gt = guc_to_gt(guc);
> > + intel_engine_mask_t reset_mask;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&guc->submission_state.lock, flags);
> > + reset_mask = guc->submission_state.reset_mask;
> > + guc->submission_state.reset_mask = 0;
> > + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> > +
> > + if (likely(reset_mask))
> > + intel_gt_handle_error(gt, reset_mask,
> > + I915_ERROR_CAPTURE,
> > + "GuC failed to reset engine mask=0x%x\n",
> > + reset_mask);
> > +}
> > +
> > int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> > const u32 *msg, u32 len)
> > {
> > @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> > struct intel_gt *gt = guc_to_gt(guc);
> > u8 guc_class, instance;
> > u32 reason;
> > + unsigned long flags;
> > if (unlikely(len != 3)) {
> > drm_err(>->i915->drm, "Invalid length %u", len);
> > @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> > drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
> > guc_class, instance, engine->name, reason);
> > - intel_gt_handle_error(gt, engine->mask,
> > - I915_ERROR_CAPTURE,
> > - "GuC failed to reset %s (reason=0x%08x)\n",
> > - engine->name, reason);
> > + spin_lock_irqsave(&guc->submission_state.lock, flags);
> > + guc->submission_state.reset_mask |= engine->mask;
> > + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> > +
> > + /*
> > + * A GT reset flushes this worker queue (G2H handler) so we must use
> > + * another worker to trigger a GT reset.
> > + */
> > + queue_work(system_unbound_wq, &guc->submission_state.reset_worker);
> > return 0;
> > }
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset
@ 2022-01-21 4:04 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-21 4:04 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel
On Thu, Jan 20, 2022 at 05:34:54PM -0800, John Harrison wrote:
> On 1/19/2022 13:24, Matthew Brost wrote:
> > The G2H handler needs to be flushed during a GT reset but a G2H
> > indicating engine reset failure can trigger a GT reset. Add a worker to
> > trigger the GT when an engine reset failure is received to break this
> trigger the GT reset?
>
Yes.
> > circular dependency.
> >
> > v2:
> > (John Harrison)
> > - Store engine reset mask
> > - Fix typo in commit message
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++--
> > 2 files changed, 42 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 9d26a86fe557..c4a9fc7dd246 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -119,6 +119,15 @@ struct intel_guc {
> > * function as it might be in an atomic context (no sleeping)
> > */
> > struct work_struct destroyed_worker;
> > + /**
> > + * @reset_worker: worker to trigger a GT reset after an engine
> > + * reset fails
> > + */
> > + struct work_struct reset_worker;
> > + /**
> > + * @reset_mask: mask of engines that failed to reset
> > + */
> > + intel_engine_mask_t reset_mask;
> reset_fail_mask might be a less ambiguous name? Same for the worker struct
> and function.
>
How about:
struct {
worker;
mask;
} engine_reset_fail;
Matt
> John.
>
> > } submission_state;
> > /**
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 3918f1be114f..514b3060b141 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
> > }
> > static void destroyed_worker_func(struct work_struct *w);
> > +static void reset_worker_func(struct work_struct *w);
> > /*
> > * Set up the memory resources to be shared with the GuC (via the GGTT)
> > @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
> > INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
> > INIT_WORK(&guc->submission_state.destroyed_worker,
> > destroyed_worker_func);
> > + INIT_WORK(&guc->submission_state.reset_worker,
> > + reset_worker_func);
> > guc->submission_state.guc_ids_bitmap =
> > bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> > @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
> > return gt->engine_class[engine_class][instance];
> > }
> > +static void reset_worker_func(struct work_struct *w)
> > +{
> > + struct intel_guc *guc = container_of(w, struct intel_guc,
> > + submission_state.reset_worker);
> > + struct intel_gt *gt = guc_to_gt(guc);
> > + intel_engine_mask_t reset_mask;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&guc->submission_state.lock, flags);
> > + reset_mask = guc->submission_state.reset_mask;
> > + guc->submission_state.reset_mask = 0;
> > + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> > +
> > + if (likely(reset_mask))
> > + intel_gt_handle_error(gt, reset_mask,
> > + I915_ERROR_CAPTURE,
> > + "GuC failed to reset engine mask=0x%x\n",
> > + reset_mask);
> > +}
> > +
> > int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> > const u32 *msg, u32 len)
> > {
> > @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> > struct intel_gt *gt = guc_to_gt(guc);
> > u8 guc_class, instance;
> > u32 reason;
> > + unsigned long flags;
> > if (unlikely(len != 3)) {
> > drm_err(>->i915->drm, "Invalid length %u", len);
> > @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> > drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X",
> > guc_class, instance, engine->name, reason);
> > - intel_gt_handle_error(gt, engine->mask,
> > - I915_ERROR_CAPTURE,
> > - "GuC failed to reset %s (reason=0x%08x)\n",
> > - engine->name, reason);
> > + spin_lock_irqsave(&guc->submission_state.lock, flags);
> > + guc->submission_state.reset_mask |= engine->mask;
> > + spin_unlock_irqrestore(&guc->submission_state.lock, flags);
> > +
> > + /*
> > + * A GT reset flushes this worker queue (G2H handler) so we must use
> > + * another worker to trigger a GT reset.
> > + */
> > + queue_work(system_unbound_wq, &guc->submission_state.reset_worker);
> > return 0;
> > }
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
2022-01-21 1:36 ` [Intel-gfx] " John Harrison
@ 2022-01-21 4:05 ` Matthew Brost
-1 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-21 4:05 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel
On Thu, Jan 20, 2022 at 05:36:22PM -0800, John Harrison wrote:
> On 1/19/2022 13:24, Matthew Brost wrote:
> > Now that the error capture is fully decoupled from fence signalling
> > (request retirement to free memory, which in turn depends on resets) we
> > can safely flush the G2H handler during a GT reset. This is eliminates
> This eliminates
>
> John.
>
Yep, will fixup in the next rev.
Matt
> > corner cases where GuC generated G2H (e.g. engine resets) race with a GT
> > reset.
> >
> > v2:
> > (John Harrison)
> > - Fix typo in commit message (s/is/in)
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> > ---
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
> > 1 file changed, 1 insertion(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 514b3060b141..406dd2e3f5a9 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
> > void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> > {
> > - int i;
> > -
> > if (unlikely(!guc_submission_initialized(guc))) {
> > /* Reset called during driver load? GuC not yet initialised! */
> > return;
> > @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> > guc_flush_submissions(guc);
> > guc_flush_destroyed_contexts(guc);
> > -
> > - /*
> > - * Handle any outstanding G2Hs before reset. Call IRQ handler directly
> > - * each pass as interrupt have been disabled. We always scrub for
> > - * outstanding G2H as it is possible for outstanding_submission_g2h to
> > - * be incremented after the context state update.
> > - */
> > - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
> > - intel_guc_to_host_event_handler(guc);
> > -#define wait_for_reset(guc, wait_var) \
> > - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
> > - do {
> > - wait_for_reset(guc, &guc->outstanding_submission_g2h);
> > - } while (!list_empty(&guc->ct.requests.incoming));
> > - }
> > + flush_work(&guc->ct.requests.worker);
> > scrub_guc_desc_for_outstanding_g2h(guc);
> > }
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
@ 2022-01-21 4:05 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-21 4:05 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel
On Thu, Jan 20, 2022 at 05:36:22PM -0800, John Harrison wrote:
> On 1/19/2022 13:24, Matthew Brost wrote:
> > Now that the error capture is fully decoupled from fence signalling
> > (request retirement to free memory, which in turn depends on resets) we
> > can safely flush the G2H handler during a GT reset. This is eliminates
> This eliminates
>
> John.
>
Yep, will fixup in the next rev.
Matt
> > corner cases where GuC generated G2H (e.g. engine resets) race with a GT
> > reset.
> >
> > v2:
> > (John Harrison)
> > - Fix typo in commit message (s/is/in)
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> > ---
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
> > 1 file changed, 1 insertion(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 514b3060b141..406dd2e3f5a9 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
> > void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> > {
> > - int i;
> > -
> > if (unlikely(!guc_submission_initialized(guc))) {
> > /* Reset called during driver load? GuC not yet initialised! */
> > return;
> > @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> > guc_flush_submissions(guc);
> > guc_flush_destroyed_contexts(guc);
> > -
> > - /*
> > - * Handle any outstanding G2Hs before reset. Call IRQ handler directly
> > - * each pass as interrupt have been disabled. We always scrub for
> > - * outstanding G2H as it is possible for outstanding_submission_g2h to
> > - * be incremented after the context state update.
> > - */
> > - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
> > - intel_guc_to_host_event_handler(guc);
> > -#define wait_for_reset(guc, wait_var) \
> > - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
> > - do {
> > - wait_for_reset(guc, &guc->outstanding_submission_g2h);
> > - } while (!list_empty(&guc->ct.requests.incoming));
> > - }
> > + flush_work(&guc->ct.requests.worker);
> > scrub_guc_desc_for_outstanding_g2h(guc);
> > }
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
2022-01-21 4:31 [PATCH 0/3] Flush G2H handler during a GT reset Matthew Brost
@ 2022-01-21 4:31 ` Matthew Brost
0 siblings, 0 replies; 22+ messages in thread
From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: john.c.harrison
Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which in turn depends on resets) we
can safely flush the G2H handler during a GT reset. This eliminates
corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.
v2:
(John Harrison)
- Fix typo in commit message (s/is/in)
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9a3f503d201aa..1331ff91c5b05 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
void intel_guc_submission_reset_prepare(struct intel_guc *guc)
{
- int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
guc_flush_submissions(guc);
guc_flush_destroyed_contexts(guc);
-
- /*
- * Handle any outstanding G2Hs before reset. Call IRQ handler directly
- * each pass as interrupt have been disabled. We always scrub for
- * outstanding G2H as it is possible for outstanding_submission_g2h to
- * be incremented after the context state update.
- */
- for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
- intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
- intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
- do {
- wait_for_reset(guc, &guc->outstanding_submission_g2h);
- } while (!list_empty(&guc->ct.requests.incoming));
- }
+ flush_work(&guc->ct.requests.worker);
scrub_guc_desc_for_outstanding_g2h(guc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
2022-01-18 21:43 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost
@ 2022-01-19 1:38 ` John Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John Harrison @ 2022-01-19 1:38 UTC (permalink / raw)
To: Matthew Brost, intel-gfx, dri-devel; +Cc: thomas.hellstrom
On 1/18/2022 13:43, Matthew Brost wrote:
> Now that the error capture is fully decoupled from fence signalling
> (request retirement to free memory, which is turn depends on resets) we
s/is/in/
With that fixed:
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
John.
> can safely flush the G2H handler during a GT reset. This is eliminates
> corner cases where GuC generated G2H (e.g. engine resets) race with a GT
> reset.
>
> Signed-off-by: Matthew Brost <mattthew.brost@intel.com>
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
> 1 file changed, 1 insertion(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index cdd8d691251ff..1a11e8986948b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
>
> void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> {
> - int i;
> -
> if (unlikely(!guc_submission_initialized(guc))) {
> /* Reset called during driver load? GuC not yet initialised! */
> return;
> @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
>
> guc_flush_submissions(guc);
> guc_flush_destroyed_contexts(guc);
> -
> - /*
> - * Handle any outstanding G2Hs before reset. Call IRQ handler directly
> - * each pass as interrupt have been disabled. We always scrub for
> - * outstanding G2H as it is possible for outstanding_submission_g2h to
> - * be incremented after the context state update.
> - */
> - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
> - intel_guc_to_host_event_handler(guc);
> -#define wait_for_reset(guc, wait_var) \
> - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
> - do {
> - wait_for_reset(guc, &guc->outstanding_submission_g2h);
> - } while (!list_empty(&guc->ct.requests.incoming));
> - }
> + flush_work(&guc->ct.requests.worker);
>
> scrub_guc_desc_for_outstanding_g2h(guc);
> }
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset
2022-01-18 21:43 [PATCH 0/3] " Matthew Brost
@ 2022-01-18 21:43 ` Matthew Brost
2022-01-19 1:38 ` John Harrison
0 siblings, 1 reply; 22+ messages in thread
From: Matthew Brost @ 2022-01-18 21:43 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: thomas.hellstrom, john.c.harrison
Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which is turn depends on resets) we
can safely flush the G2H handler during a GT reset. This is eliminates
corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.
Signed-off-by: Matthew Brost <mattthew.brost@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index cdd8d691251ff..1a11e8986948b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc);
void intel_guc_submission_reset_prepare(struct intel_guc *guc)
{
- int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
guc_flush_submissions(guc);
guc_flush_destroyed_contexts(guc);
-
- /*
- * Handle any outstanding G2Hs before reset. Call IRQ handler directly
- * each pass as interrupt have been disabled. We always scrub for
- * outstanding G2H as it is possible for outstanding_submission_g2h to
- * be incremented after the context state update.
- */
- for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) {
- intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
- intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
- do {
- wait_for_reset(guc, &guc->outstanding_submission_g2h);
- } while (!list_empty(&guc->ct.requests.incoming));
- }
+ flush_work(&guc->ct.requests.worker);
scrub_guc_desc_for_outstanding_g2h(guc);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
end of thread, other threads:[~2022-01-21 4:37 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-19 21:24 [PATCH 0/3] Flush G2H handler during a GT reset Matthew Brost
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
2022-01-19 21:24 ` [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL Matthew Brost
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
2022-01-19 21:24 ` [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset Matthew Brost
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
2022-01-21 1:34 ` John Harrison
2022-01-21 1:34 ` [Intel-gfx] " John Harrison
2022-01-21 4:04 ` Matthew Brost
2022-01-21 4:04 ` [Intel-gfx] " Matthew Brost
2022-01-19 21:24 ` [PATCH 3/3] drm/i915/guc: Flush G2H handler during " Matthew Brost
2022-01-19 21:24 ` [Intel-gfx] " Matthew Brost
2022-01-21 1:36 ` John Harrison
2022-01-21 1:36 ` [Intel-gfx] " John Harrison
2022-01-21 4:05 ` Matthew Brost
2022-01-21 4:05 ` [Intel-gfx] " Matthew Brost
2022-01-19 23:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Flush G2H handler during a GT reset (rev3) Patchwork
2022-01-20 0:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-20 4:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-01-21 4:31 [PATCH 0/3] Flush G2H handler during a GT reset Matthew Brost
2022-01-21 4:31 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost
2022-01-18 21:43 [PATCH 0/3] " Matthew Brost
2022-01-18 21:43 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost
2022-01-19 1:38 ` John Harrison
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