* [PATCH 0/3] Flush G2H handler during a GT reset @ 2022-01-21 4:31 ` Matthew Brost 0 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: john.c.harrison After a small fix to error capture code, we now can flush G2H during a GT reset which simplifies code and seals some extreme corner case races. v2: (CI) - Don't trigger GT reset from G2H handler v3: - Address John Harrison's comments v4: - Address John Harrison's comments Signed-off-by: Matthew Brost <matthew.brost@intel.com> Matthew Brost (3): drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL drm/i915/guc: Add work queue to trigger a GT reset drm/i915/guc: Flush G2H handler during a GT reset drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++------- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 3 files changed, 44 insertions(+), 22 deletions(-) -- 2.34.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 0/3] Flush G2H handler during a GT reset @ 2022-01-21 4:31 ` Matthew Brost 0 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel After a small fix to error capture code, we now can flush G2H during a GT reset which simplifies code and seals some extreme corner case races. v2: (CI) - Don't trigger GT reset from G2H handler v3: - Address John Harrison's comments v4: - Address John Harrison's comments Signed-off-by: Matthew Brost <matthew.brost@intel.com> Matthew Brost (3): drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL drm/i915/guc: Add work queue to trigger a GT reset drm/i915/guc: Flush G2H handler during a GT reset drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++------- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 3 files changed, 44 insertions(+), 22 deletions(-) -- 2.34.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost @ 2022-01-21 4:31 ` Matthew Brost -1 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: john.c.harrison Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than GFP_KERNEL to fully decouple the error capture from fence signalling. v2: (John Harrison) - Fix typo in commit message (s/do/to) Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code") Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 67f3515f07e7a..aee42eae4729f 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1516,7 +1516,7 @@ capture_engine(struct intel_engine_cs *engine, struct i915_request *rq = NULL; unsigned long flags; - ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); + ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL); if (!ee) return NULL; -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL @ 2022-01-21 4:31 ` Matthew Brost 0 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than GFP_KERNEL to fully decouple the error capture from fence signalling. v2: (John Harrison) - Fix typo in commit message (s/do/to) Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code") Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 67f3515f07e7a..aee42eae4729f 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1516,7 +1516,7 @@ capture_engine(struct intel_engine_cs *engine, struct i915_request *rq = NULL; unsigned long flags; - ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); + ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL); if (!ee) return NULL; -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost @ 2022-01-21 4:31 ` Matthew Brost -1 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: john.c.harrison The G2H handler needs to be flushed during a GT reset but a G2H indicating engine reset failure can trigger a GT reset. Add a worker to trigger the GT rest when an engine reset failure is received to break this circular dependency. v2: (John Harrison) - Store engine reset mask - Fix typo in commit message v3: (John Harrison) - Fix another typo in commit message - s/reset_*/reset_fail_*/ Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++-- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 9d26a86fe557a..d59bbf49d1c2b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -119,6 +119,15 @@ struct intel_guc { * function as it might be in an atomic context (no sleeping) */ struct work_struct destroyed_worker; + /** + * @reset_fail_worker: worker to trigger a GT reset after an + * engine reset fails + */ + struct work_struct reset_fail_worker; + /** + * @reset_fail_mask: mask of engines that failed to reset + */ + intel_engine_mask_t reset_fail_mask; } submission_state; /** diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 3918f1be114fa..9a3f503d201aa 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc) } static void destroyed_worker_func(struct work_struct *w); +static void reset_fail_worker_func(struct work_struct *w); /* * Set up the memory resources to be shared with the GuC (via the GGTT) @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc) INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts); INIT_WORK(&guc->submission_state.destroyed_worker, destroyed_worker_func); + INIT_WORK(&guc->submission_state.reset_fail_worker, + reset_fail_worker_func); guc->submission_state.guc_ids_bitmap = bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL); @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance) return gt->engine_class[engine_class][instance]; } +static void reset_fail_worker_func(struct work_struct *w) +{ + struct intel_guc *guc = container_of(w, struct intel_guc, + submission_state.reset_fail_worker); + struct intel_gt *gt = guc_to_gt(guc); + intel_engine_mask_t reset_fail_mask; + unsigned long flags; + + spin_lock_irqsave(&guc->submission_state.lock, flags); + reset_fail_mask = guc->submission_state.reset_fail_mask; + guc->submission_state.reset_fail_mask = 0; + spin_unlock_irqrestore(&guc->submission_state.lock, flags); + + if (likely(reset_fail_mask)) + intel_gt_handle_error(gt, reset_fail_mask, + I915_ERROR_CAPTURE, + "GuC failed to reset engine mask=0x%x\n", + reset_fail_mask); +} + int intel_guc_engine_failure_process_msg(struct intel_guc *guc, const u32 *msg, u32 len) { @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, struct intel_gt *gt = guc_to_gt(guc); u8 guc_class, instance; u32 reason; + unsigned long flags; if (unlikely(len != 3)) { drm_err(>->i915->drm, "Invalid length %u", len); @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X", guc_class, instance, engine->name, reason); - intel_gt_handle_error(gt, engine->mask, - I915_ERROR_CAPTURE, - "GuC failed to reset %s (reason=0x%08x)\n", - engine->name, reason); + spin_lock_irqsave(&guc->submission_state.lock, flags); + guc->submission_state.reset_fail_mask |= engine->mask; + spin_unlock_irqrestore(&guc->submission_state.lock, flags); + + /* + * A GT reset flushes this worker queue (G2H handler) so we must use + * another worker to trigger a GT reset. + */ + queue_work(system_unbound_wq, &guc->submission_state.reset_fail_worker); return 0; } -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset @ 2022-01-21 4:31 ` Matthew Brost 0 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel The G2H handler needs to be flushed during a GT reset but a G2H indicating engine reset failure can trigger a GT reset. Add a worker to trigger the GT rest when an engine reset failure is received to break this circular dependency. v2: (John Harrison) - Store engine reset mask - Fix typo in commit message v3: (John Harrison) - Fix another typo in commit message - s/reset_*/reset_fail_*/ Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++-- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 9d26a86fe557a..d59bbf49d1c2b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -119,6 +119,15 @@ struct intel_guc { * function as it might be in an atomic context (no sleeping) */ struct work_struct destroyed_worker; + /** + * @reset_fail_worker: worker to trigger a GT reset after an + * engine reset fails + */ + struct work_struct reset_fail_worker; + /** + * @reset_fail_mask: mask of engines that failed to reset + */ + intel_engine_mask_t reset_fail_mask; } submission_state; /** diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 3918f1be114fa..9a3f503d201aa 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc) } static void destroyed_worker_func(struct work_struct *w); +static void reset_fail_worker_func(struct work_struct *w); /* * Set up the memory resources to be shared with the GuC (via the GGTT) @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc) INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts); INIT_WORK(&guc->submission_state.destroyed_worker, destroyed_worker_func); + INIT_WORK(&guc->submission_state.reset_fail_worker, + reset_fail_worker_func); guc->submission_state.guc_ids_bitmap = bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL); @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance) return gt->engine_class[engine_class][instance]; } +static void reset_fail_worker_func(struct work_struct *w) +{ + struct intel_guc *guc = container_of(w, struct intel_guc, + submission_state.reset_fail_worker); + struct intel_gt *gt = guc_to_gt(guc); + intel_engine_mask_t reset_fail_mask; + unsigned long flags; + + spin_lock_irqsave(&guc->submission_state.lock, flags); + reset_fail_mask = guc->submission_state.reset_fail_mask; + guc->submission_state.reset_fail_mask = 0; + spin_unlock_irqrestore(&guc->submission_state.lock, flags); + + if (likely(reset_fail_mask)) + intel_gt_handle_error(gt, reset_fail_mask, + I915_ERROR_CAPTURE, + "GuC failed to reset engine mask=0x%x\n", + reset_fail_mask); +} + int intel_guc_engine_failure_process_msg(struct intel_guc *guc, const u32 *msg, u32 len) { @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, struct intel_gt *gt = guc_to_gt(guc); u8 guc_class, instance; u32 reason; + unsigned long flags; if (unlikely(len != 3)) { drm_err(>->i915->drm, "Invalid length %u", len); @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X", guc_class, instance, engine->name, reason); - intel_gt_handle_error(gt, engine->mask, - I915_ERROR_CAPTURE, - "GuC failed to reset %s (reason=0x%08x)\n", - engine->name, reason); + spin_lock_irqsave(&guc->submission_state.lock, flags); + guc->submission_state.reset_fail_mask |= engine->mask; + spin_unlock_irqrestore(&guc->submission_state.lock, flags); + + /* + * A GT reset flushes this worker queue (G2H handler) so we must use + * another worker to trigger a GT reset. + */ + queue_work(system_unbound_wq, &guc->submission_state.reset_fail_worker); return 0; } -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost @ 2022-01-21 18:53 ` John Harrison -1 siblings, 0 replies; 18+ messages in thread From: John Harrison @ 2022-01-21 18:53 UTC (permalink / raw) To: Matthew Brost, intel-gfx, dri-devel On 1/20/2022 20:31, Matthew Brost wrote: > The G2H handler needs to be flushed during a GT reset but a G2H > indicating engine reset failure can trigger a GT reset. Add a worker to > trigger the GT rest when an engine reset failure is received to break > this circular dependency. > > v2: > (John Harrison) > - Store engine reset mask > - Fix typo in commit message > v3: > (John Harrison) > - Fix another typo in commit message > - s/reset_*/reset_fail_*/ > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++ > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++-- > 2 files changed, 42 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > index 9d26a86fe557a..d59bbf49d1c2b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > @@ -119,6 +119,15 @@ struct intel_guc { > * function as it might be in an atomic context (no sleeping) > */ > struct work_struct destroyed_worker; > + /** > + * @reset_fail_worker: worker to trigger a GT reset after an > + * engine reset fails > + */ > + struct work_struct reset_fail_worker; > + /** > + * @reset_fail_mask: mask of engines that failed to reset > + */ > + intel_engine_mask_t reset_fail_mask; > } submission_state; > > /** > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 3918f1be114fa..9a3f503d201aa 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc) > } > > static void destroyed_worker_func(struct work_struct *w); > +static void reset_fail_worker_func(struct work_struct *w); > > /* > * Set up the memory resources to be shared with the GuC (via the GGTT) > @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc) > INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts); > INIT_WORK(&guc->submission_state.destroyed_worker, > destroyed_worker_func); > + INIT_WORK(&guc->submission_state.reset_fail_worker, > + reset_fail_worker_func); > > guc->submission_state.guc_ids_bitmap = > bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL); > @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance) > return gt->engine_class[engine_class][instance]; > } > > +static void reset_fail_worker_func(struct work_struct *w) > +{ > + struct intel_guc *guc = container_of(w, struct intel_guc, > + submission_state.reset_fail_worker); > + struct intel_gt *gt = guc_to_gt(guc); > + intel_engine_mask_t reset_fail_mask; > + unsigned long flags; > + > + spin_lock_irqsave(&guc->submission_state.lock, flags); > + reset_fail_mask = guc->submission_state.reset_fail_mask; > + guc->submission_state.reset_fail_mask = 0; > + spin_unlock_irqrestore(&guc->submission_state.lock, flags); > + > + if (likely(reset_fail_mask)) > + intel_gt_handle_error(gt, reset_fail_mask, > + I915_ERROR_CAPTURE, > + "GuC failed to reset engine mask=0x%x\n", > + reset_fail_mask); > +} > + > int intel_guc_engine_failure_process_msg(struct intel_guc *guc, > const u32 *msg, u32 len) > { > @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, > struct intel_gt *gt = guc_to_gt(guc); > u8 guc_class, instance; > u32 reason; > + unsigned long flags; > > if (unlikely(len != 3)) { > drm_err(>->i915->drm, "Invalid length %u", len); > @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, > drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X", > guc_class, instance, engine->name, reason); > > - intel_gt_handle_error(gt, engine->mask, > - I915_ERROR_CAPTURE, > - "GuC failed to reset %s (reason=0x%08x)\n", > - engine->name, reason); > + spin_lock_irqsave(&guc->submission_state.lock, flags); > + guc->submission_state.reset_fail_mask |= engine->mask; > + spin_unlock_irqrestore(&guc->submission_state.lock, flags); > + > + /* > + * A GT reset flushes this worker queue (G2H handler) so we must use > + * another worker to trigger a GT reset. > + */ > + queue_work(system_unbound_wq, &guc->submission_state.reset_fail_worker); > > return 0; > } ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset @ 2022-01-21 18:53 ` John Harrison 0 siblings, 0 replies; 18+ messages in thread From: John Harrison @ 2022-01-21 18:53 UTC (permalink / raw) To: Matthew Brost, intel-gfx, dri-devel On 1/20/2022 20:31, Matthew Brost wrote: > The G2H handler needs to be flushed during a GT reset but a G2H > indicating engine reset failure can trigger a GT reset. Add a worker to > trigger the GT rest when an engine reset failure is received to break > this circular dependency. > > v2: > (John Harrison) > - Store engine reset mask > - Fix typo in commit message > v3: > (John Harrison) > - Fix another typo in commit message > - s/reset_*/reset_fail_*/ > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++++ > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++++++++++++++++-- > 2 files changed, 42 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > index 9d26a86fe557a..d59bbf49d1c2b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > @@ -119,6 +119,15 @@ struct intel_guc { > * function as it might be in an atomic context (no sleeping) > */ > struct work_struct destroyed_worker; > + /** > + * @reset_fail_worker: worker to trigger a GT reset after an > + * engine reset fails > + */ > + struct work_struct reset_fail_worker; > + /** > + * @reset_fail_mask: mask of engines that failed to reset > + */ > + intel_engine_mask_t reset_fail_mask; > } submission_state; > > /** > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 3918f1be114fa..9a3f503d201aa 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc) > } > > static void destroyed_worker_func(struct work_struct *w); > +static void reset_fail_worker_func(struct work_struct *w); > > /* > * Set up the memory resources to be shared with the GuC (via the GGTT) > @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc) > INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts); > INIT_WORK(&guc->submission_state.destroyed_worker, > destroyed_worker_func); > + INIT_WORK(&guc->submission_state.reset_fail_worker, > + reset_fail_worker_func); > > guc->submission_state.guc_ids_bitmap = > bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL); > @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance) > return gt->engine_class[engine_class][instance]; > } > > +static void reset_fail_worker_func(struct work_struct *w) > +{ > + struct intel_guc *guc = container_of(w, struct intel_guc, > + submission_state.reset_fail_worker); > + struct intel_gt *gt = guc_to_gt(guc); > + intel_engine_mask_t reset_fail_mask; > + unsigned long flags; > + > + spin_lock_irqsave(&guc->submission_state.lock, flags); > + reset_fail_mask = guc->submission_state.reset_fail_mask; > + guc->submission_state.reset_fail_mask = 0; > + spin_unlock_irqrestore(&guc->submission_state.lock, flags); > + > + if (likely(reset_fail_mask)) > + intel_gt_handle_error(gt, reset_fail_mask, > + I915_ERROR_CAPTURE, > + "GuC failed to reset engine mask=0x%x\n", > + reset_fail_mask); > +} > + > int intel_guc_engine_failure_process_msg(struct intel_guc *guc, > const u32 *msg, u32 len) > { > @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, > struct intel_gt *gt = guc_to_gt(guc); > u8 guc_class, instance; > u32 reason; > + unsigned long flags; > > if (unlikely(len != 3)) { > drm_err(>->i915->drm, "Invalid length %u", len); > @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc, > drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s) because 0x%08X", > guc_class, instance, engine->name, reason); > > - intel_gt_handle_error(gt, engine->mask, > - I915_ERROR_CAPTURE, > - "GuC failed to reset %s (reason=0x%08x)\n", > - engine->name, reason); > + spin_lock_irqsave(&guc->submission_state.lock, flags); > + guc->submission_state.reset_fail_mask |= engine->mask; > + spin_unlock_irqrestore(&guc->submission_state.lock, flags); > + > + /* > + * A GT reset flushes this worker queue (G2H handler) so we must use > + * another worker to trigger a GT reset. > + */ > + queue_work(system_unbound_wq, &guc->submission_state.reset_fail_worker); > > return 0; > } ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost @ 2022-01-21 4:31 ` Matthew Brost -1 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: john.c.harrison Now that the error capture is fully decoupled from fence signalling (request retirement to free memory, which in turn depends on resets) we can safely flush the G2H handler during a GT reset. This eliminates corner cases where GuC generated G2H (e.g. engine resets) race with a GT reset. v2: (John Harrison) - Fix typo in commit message (s/is/in) Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 9a3f503d201aa..1331ff91c5b05 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); void intel_guc_submission_reset_prepare(struct intel_guc *guc) { - int i; - if (unlikely(!guc_submission_initialized(guc))) { /* Reset called during driver load? GuC not yet initialised! */ return; @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) guc_flush_submissions(guc); guc_flush_destroyed_contexts(guc); - - /* - * Handle any outstanding G2Hs before reset. Call IRQ handler directly - * each pass as interrupt have been disabled. We always scrub for - * outstanding G2H as it is possible for outstanding_submission_g2h to - * be incremented after the context state update. - */ - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { - intel_guc_to_host_event_handler(guc); -#define wait_for_reset(guc, wait_var) \ - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) - do { - wait_for_reset(guc, &guc->outstanding_submission_g2h); - } while (!list_empty(&guc->ct.requests.incoming)); - } + flush_work(&guc->ct.requests.worker); scrub_guc_desc_for_outstanding_g2h(guc); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset @ 2022-01-21 4:31 ` Matthew Brost 0 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:31 UTC (permalink / raw) To: intel-gfx, dri-devel Now that the error capture is fully decoupled from fence signalling (request retirement to free memory, which in turn depends on resets) we can safely flush the G2H handler during a GT reset. This eliminates corner cases where GuC generated G2H (e.g. engine resets) race with a GT reset. v2: (John Harrison) - Fix typo in commit message (s/is/in) Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 9a3f503d201aa..1331ff91c5b05 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); void intel_guc_submission_reset_prepare(struct intel_guc *guc) { - int i; - if (unlikely(!guc_submission_initialized(guc))) { /* Reset called during driver load? GuC not yet initialised! */ return; @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) guc_flush_submissions(guc); guc_flush_destroyed_contexts(guc); - - /* - * Handle any outstanding G2Hs before reset. Call IRQ handler directly - * each pass as interrupt have been disabled. We always scrub for - * outstanding G2H as it is possible for outstanding_submission_g2h to - * be incremented after the context state update. - */ - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { - intel_guc_to_host_event_handler(guc); -#define wait_for_reset(guc, wait_var) \ - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) - do { - wait_for_reset(guc, &guc->outstanding_submission_g2h); - } while (!list_empty(&guc->ct.requests.incoming)); - } + flush_work(&guc->ct.requests.worker); scrub_guc_desc_for_outstanding_g2h(guc); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Flush G2H handler during a GT reset 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost ` (3 preceding siblings ...) (?) @ 2022-01-21 4:59 ` Patchwork -1 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2022-01-21 4:59 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx == Series Details == Series: Flush G2H handler during a GT reset URL : https://patchwork.freedesktop.org/series/99136/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Flush G2H handler during a GT reset 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost ` (4 preceding siblings ...) (?) @ 2022-01-21 5:25 ` Patchwork -1 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2022-01-21 5:25 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5049 bytes --] == Series Details == Series: Flush G2H handler during a GT reset URL : https://patchwork.freedesktop.org/series/99136/ State : success == Summary == CI Bug Log - changes from CI_DRM_11115 -> Patchwork_22051 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/index.html Participating hosts (42 -> 38) ------------------------------ Missing (4): fi-kbl-soraka fi-bsw-cyan fi-bdw-samus fi-kbl-7500u Known issues ------------ Here are the changes found in Patchwork_22051 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][2] -> [FAIL][3] ([i915#4547]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html * igt@i915_selftest@live@gt_engines: - bat-dg1-6: [PASS][4] -> [INCOMPLETE][5] ([i915#4418]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/bat-dg1-6/igt@i915_selftest@live@gt_engines.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/bat-dg1-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][6] -> [DMESG-FAIL][7] ([i915#4528]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/fi-blb-e6850/igt@i915_selftest@live@requests.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-blb-e6850/igt@i915_selftest@live@requests.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-skl-6600u/igt@runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][9] ([i915#2426] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-bdw-5557u/igt@runner@aborted.html - bat-dg1-6: NOTRUN -> [FAIL][10] ([i915#4214] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/bat-dg1-6/igt@runner@aborted.html - fi-blb-e6850: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / [i915#4312]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-blb-e6850/igt@runner@aborted.html #### Possible fixes #### * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [INCOMPLETE][12] ([i915#3921]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-snb-2600/igt@i915_selftest@live@hangcheck.html #### Warnings #### * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][14] ([fdo#109271]) -> [FAIL][15] ([i915#3049]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4214]: https://gitlab.freedesktop.org/drm/intel/issues/4214 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897 Build changes ------------- * Linux: CI_DRM_11115 -> Patchwork_22051 CI-20190529: 20190529 CI_DRM_11115: 4e12213687264ffccb45d72fe638f94d3ca666bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22051: 41d8611617d3b97ce000ec529dcef74aaa2efe04 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 41d8611617d3 drm/i915/guc: Flush G2H handler during a GT reset e99d26d68785 drm/i915/guc: Add work queue to trigger a GT reset 054f74cfab51 drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/index.html [-- Attachment #2: Type: text/html, Size: 6129 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Flush G2H handler during a GT reset 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost ` (5 preceding siblings ...) (?) @ 2022-01-21 7:00 ` Patchwork -1 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2022-01-21 7:00 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 28766 bytes --] == Series Details == Series: Flush G2H handler during a GT reset URL : https://patchwork.freedesktop.org/series/99136/ State : success == Summary == CI Bug Log - changes from CI_DRM_11115_full -> Patchwork_22051_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in Patchwork_22051_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl8/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_ctx_persistence@engines-queued: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb5/igt@gem_ctx_persistence@engines-queued.html * igt@gem_eio@in-flight-suspend: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#180] / [i915#3614]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl3/igt@gem_eio@in-flight-suspend.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-glk4/igt@gem_exec_fair@basic-none@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk4/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: NOTRUN -> [DMESG-WARN][16] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@gem_exec_suspend@basic-s3@smem.html * igt@gem_lmem_swapping@heavy-random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl1/igt@gem_lmem_swapping@heavy-random.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@gem_userptr_blits@dmabuf-sync.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][19] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271]) +64 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@i915_pm_rpm@modeset-lpsp-stress.html * igt@i915_pm_rpm@sysfs-read: - shard-snb: NOTRUN -> [SKIP][21] ([fdo#109271]) +21 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb5/igt@i915_pm_rpm@sysfs-read.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][22] -> [INCOMPLETE][23] ([i915#3921]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-snb7/igt@i915_selftest@live@hangcheck.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb4/igt@i915_selftest@live@hangcheck.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][24] -> [INCOMPLETE][25] ([i915#4817]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl8/igt@i915_suspend@sysfs-reader.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl3/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-glk: [PASS][26] -> [DMESG-WARN][27] ([i915#118]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +3 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][31] ([i915#3689] / [i915#3886]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-tglb1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109278] / [i915#3886]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@hdmi-crc-fast: - shard-apl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +5 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl1/igt@kms_chamelium@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-mode-timings: - shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +5 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl7/igt@kms_chamelium@hdmi-mode-timings.html * igt@kms_color_chamelium@pipe-b-ctm-negative: - shard-snb: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb5/igt@kms_color_chamelium@pipe-b-ctm-negative.html * igt@kms_color_chamelium@pipe-d-ctm-0-75: - shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl6/igt@kms_color_chamelium@pipe-d-ctm-0-75.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-iclb: [PASS][38] -> [FAIL][39] ([i915#2346]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-skl: [PASS][40] -> [FAIL][41] ([i915#2346]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html * igt@kms_flip@flip-vs-suspend@b-edp1: - shard-skl: [PASS][42] -> [INCOMPLETE][43] ([i915#4839]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl4/igt@kms_flip@flip-vs-suspend@b-edp1.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl8/igt@kms_flip@flip-vs-suspend@b-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling: - shard-glk: [PASS][44] -> [FAIL][45] ([i915#4911]) +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-glk6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling: - shard-iclb: [PASS][46] -> [SKIP][47] ([i915#3701]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271]) +50 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: - shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +61 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +3 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html - shard-skl: [PASS][52] -> [FAIL][53] ([i915#1188]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533]) +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][56] ([i915#265]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-kbl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-skl: NOTRUN -> [FAIL][58] ([fdo#108145] / [i915#265]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][59] -> [FAIL][60] ([fdo#108145] / [i915#265]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_su@page_flip-p010: - shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@kms_psr2_su@page_flip-p010.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][63] -> [DMESG-WARN][64] ([i915#180] / [i915#295]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@perf@polling-parameterized: - shard-skl: NOTRUN -> [FAIL][65] ([i915#1542]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl6/igt@perf@polling-parameterized.html * igt@sysfs_clients@create: - shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@sysfs_clients@create.html * igt@sysfs_clients@fair-3: - shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2994]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@sysfs_clients@fair-3.html * igt@sysfs_clients@recycle: - shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl6/igt@sysfs_clients@recycle.html #### Possible fixes #### * igt@gem_eio@unwedge-stress: - shard-tglb: [FAIL][69] ([i915#232]) -> [PASS][70] +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-tglb3/igt@gem_eio@unwedge-stress.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-tglb6/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [SKIP][71] ([i915#4525]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [FAIL][73] ([i915#2842]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl8/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][75] ([i915#2842]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html - shard-glk: [FAIL][77] ([i915#2842]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-iclb: [FAIL][79] ([i915#2842]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb6/igt@gem_exec_fair@basic-pace@rcs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb1/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [FAIL][81] ([i915#2842]) -> [PASS][82] +4 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_softpin@allocator-evict-all-engines: - shard-glk: [FAIL][83] ([i915#4171]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-glk8/igt@gem_softpin@allocator-evict-all-engines.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk5/igt@gem_softpin@allocator-evict-all-engines.html * igt@i915_module_load@reload: - shard-skl: [DMESG-WARN][85] ([i915#1982]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl3/igt@i915_module_load@reload.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl8/igt@i915_module_load@reload.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-snb: [INCOMPLETE][87] -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-snb7/igt@i915_suspend@fence-restore-tiled2untiled.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb5/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][89] ([i915#180]) -> [PASS][90] +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +4 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][93] ([fdo#108145] / [i915#265]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][95] ([fdo#109441]) -> [PASS][96] +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@perf@polling: - shard-skl: [FAIL][97] ([i915#1542]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl9/igt@perf@polling.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl4/igt@perf@polling.html * igt@perf@polling-parameterized: - shard-glk: [FAIL][99] ([i915#1542]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-glk6/igt@perf@polling-parameterized.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk4/igt@perf@polling-parameterized.html #### Warnings #### * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [FAIL][101] ([i915#2842]) -> [FAIL][102] ([i915#2851]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb4/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][103] ([i915#2684]) -> [WARN][104] ([i915#1804] / [i915#2684]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][105] ([i915#1804] / [i915#2684]) -> [WARN][106] ([i915#2684]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-iclb: [SKIP][107] ([i915#2920]) -> [SKIP][108] ([fdo#111068] / [i915#658]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-iclb: [SKIP][109] ([fdo#111068] / [i915#658]) -> [SKIP][110] ([i915#2920]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@runner@aborted: - shard-kbl: ([FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#602]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl6/igt@runner@aborted.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl1/igt@runner@aborted.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl1/igt@runner@aborted.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-kbl1/igt@runner@aborted.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@runner@aborted.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl4/igt@runner@aborted.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@runner@aborted.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl4/igt@runner@aborted.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@runner@aborted.html - shard-skl: ([FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#2029] / [i915#3002] / [i915#4312]) -> ([FAIL][125], [FAIL][126]) ([i915#3002] / [i915#4312]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl4/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl8/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl4/igt@runner@aborted.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11115/shard-skl4/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl4/igt@runner@aborted.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-skl10/igt@runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 [i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 [i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839 [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 Build changes ------------- * Linux: CI_DRM_11115 -> Patchwork_22051 CI-20190529: 20190529 CI_DRM_11115: 4e12213687264ffccb45d72fe638f94d3ca666bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22051: 41d8611617d3b97ce000ec529dcef74aaa2efe04 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/index.html [-- Attachment #2: Type: text/html, Size: 36533 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/3] Flush G2H handler during a GT reset @ 2022-01-19 21:24 Matthew Brost 2022-01-19 21:24 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost 0 siblings, 1 reply; 18+ messages in thread From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw) To: dri-devel, intel-gfx; +Cc: john.c.harrison After a small fix to error capture code, we now can flush G2H during a GT reset which simplifies code and seals some extreme corner case races. v2: (CI) - Don't trigger GT reset from G2H handler v3: - Address John Harrison's comments Signed-off-by: Matthew Brost <matthew.brost@intel.com> Matthew Brost (3): drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL drm/i915/guc: Add work queue to trigger a GT reset drm/i915/guc: Flush G2H handler during a GT reset drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++------- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 3 files changed, 44 insertions(+), 22 deletions(-) -- 2.34.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset 2022-01-19 21:24 [PATCH 0/3] " Matthew Brost @ 2022-01-19 21:24 ` Matthew Brost 2022-01-21 1:36 ` John Harrison 0 siblings, 1 reply; 18+ messages in thread From: Matthew Brost @ 2022-01-19 21:24 UTC (permalink / raw) To: dri-devel, intel-gfx; +Cc: john.c.harrison Now that the error capture is fully decoupled from fence signalling (request retirement to free memory, which in turn depends on resets) we can safely flush the G2H handler during a GT reset. This is eliminates corner cases where GuC generated G2H (e.g. engine resets) race with a GT reset. v2: (John Harrison) - Fix typo in commit message (s/is/in) Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 514b3060b141..406dd2e3f5a9 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); void intel_guc_submission_reset_prepare(struct intel_guc *guc) { - int i; - if (unlikely(!guc_submission_initialized(guc))) { /* Reset called during driver load? GuC not yet initialised! */ return; @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) guc_flush_submissions(guc); guc_flush_destroyed_contexts(guc); - - /* - * Handle any outstanding G2Hs before reset. Call IRQ handler directly - * each pass as interrupt have been disabled. We always scrub for - * outstanding G2H as it is possible for outstanding_submission_g2h to - * be incremented after the context state update. - */ - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { - intel_guc_to_host_event_handler(guc); -#define wait_for_reset(guc, wait_var) \ - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) - do { - wait_for_reset(guc, &guc->outstanding_submission_g2h); - } while (!list_empty(&guc->ct.requests.incoming)); - } + flush_work(&guc->ct.requests.worker); scrub_guc_desc_for_outstanding_g2h(guc); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset 2022-01-19 21:24 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost @ 2022-01-21 1:36 ` John Harrison 2022-01-21 4:05 ` Matthew Brost 0 siblings, 1 reply; 18+ messages in thread From: John Harrison @ 2022-01-21 1:36 UTC (permalink / raw) To: Matthew Brost, dri-devel, intel-gfx On 1/19/2022 13:24, Matthew Brost wrote: > Now that the error capture is fully decoupled from fence signalling > (request retirement to free memory, which in turn depends on resets) we > can safely flush the G2H handler during a GT reset. This is eliminates This eliminates John. > corner cases where GuC generated G2H (e.g. engine resets) race with a GT > reset. > > v2: > (John Harrison) > - Fix typo in commit message (s/is/in) > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > --- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- > 1 file changed, 1 insertion(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 514b3060b141..406dd2e3f5a9 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); > > void intel_guc_submission_reset_prepare(struct intel_guc *guc) > { > - int i; > - > if (unlikely(!guc_submission_initialized(guc))) { > /* Reset called during driver load? GuC not yet initialised! */ > return; > @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) > > guc_flush_submissions(guc); > guc_flush_destroyed_contexts(guc); > - > - /* > - * Handle any outstanding G2Hs before reset. Call IRQ handler directly > - * each pass as interrupt have been disabled. We always scrub for > - * outstanding G2H as it is possible for outstanding_submission_g2h to > - * be incremented after the context state update. > - */ > - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { > - intel_guc_to_host_event_handler(guc); > -#define wait_for_reset(guc, wait_var) \ > - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) > - do { > - wait_for_reset(guc, &guc->outstanding_submission_g2h); > - } while (!list_empty(&guc->ct.requests.incoming)); > - } > + flush_work(&guc->ct.requests.worker); > > scrub_guc_desc_for_outstanding_g2h(guc); > } ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset 2022-01-21 1:36 ` John Harrison @ 2022-01-21 4:05 ` Matthew Brost 0 siblings, 0 replies; 18+ messages in thread From: Matthew Brost @ 2022-01-21 4:05 UTC (permalink / raw) To: John Harrison; +Cc: intel-gfx, dri-devel On Thu, Jan 20, 2022 at 05:36:22PM -0800, John Harrison wrote: > On 1/19/2022 13:24, Matthew Brost wrote: > > Now that the error capture is fully decoupled from fence signalling > > (request retirement to free memory, which in turn depends on resets) we > > can safely flush the G2H handler during a GT reset. This is eliminates > This eliminates > > John. > Yep, will fixup in the next rev. Matt > > corner cases where GuC generated G2H (e.g. engine resets) race with a GT > > reset. > > > > v2: > > (John Harrison) > > - Fix typo in commit message (s/is/in) > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > > --- > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- > > 1 file changed, 1 insertion(+), 17 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > index 514b3060b141..406dd2e3f5a9 100644 > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > > @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); > > void intel_guc_submission_reset_prepare(struct intel_guc *guc) > > { > > - int i; > > - > > if (unlikely(!guc_submission_initialized(guc))) { > > /* Reset called during driver load? GuC not yet initialised! */ > > return; > > @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) > > guc_flush_submissions(guc); > > guc_flush_destroyed_contexts(guc); > > - > > - /* > > - * Handle any outstanding G2Hs before reset. Call IRQ handler directly > > - * each pass as interrupt have been disabled. We always scrub for > > - * outstanding G2H as it is possible for outstanding_submission_g2h to > > - * be incremented after the context state update. > > - */ > > - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { > > - intel_guc_to_host_event_handler(guc); > > -#define wait_for_reset(guc, wait_var) \ > > - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) > > - do { > > - wait_for_reset(guc, &guc->outstanding_submission_g2h); > > - } while (!list_empty(&guc->ct.requests.incoming)); > > - } > > + flush_work(&guc->ct.requests.worker); > > scrub_guc_desc_for_outstanding_g2h(guc); > > } > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/3] Flush G2H handler during a GT reset @ 2022-01-18 21:43 Matthew Brost 2022-01-18 21:43 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost 0 siblings, 1 reply; 18+ messages in thread From: Matthew Brost @ 2022-01-18 21:43 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: thomas.hellstrom, john.c.harrison After a small fix to error capture code, we now can flush G2H during a GT reset which simplifies code and seals some extreme corner case races. v2: (CI) - Don't trigger GT reset from G2H handler Signed-off-by: Matthew Brost <matthew.brost@intel.com> Matthew Brost (3): drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL drm/i915/guc: Add work queue to trigger a GT reset drm/i915/guc: Flush G2H handler during a GT reset drivers/gpu/drm/i915/gt/uc/intel_guc.h | 5 +++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 41 +++++++++---------- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 3 files changed, 26 insertions(+), 22 deletions(-) -- 2.34.1 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset 2022-01-18 21:43 [PATCH 0/3] " Matthew Brost @ 2022-01-18 21:43 ` Matthew Brost 2022-01-19 1:38 ` John Harrison 0 siblings, 1 reply; 18+ messages in thread From: Matthew Brost @ 2022-01-18 21:43 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: thomas.hellstrom, john.c.harrison Now that the error capture is fully decoupled from fence signalling (request retirement to free memory, which is turn depends on resets) we can safely flush the G2H handler during a GT reset. This is eliminates corner cases where GuC generated G2H (e.g. engine resets) race with a GT reset. Signed-off-by: Matthew Brost <mattthew.brost@intel.com> --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index cdd8d691251ff..1a11e8986948b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); void intel_guc_submission_reset_prepare(struct intel_guc *guc) { - int i; - if (unlikely(!guc_submission_initialized(guc))) { /* Reset called during driver load? GuC not yet initialised! */ return; @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) guc_flush_submissions(guc); guc_flush_destroyed_contexts(guc); - - /* - * Handle any outstanding G2Hs before reset. Call IRQ handler directly - * each pass as interrupt have been disabled. We always scrub for - * outstanding G2H as it is possible for outstanding_submission_g2h to - * be incremented after the context state update. - */ - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { - intel_guc_to_host_event_handler(guc); -#define wait_for_reset(guc, wait_var) \ - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) - do { - wait_for_reset(guc, &guc->outstanding_submission_g2h); - } while (!list_empty(&guc->ct.requests.incoming)); - } + flush_work(&guc->ct.requests.worker); scrub_guc_desc_for_outstanding_g2h(guc); } -- 2.34.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset 2022-01-18 21:43 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost @ 2022-01-19 1:38 ` John Harrison 0 siblings, 0 replies; 18+ messages in thread From: John Harrison @ 2022-01-19 1:38 UTC (permalink / raw) To: Matthew Brost, intel-gfx, dri-devel; +Cc: thomas.hellstrom On 1/18/2022 13:43, Matthew Brost wrote: > Now that the error capture is fully decoupled from fence signalling > (request retirement to free memory, which is turn depends on resets) we s/is/in/ With that fixed: Reviewed-by: John Harrison <John.C.Harrison@Intel.com> John. > can safely flush the G2H handler during a GT reset. This is eliminates > corner cases where GuC generated G2H (e.g. engine resets) race with a GT > reset. > > Signed-off-by: Matthew Brost <mattthew.brost@intel.com> > --- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 18 +----------------- > 1 file changed, 1 insertion(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index cdd8d691251ff..1a11e8986948b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc *guc); > > void intel_guc_submission_reset_prepare(struct intel_guc *guc) > { > - int i; > - > if (unlikely(!guc_submission_initialized(guc))) { > /* Reset called during driver load? GuC not yet initialised! */ > return; > @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc) > > guc_flush_submissions(guc); > guc_flush_destroyed_contexts(guc); > - > - /* > - * Handle any outstanding G2Hs before reset. Call IRQ handler directly > - * each pass as interrupt have been disabled. We always scrub for > - * outstanding G2H as it is possible for outstanding_submission_g2h to > - * be incremented after the context state update. > - */ > - for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); ++i) { > - intel_guc_to_host_event_handler(guc); > -#define wait_for_reset(guc, wait_var) \ > - intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20)) > - do { > - wait_for_reset(guc, &guc->outstanding_submission_g2h); > - } while (!list_empty(&guc->ct.requests.incoming)); > - } > + flush_work(&guc->ct.requests.worker); > > scrub_guc_desc_for_outstanding_g2h(guc); > } ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-01-21 18:54 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-21 4:31 [PATCH 0/3] Flush G2H handler during a GT reset Matthew Brost 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost 2022-01-21 4:31 ` [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL Matthew Brost 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost 2022-01-21 4:31 ` [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset Matthew Brost 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost 2022-01-21 18:53 ` John Harrison 2022-01-21 18:53 ` [Intel-gfx] " John Harrison 2022-01-21 4:31 ` [PATCH 3/3] drm/i915/guc: Flush G2H handler during " Matthew Brost 2022-01-21 4:31 ` [Intel-gfx] " Matthew Brost 2022-01-21 4:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork 2022-01-21 5:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-01-21 7:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2022-01-19 21:24 [PATCH 0/3] " Matthew Brost 2022-01-19 21:24 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost 2022-01-21 1:36 ` John Harrison 2022-01-21 4:05 ` Matthew Brost 2022-01-18 21:43 [PATCH 0/3] " Matthew Brost 2022-01-18 21:43 ` [PATCH 3/3] drm/i915/guc: " Matthew Brost 2022-01-19 1:38 ` John Harrison
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