From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, Marcel Apfelbaum <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, Igor Mammedov <imammedo@redhat.com> Cc: linux-cxl@vger.kernel.org, "Ben Widawsky" <ben.widawsky@intel.com>, "Alex Bennée" <alex.bennee@linaro.org>, "Peter Maydell" <peter.maydell@linaro.org>, linuxarm@huawei.com, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Saransh Gupta1" <saransh@ibm.com>, "Shreyas Shah" <shreyas.shah@elastics.cloud>, "Chris Browy" <cbrowy@avery-design.com>, "Samarth Saxena" <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: [PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter encoding/decoding Date: Mon, 24 Jan 2022 17:16:51 +0000 [thread overview] Message-ID: <20220124171705.10432-29-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20220124171705.10432-1-Jonathan.Cameron@huawei.com> From: Jonathan Cameron <jonathan.cameron@huawei.com> Both registers and the CFMWS entries in CDAT use simple encodings for the number of interleave ways and the interleave granularity. Introduce simple conversion functions to/from the unencoded number / size. So far the iw decode has not been needed so is it not implemented. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-component-utils.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_component.h | 8 ++++++++ 2 files changed, 42 insertions(+) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 5007b29ebb..be2c5599d6 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qapi/error.h" #include "hw/pci/pci.h" #include "hw/cxl/cxl.h" @@ -210,3 +211,36 @@ void cxl_component_create_dvsec(CXLComponentState *cxl, uint16_t length, range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); cxl->dvsec_offset += length; } + +uint8_t cxl_interleave_ways_enc(int iw, Error **errp) +{ + switch (iw) { + case 1: return 0x0; + case 2: return 0x1; + case 4: return 0x2; + case 8: return 0x3; + case 16: return 0x4; + case 3: return 0x8; + case 6: return 0x9; + case 12: return 0xa; + default: + error_setg(errp, "Interleave ways: %d not supported", iw); + return 0; + } +} + +uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp) +{ + switch (gran) { + case 256: return 0; + case 512: return 1; + case 1024: return 2; + case 2048: return 3; + case 4096: return 4; + case 8192: return 5; + case 16384: return 6; + default: + error_setg(errp, "Interleave granularity: %lu invalid", gran); + return 0; + } +} diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 30e576351d..d30c3f4716 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -193,4 +193,12 @@ void cxl_component_register_init_common(uint32_t *reg_state, void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, uint16_t length, uint16_t type, uint8_t rev, uint8_t *body); +uint8_t cxl_interleave_ways_enc(int iw, Error **errp); +uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); + +static inline hwaddr cxl_decode_ig(int ig) +{ + return 1 << (ig + 8); +} + #endif -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, Marcel Apfelbaum <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, Igor Mammedov <imammedo@redhat.com> Cc: linux-cxl@vger.kernel.org, "Ben Widawsky" <ben.widawsky@intel.com>, "Alex Bennée" <alex.bennee@linaro.org>, "Peter Maydell" <peter.maydell@linaro.org>, linuxarm@huawei.com, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Saransh Gupta1" <saransh@ibm.com>, "Shreyas Shah" <shreyas.shah@elastics.cloud>, "Chris Browy" <cbrowy@avery-design.com>, "Samarth Saxena" <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: [PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter encoding/decoding Date: Mon, 24 Jan 2022 17:16:51 +0000 [thread overview] Message-ID: <20220124171705.10432-29-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20220124171705.10432-1-Jonathan.Cameron@huawei.com> From: Jonathan Cameron <jonathan.cameron@huawei.com> Both registers and the CFMWS entries in CDAT use simple encodings for the number of interleave ways and the interleave granularity. Introduce simple conversion functions to/from the unencoded number / size. So far the iw decode has not been needed so is it not implemented. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-component-utils.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_component.h | 8 ++++++++ 2 files changed, 42 insertions(+) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 5007b29ebb..be2c5599d6 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qapi/error.h" #include "hw/pci/pci.h" #include "hw/cxl/cxl.h" @@ -210,3 +211,36 @@ void cxl_component_create_dvsec(CXLComponentState *cxl, uint16_t length, range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length); cxl->dvsec_offset += length; } + +uint8_t cxl_interleave_ways_enc(int iw, Error **errp) +{ + switch (iw) { + case 1: return 0x0; + case 2: return 0x1; + case 4: return 0x2; + case 8: return 0x3; + case 16: return 0x4; + case 3: return 0x8; + case 6: return 0x9; + case 12: return 0xa; + default: + error_setg(errp, "Interleave ways: %d not supported", iw); + return 0; + } +} + +uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp) +{ + switch (gran) { + case 256: return 0; + case 512: return 1; + case 1024: return 2; + case 2048: return 3; + case 4096: return 4; + case 8192: return 5; + case 16384: return 6; + default: + error_setg(errp, "Interleave granularity: %lu invalid", gran); + return 0; + } +} diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 30e576351d..d30c3f4716 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -193,4 +193,12 @@ void cxl_component_register_init_common(uint32_t *reg_state, void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, uint16_t length, uint16_t type, uint8_t rev, uint8_t *body); +uint8_t cxl_interleave_ways_enc(int iw, Error **errp); +uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); + +static inline hwaddr cxl_decode_ig(int ig) +{ + return 1 << (ig + 8); +} + #endif -- 2.32.0
next prev parent reply other threads:[~2022-01-24 17:31 UTC|newest] Thread overview: 182+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-24 17:16 [PATCH v4 00/42] CXl 2.0 emulation Support Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 01/42] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-25 13:53 ` Alex Bennée 2022-01-25 13:53 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 02/42] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-26 12:32 ` Alex Bennée 2022-01-26 12:32 ` Alex Bennée 2022-01-28 14:22 ` Jonathan Cameron 2022-01-28 14:22 ` Jonathan Cameron via 2022-01-28 14:46 ` Jonathan Cameron 2022-01-28 14:46 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 03/42] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-26 18:06 ` Alex Bennée 2022-01-26 18:06 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 04/42] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-26 18:07 ` Alex Bennée 2022-01-26 18:07 ` Alex Bennée 2022-01-28 15:02 ` Jonathan Cameron 2022-01-28 15:02 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 05/42] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-26 18:17 ` Alex Bennée 2022-01-26 18:17 ` Alex Bennée 2022-01-28 15:16 ` Jonathan Cameron 2022-01-28 15:16 ` Jonathan Cameron via 2022-01-28 16:37 ` Alex Bennée 2022-01-28 16:37 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 06/42] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-26 18:22 ` Alex Bennée 2022-01-26 18:22 ` Alex Bennée 2022-01-28 15:52 ` Jonathan Cameron 2022-01-28 15:52 ` Jonathan Cameron via 2022-01-27 11:31 ` Alex Bennée 2022-01-27 11:31 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 07/42] hw/cxl/device: Add memory device utilities Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 11:28 ` Alex Bennée 2022-01-27 11:28 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 08/42] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 11:43 ` Alex Bennée 2022-01-27 11:43 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 09/42] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 11:50 ` Alex Bennée 2022-01-27 11:50 ` Alex Bennée 2022-01-28 17:52 ` Jonathan Cameron 2022-01-28 17:52 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 10/42] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 11:55 ` Alex Bennée 2022-01-27 11:55 ` Alex Bennée 2022-01-28 16:47 ` Jonathan Cameron 2022-01-28 16:47 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 11/42] hw/pxb: Use a type for realizing expanders Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 12:01 ` Alex Bennée 2022-01-27 12:01 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 12:05 ` Alex Bennée 2022-01-27 12:05 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 13/42] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 13:59 ` Alex Bennée 2022-01-27 13:59 ` Alex Bennée 2022-01-28 18:20 ` Jonathan Cameron 2022-01-28 18:20 ` Jonathan Cameron via 2022-01-28 18:48 ` Jonathan Cameron 2022-01-28 18:48 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 14:06 ` Alex Bennée 2022-01-27 14:06 ` Alex Bennée 2022-01-28 18:26 ` Jonathan Cameron 2022-01-28 18:26 ` Jonathan Cameron via 2022-01-28 18:34 ` Alex Bennée 2022-01-28 18:34 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 15/42] acpi/pci: Consolidate host bridge setup Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 14:10 ` Alex Bennée 2022-01-27 14:10 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 16/42] tests/acpi: Add update DSDT.viot Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 14:12 ` Alex Bennée 2022-01-27 14:12 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-27 14:18 ` Alex Bennée 2022-01-27 14:18 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 18/42] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 19/42] hw/cxl/rp: Add a root port Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 20/42] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 21/42] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 22/42] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 23/42] tests/acpi: allow CEDT table addition Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-02-09 18:18 ` Jonathan Cameron 2022-02-09 18:18 ` Jonathan Cameron via 2022-02-09 19:09 ` Michael S. Tsirkin 2022-02-09 19:09 ` Michael S. Tsirkin 2022-01-24 17:16 ` [PATCH v4 24/42] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 25/42] hw/cxl/device: Add some trivial commands Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 26/42] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 27/42] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-28 17:29 ` Jonathan Cameron 2022-01-28 17:29 ` Jonathan Cameron via 2022-01-24 17:16 ` Jonathan Cameron [this message] 2022-01-24 17:16 ` [PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 29/42] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-25 17:02 ` Alex Bennée 2022-01-25 17:02 ` Alex Bennée 2022-01-25 17:51 ` Jonathan Cameron 2022-01-25 17:51 ` Jonathan Cameron via 2022-01-25 22:53 ` Alex Bennée 2022-01-25 22:53 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 30/42] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 31/42] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-25 17:15 ` Alex Bennée 2022-01-25 17:15 ` Alex Bennée 2022-01-25 18:13 ` Jonathan Cameron 2022-01-25 18:13 ` Jonathan Cameron via 2022-01-25 18:16 ` Michael S. Tsirkin 2022-01-25 18:16 ` Michael S. Tsirkin 2022-01-26 12:24 ` Alex Bennée 2022-01-26 12:24 ` Alex Bennée 2022-01-24 17:16 ` [PATCH v4 32/42] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 33/42] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 34/42] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 35/42] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:16 ` [PATCH v4 36/42] arm/virt: Allow virt/CEDT creation Jonathan Cameron 2022-01-24 17:16 ` Jonathan Cameron via 2022-01-24 17:17 ` [PATCH v4 37/42] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron 2022-01-24 17:17 ` Jonathan Cameron via 2022-01-24 17:17 ` [PATCH v4 38/42] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron 2022-01-24 17:17 ` Jonathan Cameron via 2022-01-24 17:17 ` [PATCH v4 39/42] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron 2022-01-24 17:17 ` Jonathan Cameron via 2022-01-24 17:17 ` [PATCH v4 40/42] i386/pc: Enable CXL fixed memory windows Jonathan Cameron 2022-01-24 17:17 ` Jonathan Cameron via 2022-01-24 17:17 ` [PATCH v4 41/42] qtest/acpi: Add reference CEDT tables Jonathan Cameron 2022-01-24 17:17 ` Jonathan Cameron via 2022-01-24 17:17 ` [PATCH v4 42/42] qtest/cxl: Add very basic sanity tests Jonathan Cameron 2022-01-24 17:17 ` Jonathan Cameron via 2022-01-24 18:11 ` [PATCH v4 00/42] CXl 2.0 emulation Support Jonathan Cameron 2022-01-24 18:11 ` Jonathan Cameron via 2022-01-25 13:55 ` Alex Bennée 2022-01-25 13:55 ` Alex Bennée 2022-01-25 15:49 ` Jonathan Cameron 2022-01-25 15:49 ` Jonathan Cameron via 2022-01-25 19:18 ` Ben Widawsky 2022-01-25 19:18 ` Ben Widawsky 2022-01-25 23:55 ` Ben Widawsky 2022-01-25 23:55 ` Ben Widawsky 2022-01-26 9:46 ` Jonathan Cameron 2022-01-26 9:46 ` Jonathan Cameron via 2022-01-27 14:22 ` Alex Bennée 2022-01-27 14:22 ` Alex Bennée 2022-01-27 16:42 ` Jonathan Cameron 2022-01-27 16:42 ` Jonathan Cameron via
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