From: Bjorn Helgaas <helgaas@kernel.org>
To: qizhong cheng <qizhong.cheng@mediatek.com>
Cc: "Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, chuanjia.liu@mediatek.com
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Date: Tue, 25 Jan 2022 10:57:48 -0600 [thread overview]
Message-ID: <20220125165748.GA1458116@bhelgaas> (raw)
In-Reply-To: <20220123033306.29799-1-qizhong.cheng@mediatek.com>
All patches change *something*. Can you update the subject line so it
says something specific about the change?
Maybe something like "Clear MSI status before dispatching handler"?
On Sun, Jan 23, 2022 at 11:33:06AM +0800, qizhong cheng wrote:
> As an edge-triggered interrupts, its interrupt status should be cleared
> before dispatch to the handler of device.
I'm not an IRQ expert, but the reasoning that "we should clear the MSI
interrupt status before dispatching the handler because MSI is an
edge-triggered interrupt" doesn't seem completely convincing because
your code will now look like this:
/* Clear the INTx */
writel(1 << bit, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->irq_domain, bit - INTX_SHIFT);
...
/* Clear MSI interrupt status */
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->inner_domain, bit);
You clear interrupt status before dispatching the handler for *both*
level-triggered INTx interrupts and edge-triggered MSI interrupts.
So it doesn't seem that simply being edge-triggered is the critical
factor here.
> Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
> ---
> drivers/pci/controller/pcie-mediatek.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 2f3f974977a3..705ea33758b1 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -624,12 +624,12 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
> if (status & MSI_STATUS){
> unsigned long imsi_status;
>
> + /* Clear MSI interrupt status */
> + writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
> for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
> generic_handle_domain_irq(port->inner_domain, bit);
> }
> - /* Clear MSI interrupt status */
> - writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> }
> }
>
> --
> 2.25.1
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: qizhong cheng <qizhong.cheng@mediatek.com>
Cc: "Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, chuanjia.liu@mediatek.com
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Date: Tue, 25 Jan 2022 10:57:48 -0600 [thread overview]
Message-ID: <20220125165748.GA1458116@bhelgaas> (raw)
In-Reply-To: <20220123033306.29799-1-qizhong.cheng@mediatek.com>
All patches change *something*. Can you update the subject line so it
says something specific about the change?
Maybe something like "Clear MSI status before dispatching handler"?
On Sun, Jan 23, 2022 at 11:33:06AM +0800, qizhong cheng wrote:
> As an edge-triggered interrupts, its interrupt status should be cleared
> before dispatch to the handler of device.
I'm not an IRQ expert, but the reasoning that "we should clear the MSI
interrupt status before dispatching the handler because MSI is an
edge-triggered interrupt" doesn't seem completely convincing because
your code will now look like this:
/* Clear the INTx */
writel(1 << bit, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->irq_domain, bit - INTX_SHIFT);
...
/* Clear MSI interrupt status */
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->inner_domain, bit);
You clear interrupt status before dispatching the handler for *both*
level-triggered INTx interrupts and edge-triggered MSI interrupts.
So it doesn't seem that simply being edge-triggered is the critical
factor here.
> Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
> ---
> drivers/pci/controller/pcie-mediatek.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 2f3f974977a3..705ea33758b1 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -624,12 +624,12 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
> if (status & MSI_STATUS){
> unsigned long imsi_status;
>
> + /* Clear MSI interrupt status */
> + writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
> for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
> generic_handle_domain_irq(port->inner_domain, bit);
> }
> - /* Clear MSI interrupt status */
> - writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> }
> }
>
> --
> 2.25.1
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: qizhong cheng <qizhong.cheng@mediatek.com>
Cc: "Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, chuanjia.liu@mediatek.com
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Date: Tue, 25 Jan 2022 10:57:48 -0600 [thread overview]
Message-ID: <20220125165748.GA1458116@bhelgaas> (raw)
In-Reply-To: <20220123033306.29799-1-qizhong.cheng@mediatek.com>
All patches change *something*. Can you update the subject line so it
says something specific about the change?
Maybe something like "Clear MSI status before dispatching handler"?
On Sun, Jan 23, 2022 at 11:33:06AM +0800, qizhong cheng wrote:
> As an edge-triggered interrupts, its interrupt status should be cleared
> before dispatch to the handler of device.
I'm not an IRQ expert, but the reasoning that "we should clear the MSI
interrupt status before dispatching the handler because MSI is an
edge-triggered interrupt" doesn't seem completely convincing because
your code will now look like this:
/* Clear the INTx */
writel(1 << bit, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->irq_domain, bit - INTX_SHIFT);
...
/* Clear MSI interrupt status */
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->inner_domain, bit);
You clear interrupt status before dispatching the handler for *both*
level-triggered INTx interrupts and edge-triggered MSI interrupts.
So it doesn't seem that simply being edge-triggered is the critical
factor here.
> Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
> ---
> drivers/pci/controller/pcie-mediatek.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index 2f3f974977a3..705ea33758b1 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -624,12 +624,12 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc)
> if (status & MSI_STATUS){
> unsigned long imsi_status;
>
> + /* Clear MSI interrupt status */
> + writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
> for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
> generic_handle_domain_irq(port->inner_domain, bit);
> }
> - /* Clear MSI interrupt status */
> - writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
> }
> }
>
> --
> 2.25.1
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2022-01-25 16:58 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-23 3:33 [PATCH] PCI: mediatek: Change MSI interrupt processing sequence qizhong cheng
2022-01-23 3:33 ` qizhong cheng
2022-01-23 3:33 ` qizhong cheng
2022-01-24 3:12 ` Chen-Yu Tsai
2022-01-24 3:12 ` Chen-Yu Tsai
2022-01-24 3:12 ` Chen-Yu Tsai
2022-01-24 6:27 ` qizhong.cheng
2022-01-24 6:27 ` qizhong.cheng
2022-01-24 6:55 ` Chen-Yu Tsai
2022-01-24 6:55 ` Chen-Yu Tsai
2022-01-24 6:55 ` Chen-Yu Tsai
2022-01-24 8:34 ` qizhong.cheng
2022-01-24 8:34 ` qizhong.cheng
2022-01-25 16:57 ` Bjorn Helgaas [this message]
2022-01-25 16:57 ` Bjorn Helgaas
2022-01-25 16:57 ` Bjorn Helgaas
2022-01-25 17:21 ` Marc Zyngier
2022-01-25 17:21 ` Marc Zyngier
2022-01-25 17:21 ` Marc Zyngier
2022-01-26 3:37 ` qizhong.cheng
2022-01-26 3:37 ` qizhong.cheng
2022-01-27 21:21 ` Bjorn Helgaas
2022-01-27 21:21 ` Bjorn Helgaas
2022-01-27 21:21 ` Bjorn Helgaas
2022-01-28 7:58 ` Jianjun Wang
2022-01-28 7:58 ` Jianjun Wang
2022-02-08 7:08 ` qizhong.cheng
2022-02-08 7:08 ` qizhong.cheng
2022-01-28 8:57 ` Marc Zyngier
2022-01-28 8:57 ` Marc Zyngier
2022-01-28 8:57 ` Marc Zyngier
2022-01-28 13:12 ` Bjorn Helgaas
2022-01-28 13:12 ` Bjorn Helgaas
2022-01-28 13:12 ` Bjorn Helgaas
2022-01-28 15:09 ` Marc Zyngier
2022-01-28 15:09 ` Marc Zyngier
2022-01-28 15:09 ` Marc Zyngier
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