From: Marc Zyngier <maz@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "qizhong.cheng" <qizhong.cheng@mediatek.com>,
"Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, chuanjia.liu@mediatek.com,
"Srikanth Thokala" <srikanth.thokala@intel.com>,
"Pratyush Anand" <pratyush.anand@gmail.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Pali Rohár" <pali@kernel.org>
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Date: Fri, 28 Jan 2022 15:09:49 +0000 [thread overview]
Message-ID: <87o83v6gn6.wl-maz@kernel.org> (raw)
In-Reply-To: <20220128131250.GA200007@bhelgaas>
On Fri, 28 Jan 2022 13:12:50 +0000,
Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Jan 28, 2022 at 08:57:16AM +0000, Marc Zyngier wrote:
> > On Thu, 27 Jan 2022 21:21:00 +0000,
> > Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> Thanks a lot for taking a look at these, Marc! Is there anything we
> can do to make all these drivers/pci/controller/* drivers more
> consistent and easier to review? I found it very difficult to look
> across all of them and find similar design patterns.
It looks to me that a number of them are just wrapping the same
underlying IP block, most likely the DW controller (this looks to be
the case for at least the first two).
They probably all use different register and bit offsets, but it
should be possible to write a library abstracting all these details
and have a common handling for most of them. This would certainly go a
long way in making things more solid.
M.
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "qizhong.cheng" <qizhong.cheng@mediatek.com>,
"Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, chuanjia.liu@mediatek.com,
"Srikanth Thokala" <srikanth.thokala@intel.com>,
"Pratyush Anand" <pratyush.anand@gmail.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Pali Rohár" <pali@kernel.org>
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Date: Fri, 28 Jan 2022 15:09:49 +0000 [thread overview]
Message-ID: <87o83v6gn6.wl-maz@kernel.org> (raw)
In-Reply-To: <20220128131250.GA200007@bhelgaas>
On Fri, 28 Jan 2022 13:12:50 +0000,
Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Jan 28, 2022 at 08:57:16AM +0000, Marc Zyngier wrote:
> > On Thu, 27 Jan 2022 21:21:00 +0000,
> > Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> Thanks a lot for taking a look at these, Marc! Is there anything we
> can do to make all these drivers/pci/controller/* drivers more
> consistent and easier to review? I found it very difficult to look
> across all of them and find similar design patterns.
It looks to me that a number of them are just wrapping the same
underlying IP block, most likely the DW controller (this looks to be
the case for at least the first two).
They probably all use different register and bit offsets, but it
should be possible to write a library abstracting all these details
and have a common handling for most of them. This would certainly go a
long way in making things more solid.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "qizhong.cheng" <qizhong.cheng@mediatek.com>,
"Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, chuanjia.liu@mediatek.com,
"Srikanth Thokala" <srikanth.thokala@intel.com>,
"Pratyush Anand" <pratyush.anand@gmail.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Pali Rohár" <pali@kernel.org>
Subject: Re: [PATCH] PCI: mediatek: Change MSI interrupt processing sequence
Date: Fri, 28 Jan 2022 15:09:49 +0000 [thread overview]
Message-ID: <87o83v6gn6.wl-maz@kernel.org> (raw)
In-Reply-To: <20220128131250.GA200007@bhelgaas>
On Fri, 28 Jan 2022 13:12:50 +0000,
Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Jan 28, 2022 at 08:57:16AM +0000, Marc Zyngier wrote:
> > On Thu, 27 Jan 2022 21:21:00 +0000,
> > Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> Thanks a lot for taking a look at these, Marc! Is there anything we
> can do to make all these drivers/pci/controller/* drivers more
> consistent and easier to review? I found it very difficult to look
> across all of them and find similar design patterns.
It looks to me that a number of them are just wrapping the same
underlying IP block, most likely the DW controller (this looks to be
the case for at least the first two).
They probably all use different register and bit offsets, but it
should be possible to write a library abstracting all these details
and have a common handling for most of them. This would certainly go a
long way in making things more solid.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-01-28 15:09 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-23 3:33 [PATCH] PCI: mediatek: Change MSI interrupt processing sequence qizhong cheng
2022-01-23 3:33 ` qizhong cheng
2022-01-23 3:33 ` qizhong cheng
2022-01-24 3:12 ` Chen-Yu Tsai
2022-01-24 3:12 ` Chen-Yu Tsai
2022-01-24 3:12 ` Chen-Yu Tsai
2022-01-24 6:27 ` qizhong.cheng
2022-01-24 6:27 ` qizhong.cheng
2022-01-24 6:55 ` Chen-Yu Tsai
2022-01-24 6:55 ` Chen-Yu Tsai
2022-01-24 6:55 ` Chen-Yu Tsai
2022-01-24 8:34 ` qizhong.cheng
2022-01-24 8:34 ` qizhong.cheng
2022-01-25 16:57 ` Bjorn Helgaas
2022-01-25 16:57 ` Bjorn Helgaas
2022-01-25 16:57 ` Bjorn Helgaas
2022-01-25 17:21 ` Marc Zyngier
2022-01-25 17:21 ` Marc Zyngier
2022-01-25 17:21 ` Marc Zyngier
2022-01-26 3:37 ` qizhong.cheng
2022-01-26 3:37 ` qizhong.cheng
2022-01-27 21:21 ` Bjorn Helgaas
2022-01-27 21:21 ` Bjorn Helgaas
2022-01-27 21:21 ` Bjorn Helgaas
2022-01-28 7:58 ` Jianjun Wang
2022-01-28 7:58 ` Jianjun Wang
2022-02-08 7:08 ` qizhong.cheng
2022-02-08 7:08 ` qizhong.cheng
2022-01-28 8:57 ` Marc Zyngier
2022-01-28 8:57 ` Marc Zyngier
2022-01-28 8:57 ` Marc Zyngier
2022-01-28 13:12 ` Bjorn Helgaas
2022-01-28 13:12 ` Bjorn Helgaas
2022-01-28 13:12 ` Bjorn Helgaas
2022-01-28 15:09 ` Marc Zyngier [this message]
2022-01-28 15:09 ` Marc Zyngier
2022-01-28 15:09 ` Marc Zyngier
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