From: Lucas De Marchi <lucas.demarchi@intel.com> To: intel-gfx@lists.freedesktop.org Cc: "Matthew Brost" <matthew.brost@intel.com>, "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, dri-devel@lists.freedesktop.org, "Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>, "John Harrison" <John.C.Harrison@Intel.com> Subject: [PATCH 11/19] drm/i915/guc: Convert golden context prep to dma_buf_map Date: Wed, 26 Jan 2022 12:36:54 -0800 [thread overview] Message-ID: <20220126203702.1784589-12-lucas.demarchi@intel.com> (raw) In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> Use the saved ads_map to prepare the golden context. One difference from the init context is that this function can be called before there is a gem object (and thus the guc->ads_map) to calculare the size of the golden context that should be allocated for that object. So in this case the function needs to be prepared for not having the system_info with enabled engines filled out. To accomplish that an info_map is prepared on the side to point either to the gem object or the local variable on the stack. This allows making fill_engine_enable_masks() operate always with a dma_buf_map argument. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 52 +++++++++++++--------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 15990c229b54..dd9ec47eed16 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -67,6 +67,12 @@ struct __guc_ads_blob { dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\ field_, val_) +#define info_map_write(map_, field_, val_) \ + dma_buf_map_write_field(map_, struct guc_gt_system_info, field_, val_) + +#define info_map_read(map_, field_) \ + dma_buf_map_read_field(map_, struct guc_gt_system_info, field_) + static u32 guc_ads_regset_size(struct intel_guc *guc) { GEM_BUG_ON(!guc->ads_regset_size); @@ -378,24 +384,24 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc, } static void fill_engine_enable_masks(struct intel_gt *gt, - struct guc_gt_system_info *info) + struct dma_buf_map *info_map) { - info->engine_enabled_masks[GUC_RENDER_CLASS] = 1; - info->engine_enabled_masks[GUC_BLITTER_CLASS] = 1; - info->engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt); - info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt); + info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); + info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt)); } #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32)) #define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE) -static int guc_prep_golden_context(struct intel_guc *guc, - struct __guc_ads_blob *blob) +static int guc_prep_golden_context(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); u32 addr_ggtt, offset; u32 total_size = 0, alloc_size, real_size; u8 engine_class, guc_class; - struct guc_gt_system_info *info, local_info; + struct guc_gt_system_info local_info; + struct dma_buf_map info_map; /* * Reserve the memory for the golden contexts and point GuC at it but @@ -409,14 +415,15 @@ static int guc_prep_golden_context(struct intel_guc *guc, * GuC will also validate that the LRC base + size fall within the * allowed GGTT range. */ - if (blob) { + if (!dma_buf_map_is_null(&guc->ads_map)) { offset = guc_ads_golden_ctxt_offset(guc); addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; - info = &blob->system_info; + info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, + offsetof(struct __guc_ads_blob, system_info)); } else { memset(&local_info, 0, sizeof(local_info)); - info = &local_info; - fill_engine_enable_masks(gt, info); + dma_buf_map_set_vaddr(&info_map, &local_info); + fill_engine_enable_masks(gt, &info_map); } for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { @@ -425,14 +432,14 @@ static int guc_prep_golden_context(struct intel_guc *guc, guc_class = engine_class_to_guc_class(engine_class); - if (!info->engine_enabled_masks[guc_class]) + if (!info_map_read(&info_map, engine_enabled_masks[guc_class])) continue; real_size = intel_engine_context_size(gt, engine_class); alloc_size = PAGE_ALIGN(real_size); total_size += alloc_size; - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) continue; /* @@ -446,12 +453,15 @@ static int guc_prep_golden_context(struct intel_guc *guc, * what comes before it in the context image (which is identical * on all engines). */ - blob->ads.eng_state_size[guc_class] = real_size - LRC_SKIP_SIZE; - blob->ads.golden_context_lrca[guc_class] = addr_ggtt; + ads_blob_write(guc, ads.eng_state_size[guc_class], + real_size - LRC_SKIP_SIZE); + ads_blob_write(guc, ads.golden_context_lrca[guc_class], + addr_ggtt); + addr_ggtt += alloc_size; } - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) return total_size; GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); @@ -559,13 +569,15 @@ static void __guc_ads_init(struct intel_guc *guc) struct intel_gt *gt = guc_to_gt(guc); struct drm_i915_private *i915 = gt->i915; struct __guc_ads_blob *blob = guc->ads_blob; + struct dma_buf_map info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, + offsetof(struct __guc_ads_blob, system_info)); u32 base; /* GuC scheduling policies */ guc_policies_init(guc); /* System info */ - fill_engine_enable_masks(gt, &blob->system_info); + fill_engine_enable_masks(gt, &info_map); blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] = hweight8(gt->info.sseu.slice_mask); @@ -581,7 +593,7 @@ static void __guc_ads_init(struct intel_guc *guc) } /* Golden contexts for re-initialising after a watchdog reset */ - guc_prep_golden_context(guc, blob); + guc_prep_golden_context(guc); guc_mapping_table_init(guc_to_gt(guc), &blob->system_info); @@ -624,7 +636,7 @@ int intel_guc_ads_create(struct intel_guc *guc) guc->ads_regset_size = ret; /* Likewise the golden contexts: */ - ret = guc_prep_golden_context(guc, NULL); + ret = guc_prep_golden_context(guc); if (ret < 0) return ret; guc->ads_golden_ctxt_size = ret; -- 2.35.0
WARNING: multiple messages have this Message-ID (diff)
From: Lucas De Marchi <lucas.demarchi@intel.com> To: intel-gfx@lists.freedesktop.org Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 11/19] drm/i915/guc: Convert golden context prep to dma_buf_map Date: Wed, 26 Jan 2022 12:36:54 -0800 [thread overview] Message-ID: <20220126203702.1784589-12-lucas.demarchi@intel.com> (raw) In-Reply-To: <20220126203702.1784589-1-lucas.demarchi@intel.com> Use the saved ads_map to prepare the golden context. One difference from the init context is that this function can be called before there is a gem object (and thus the guc->ads_map) to calculare the size of the golden context that should be allocated for that object. So in this case the function needs to be prepared for not having the system_info with enabled engines filled out. To accomplish that an info_map is prepared on the side to point either to the gem object or the local variable on the stack. This allows making fill_engine_enable_masks() operate always with a dma_buf_map argument. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 52 +++++++++++++--------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 15990c229b54..dd9ec47eed16 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -67,6 +67,12 @@ struct __guc_ads_blob { dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\ field_, val_) +#define info_map_write(map_, field_, val_) \ + dma_buf_map_write_field(map_, struct guc_gt_system_info, field_, val_) + +#define info_map_read(map_, field_) \ + dma_buf_map_read_field(map_, struct guc_gt_system_info, field_) + static u32 guc_ads_regset_size(struct intel_guc *guc) { GEM_BUG_ON(!guc->ads_regset_size); @@ -378,24 +384,24 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc, } static void fill_engine_enable_masks(struct intel_gt *gt, - struct guc_gt_system_info *info) + struct dma_buf_map *info_map) { - info->engine_enabled_masks[GUC_RENDER_CLASS] = 1; - info->engine_enabled_masks[GUC_BLITTER_CLASS] = 1; - info->engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt); - info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt); + info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); + info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt)); } #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32)) #define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE) -static int guc_prep_golden_context(struct intel_guc *guc, - struct __guc_ads_blob *blob) +static int guc_prep_golden_context(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); u32 addr_ggtt, offset; u32 total_size = 0, alloc_size, real_size; u8 engine_class, guc_class; - struct guc_gt_system_info *info, local_info; + struct guc_gt_system_info local_info; + struct dma_buf_map info_map; /* * Reserve the memory for the golden contexts and point GuC at it but @@ -409,14 +415,15 @@ static int guc_prep_golden_context(struct intel_guc *guc, * GuC will also validate that the LRC base + size fall within the * allowed GGTT range. */ - if (blob) { + if (!dma_buf_map_is_null(&guc->ads_map)) { offset = guc_ads_golden_ctxt_offset(guc); addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; - info = &blob->system_info; + info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, + offsetof(struct __guc_ads_blob, system_info)); } else { memset(&local_info, 0, sizeof(local_info)); - info = &local_info; - fill_engine_enable_masks(gt, info); + dma_buf_map_set_vaddr(&info_map, &local_info); + fill_engine_enable_masks(gt, &info_map); } for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { @@ -425,14 +432,14 @@ static int guc_prep_golden_context(struct intel_guc *guc, guc_class = engine_class_to_guc_class(engine_class); - if (!info->engine_enabled_masks[guc_class]) + if (!info_map_read(&info_map, engine_enabled_masks[guc_class])) continue; real_size = intel_engine_context_size(gt, engine_class); alloc_size = PAGE_ALIGN(real_size); total_size += alloc_size; - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) continue; /* @@ -446,12 +453,15 @@ static int guc_prep_golden_context(struct intel_guc *guc, * what comes before it in the context image (which is identical * on all engines). */ - blob->ads.eng_state_size[guc_class] = real_size - LRC_SKIP_SIZE; - blob->ads.golden_context_lrca[guc_class] = addr_ggtt; + ads_blob_write(guc, ads.eng_state_size[guc_class], + real_size - LRC_SKIP_SIZE); + ads_blob_write(guc, ads.golden_context_lrca[guc_class], + addr_ggtt); + addr_ggtt += alloc_size; } - if (!blob) + if (dma_buf_map_is_null(&guc->ads_map)) return total_size; GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); @@ -559,13 +569,15 @@ static void __guc_ads_init(struct intel_guc *guc) struct intel_gt *gt = guc_to_gt(guc); struct drm_i915_private *i915 = gt->i915; struct __guc_ads_blob *blob = guc->ads_blob; + struct dma_buf_map info_map = DMA_BUF_MAP_INIT_OFFSET(&guc->ads_map, + offsetof(struct __guc_ads_blob, system_info)); u32 base; /* GuC scheduling policies */ guc_policies_init(guc); /* System info */ - fill_engine_enable_masks(gt, &blob->system_info); + fill_engine_enable_masks(gt, &info_map); blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] = hweight8(gt->info.sseu.slice_mask); @@ -581,7 +593,7 @@ static void __guc_ads_init(struct intel_guc *guc) } /* Golden contexts for re-initialising after a watchdog reset */ - guc_prep_golden_context(guc, blob); + guc_prep_golden_context(guc); guc_mapping_table_init(guc_to_gt(guc), &blob->system_info); @@ -624,7 +636,7 @@ int intel_guc_ads_create(struct intel_guc *guc) guc->ads_regset_size = ret; /* Likewise the golden contexts: */ - ret = guc_prep_golden_context(guc, NULL); + ret = guc_prep_golden_context(guc); if (ret < 0) return ret; guc->ads_golden_ctxt_size = ret; -- 2.35.0
next prev parent reply other threads:[~2022-01-26 20:37 UTC|newest] Thread overview: 133+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-26 20:36 [PATCH 00/19] drm/i915/guc: Refactor ADS access to use dma_buf_map Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-26 20:36 ` [PATCH 01/19] dma-buf-map: Add read/write helpers Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-27 7:24 ` Christian König 2022-01-27 7:24 ` [Intel-gfx] " Christian König 2022-01-27 7:24 ` Christian König 2022-01-27 7:36 ` Matthew Brost 2022-01-27 7:36 ` [Intel-gfx] " Matthew Brost 2022-01-27 7:36 ` Matthew Brost 2022-01-27 7:59 ` Christian König 2022-01-27 7:59 ` [Intel-gfx] " Christian König 2022-01-27 7:59 ` Christian König 2022-01-27 9:02 ` [Intel-gfx] " Daniel Vetter 2022-01-27 9:02 ` Daniel Vetter 2022-01-27 14:26 ` Thomas Zimmermann 2022-01-27 14:26 ` [Intel-gfx] " Thomas Zimmermann 2022-01-27 14:26 ` Thomas Zimmermann 2022-01-27 16:34 ` Lucas De Marchi 2022-01-27 16:34 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 16:34 ` Lucas De Marchi 2022-01-28 8:32 ` Thomas Zimmermann 2022-01-28 8:32 ` [Intel-gfx] " Thomas Zimmermann 2022-01-28 8:32 ` Thomas Zimmermann 2022-01-26 20:36 ` [PATCH 02/19] dma-buf-map: Add helper to initialize second map Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 7:27 ` Christian König 2022-01-27 7:27 ` [Intel-gfx] " Christian König 2022-01-27 7:27 ` Christian König 2022-01-27 7:57 ` Lucas De Marchi 2022-01-27 7:57 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 7:57 ` Lucas De Marchi 2022-01-27 8:02 ` Christian König 2022-01-27 8:02 ` [Intel-gfx] " Christian König 2022-01-27 8:02 ` Christian König 2022-01-27 8:18 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 8:55 ` Christian König 2022-01-27 9:12 ` Lucas De Marchi 2022-01-27 9:12 ` Lucas De Marchi 2022-01-27 9:21 ` Christian König 2022-01-27 9:21 ` Christian König 2022-01-27 8:57 ` Daniel Vetter 2022-01-27 8:57 ` [Intel-gfx] " Daniel Vetter 2022-01-27 8:57 ` Daniel Vetter 2022-01-27 9:33 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 10:00 ` Daniel Vetter 2022-01-27 10:00 ` Daniel Vetter 2022-01-27 10:21 ` Christian König 2022-01-27 11:16 ` Daniel Vetter 2022-01-27 11:16 ` Daniel Vetter 2022-01-27 11:44 ` [Linaro-mm-sig] " Christian König 2022-01-27 11:44 ` [Intel-gfx] [Linaro-mm-sig] " Christian König 2022-01-27 11:56 ` [Linaro-mm-sig] Re: [Intel-gfx] " Daniel Vetter 2022-01-27 11:56 ` Daniel Vetter 2022-01-27 11:56 ` [Intel-gfx] [Linaro-mm-sig] " Daniel Vetter 2022-01-27 16:13 ` [Linaro-mm-sig] Re: [Intel-gfx] " Lucas De Marchi 2022-01-27 16:13 ` [Intel-gfx] [Linaro-mm-sig] " Lucas De Marchi 2022-01-27 16:13 ` [Linaro-mm-sig] Re: [Intel-gfx] " Lucas De Marchi 2022-01-27 14:52 ` Thomas Zimmermann 2022-01-27 16:12 ` Lucas De Marchi 2022-01-27 14:33 ` Thomas Zimmermann 2022-01-27 14:33 ` [Intel-gfx] " Thomas Zimmermann 2022-01-27 14:33 ` Thomas Zimmermann 2022-01-27 15:59 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 15:59 ` Lucas De Marchi 2022-01-28 8:15 ` Thomas Zimmermann 2022-01-28 8:34 ` Thomas Zimmermann 2022-01-26 20:36 ` [PATCH 03/19] drm/i915/gt: Add helper for shmem copy to dma_buf_map Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] [PATCH 04/19] drm/i915/guc: Keep dma_buf_map of ads_blob around Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-26 20:36 ` [PATCH 05/19] drm/i915/guc: Add read/write helpers for ADS blob Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] [PATCH 06/19] drm/i915/guc: Convert golden context init to dma_buf_map Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-26 20:36 ` [PATCH 07/19] drm/i915/guc: Convert policies update " Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [PATCH 08/19] drm/i915/guc: Convert engine record " Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [PATCH 09/19] dma-buf-map: Add wrapper over memset Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 7:28 ` Christian König 2022-01-27 7:28 ` [Intel-gfx] " Christian König 2022-01-27 7:28 ` Christian König 2022-01-27 14:54 ` Thomas Zimmermann 2022-01-27 14:54 ` [Intel-gfx] " Thomas Zimmermann 2022-01-27 14:54 ` Thomas Zimmermann 2022-01-27 15:38 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 15:38 ` Lucas De Marchi 2022-01-27 15:47 ` Thomas Zimmermann 2022-01-26 20:36 ` [PATCH 10/19] drm/i915/guc: Convert guc_ads_private_data_reset to dma_buf_map Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi [this message] 2022-01-26 20:36 ` [Intel-gfx] [PATCH 11/19] drm/i915/guc: Convert golden context prep " Lucas De Marchi 2022-01-26 20:36 ` [PATCH 12/19] drm/i915/guc: Replace check for golden context size Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] [PATCH 13/19] drm/i915/guc: Convert mapping table to dma_buf_map Lucas De Marchi 2022-01-26 20:36 ` Lucas De Marchi 2022-01-26 20:36 ` [PATCH 14/19] drm/i915/guc: Convert capture list " Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [PATCH 15/19] drm/i915/guc: Prepare for error propagation Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:36 ` [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset Lucas De Marchi 2022-01-26 20:36 ` [Intel-gfx] " Lucas De Marchi 2022-01-27 0:29 ` kernel test robot 2022-01-27 0:29 ` kernel test robot 2022-01-27 0:29 ` [Intel-gfx] " kernel test robot 2022-01-27 2:02 ` kernel test robot 2022-01-27 2:02 ` kernel test robot 2022-01-27 2:02 ` [Intel-gfx] " kernel test robot 2022-01-27 2:02 ` kernel test robot 2022-01-27 4:37 ` kernel test robot 2022-01-27 4:37 ` kernel test robot 2022-01-27 4:37 ` [Intel-gfx] " kernel test robot 2022-02-01 22:42 ` Daniele Ceraolo Spurio 2022-02-01 22:42 ` [Intel-gfx] " Daniele Ceraolo Spurio 2022-02-03 23:44 ` Lucas De Marchi 2022-02-03 23:44 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:37 ` [PATCH 17/19] drm/i915/guc: Convert guc_mmio_reg_state_init to dma_buf_map Lucas De Marchi 2022-01-26 20:37 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:37 ` [PATCH 18/19] drm/i915/guc: Convert __guc_ads_init " Lucas De Marchi 2022-01-26 20:37 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 20:37 ` [PATCH 19/19] drm/i915/guc: Remove plain ads_blob pointer Lucas De Marchi 2022-01-26 20:37 ` [Intel-gfx] " Lucas De Marchi 2022-01-26 23:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map Patchwork 2022-01-26 23:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-01-26 23:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-01-26 23:42 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork 2022-01-27 5:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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