* Re: [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support
@ 2022-01-28 8:35 kernel test robot
2022-01-30 2:33 ` kernel test robot
0 siblings, 1 reply; 7+ messages in thread
From: kernel test robot @ 2022-01-28 8:35 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 15442 bytes --]
CC: llvm(a)lists.linux.dev
CC: kbuild-all(a)lists.01.org
In-Reply-To: <20220126233454.3362047-4-eranian@google.com>
References: <20220126233454.3362047-4-eranian@google.com>
TO: Stephane Eranian <eranian@google.com>
Hi Stephane,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20220125]
[cannot apply to tip/x86/core rafael-pm/linux-next tip/perf/core v5.17-rc1 v5.16 v5.16-rc8 v5.17-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516
base: d25ee88530253138d0b20d43511ca5acbda4e9f7
:::::: branch date: 32 hours ago
:::::: commit date: 32 hours ago
config: x86_64-randconfig-c007-20220124 (https://download.01.org/0day-ci/archive/20220128/202201281639.FC1PUTSK-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 33b45ee44b1f32ffdbc995e6fec806271b4b3ba4)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/933d072f6e0c0409115a8038a89a56979a042d30
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516
git checkout 933d072f6e0c0409115a8038a89a56979a042d30
# save the config file to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 clang-analyzer
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
clang-analyzer warnings: (new ones prefixed by >>)
include/linux/build_bug.h:50:2: note: expanded from macro 'BUILD_BUG_ON'
BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
^
include/linux/build_bug.h:39:37: note: expanded from macro 'BUILD_BUG_ON_MSG'
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^
include/linux/compiler_types.h:346:2: note: expanded from macro 'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^
include/linux/compiler_types.h:334:2: note: expanded from macro '_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
^
include/linux/compiler_types.h:318:2: note: expanded from macro '__compiletime_assert'
do { \
^
include/scsi/scsi_device.h:469:9: note: Calling '__scsi_execute'
return scsi_execute(sdev, cmd, data_direction, buffer,
^
include/scsi/scsi_device.h:460:2: note: expanded from macro 'scsi_execute'
__scsi_execute(sdev, cmd, data_direction, buffer, bufflen, \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/scsi/scsi_lib.c:220:4: note: 'data_direction' is not equal to DMA_TO_DEVICE
data_direction == DMA_TO_DEVICE ?
^~~~~~~~~~~~~~
drivers/scsi/scsi_lib.c:220:4: note: '?' condition is false
drivers/scsi/scsi_lib.c:222:4: note: '?' condition is false
rq_flags & RQF_PM ? BLK_MQ_REQ_PM : 0);
^
drivers/scsi/scsi_lib.c:223:2: note: Taking true branch
if (IS_ERR(req))
^
drivers/scsi/scsi_lib.c:224:3: note: Returning without writing to 'sshdr->response_code'
return PTR_ERR(req);
^
include/scsi/scsi_device.h:469:9: note: Returning from '__scsi_execute'
return scsi_execute(sdev, cmd, data_direction, buffer,
^
include/scsi/scsi_device.h:460:2: note: expanded from macro 'scsi_execute'
__scsi_execute(sdev, cmd, data_direction, buffer, bufflen, \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/scsi/scsi_device.h:469:2: note: Returning without writing to 'sshdr->response_code'
return scsi_execute(sdev, cmd, data_direction, buffer,
^
drivers/scsi/scsi_lib.c:2202:11: note: Returning from 'scsi_execute_req'
result = scsi_execute_req(sdev, cmd, DMA_FROM_DEVICE, buffer, len,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/scsi/scsi_lib.c:2204:6: note: Assuming 'result' is >= 0
if (result < 0)
^~~~~~~~~~
drivers/scsi/scsi_lib.c:2204:2: note: Taking false branch
if (result < 0)
^
drivers/scsi/scsi_lib.c:2212:7: note: Calling 'scsi_status_is_good'
if (!scsi_status_is_good(result)) {
^~~~~~~~~~~~~~~~~~~~~~~~~~~
include/scsi/scsi.h:198:6: note: 'status' is >= 0
if (status < 0)
^~~~~~
include/scsi/scsi.h:198:2: note: Taking false branch
if (status < 0)
^
include/scsi/scsi.h:201:6: note: Assuming the condition is true
if (host_byte(status) == DID_NO_CONNECT)
^
include/scsi/scsi.h:124:29: note: expanded from macro 'host_byte'
#define host_byte(result) (((result) >> 16) & 0xff)
^
include/scsi/scsi.h:201:2: note: Taking true branch
if (host_byte(status) == DID_NO_CONNECT)
^
include/scsi/scsi.h:202:3: note: Returning zero, which participates in a condition later
return false;
^~~~~~~~~~~~
drivers/scsi/scsi_lib.c:2212:7: note: Returning from 'scsi_status_is_good'
if (!scsi_status_is_good(result)) {
^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/scsi/scsi_lib.c:2212:2: note: Taking true branch
if (!scsi_status_is_good(result)) {
^
drivers/scsi/scsi_lib.c:2213:7: note: Calling 'scsi_sense_valid'
if (scsi_sense_valid(sshdr)) {
^~~~~~~~~~~~~~~~~~~~~~~
include/scsi/scsi_common.h:63:7: note: 'sshdr' is non-null
if (!sshdr)
^~~~~
include/scsi/scsi_common.h:63:2: note: Taking false branch
if (!sshdr)
^
include/scsi/scsi_common.h:66:31: note: The left operand of '&' is a garbage value
return (sshdr->response_code & 0x70) == 0x70;
~~~~~~~~~~~~~~~~~~~~ ^
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
3 warnings generated.
>> arch/x86/events/amd/core.c:682:3: warning: Value stored to 'hwc' is never read [clang-analyzer-deadcode.DeadStores]
hwc = &cpuc->events[idx]->hw;
^ ~~~~~~~~~~~~~~~~~~~~~~
arch/x86/events/amd/core.c:682:3: note: Value stored to 'hwc' is never read
hwc = &cpuc->events[idx]->hw;
^ ~~~~~~~~~~~~~~~~~~~~~~
Suppressed 2 warnings (1 in non-user code, 1 with check filters).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 with check filters).
1 warning generated.
Suppressed 1 warnings (1 with check filters).
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
1 warning generated.
Suppressed 1 warnings (1 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
2 warnings generated.
drivers/dma-buf/dma-resv.c:525:34: warning: Access to field 'shared_count' results in a dereference of a null pointer (loaded from variable 'list') [clang-analyzer-core.NullDereference]
RCU_INIT_POINTER(list->shared[list->shared_count++], f);
^
include/linux/rcupdate.h:860:14: note: expanded from macro 'RCU_INIT_POINTER'
WRITE_ONCE(p, RCU_INITIALIZER(v)); \
^
include/asm-generic/rwonce.h:61:15: note: expanded from macro 'WRITE_ONCE'
__WRITE_ONCE(x, val); \
^
include/asm-generic/rwonce.h:55:27: note: expanded from macro '__WRITE_ONCE'
*(volatile typeof(x) *)&(x) = (val); \
^
drivers/dma-buf/dma-resv.c:494:2: note: Assuming 'debug_locks' is 0
dma_resv_assert_held(dst);
^
include/linux/dma-resv.h:271:35: note: expanded from macro 'dma_resv_assert_held'
#define dma_resv_assert_held(obj) lockdep_assert_held(&(obj)->lock.base)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/lockdep.h:316:2: note: expanded from macro 'lockdep_assert_held'
lockdep_assert(lockdep_is_held(l) != LOCK_STATE_NOT_HELD)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/lockdep.h:310:15: note: expanded from macro 'lockdep_assert'
do { WARN_ON(debug_locks && !(cond)); } while (0)
^~~~~~~~~~~
include/asm-generic/bug.h:121:25: note: expanded from macro 'WARN_ON'
int __ret_warn_on = !!(condition); \
^~~~~~~~~
drivers/dma-buf/dma-resv.c:494:2: note: Left side of '&&' is false
dma_resv_assert_held(dst);
^
include/linux/dma-resv.h:271:35: note: expanded from macro 'dma_resv_assert_held'
#define dma_resv_assert_held(obj) lockdep_assert_held(&(obj)->lock.base)
^
include/linux/lockdep.h:316:2: note: expanded from macro 'lockdep_assert_held'
lockdep_assert(lockdep_is_held(l) != LOCK_STATE_NOT_HELD)
^
include/linux/lockdep.h:310:27: note: expanded from macro 'lockdep_assert'
do { WARN_ON(debug_locks && !(cond)); } while (0)
^
drivers/dma-buf/dma-resv.c:494:2: note: Taking false branch
dma_resv_assert_held(dst);
^
include/linux/dma-resv.h:271:35: note: expanded from macro 'dma_resv_assert_held'
#define dma_resv_assert_held(obj) lockdep_assert_held(&(obj)->lock.base)
^
include/linux/lockdep.h:316:2: note: expanded from macro 'lockdep_assert_held'
lockdep_assert(lockdep_is_held(l) != LOCK_STATE_NOT_HELD)
^
include/linux/lockdep.h:310:7: note: expanded from macro 'lockdep_assert'
do { WARN_ON(debug_locks && !(cond)); } while (0)
^
include/asm-generic/bug.h:122:2: note: expanded from macro 'WARN_ON'
if (unlikely(__ret_warn_on)) \
^
drivers/dma-buf/dma-resv.c:494:2: note: Loop condition is false. Exiting loop
dma_resv_assert_held(dst);
^
include/linux/dma-resv.h:271:35: note: expanded from macro 'dma_resv_assert_held'
#define dma_resv_assert_held(obj) lockdep_assert_held(&(obj)->lock.base)
^
include/linux/lockdep.h:316:2: note: expanded from macro 'lockdep_assert_held'
lockdep_assert(lockdep_is_held(l) != LOCK_STATE_NOT_HELD)
^
include/linux/lockdep.h:310:2: note: expanded from macro 'lockdep_assert'
vim +/hwc +682 arch/x86/events/amd/core.c
933d072f6e0c04 Stephane Eranian 2022-01-26 672
933d072f6e0c04 Stephane Eranian 2022-01-26 673 static void amd_pmu_enable_all(int added)
933d072f6e0c04 Stephane Eranian 2022-01-26 674 {
933d072f6e0c04 Stephane Eranian 2022-01-26 675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
933d072f6e0c04 Stephane Eranian 2022-01-26 676 struct hw_perf_event *hwc;
933d072f6e0c04 Stephane Eranian 2022-01-26 677 int idx;
933d072f6e0c04 Stephane Eranian 2022-01-26 678
933d072f6e0c04 Stephane Eranian 2022-01-26 679 amd_brs_enable_all();
933d072f6e0c04 Stephane Eranian 2022-01-26 680
933d072f6e0c04 Stephane Eranian 2022-01-26 681 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
933d072f6e0c04 Stephane Eranian 2022-01-26 @682 hwc = &cpuc->events[idx]->hw;
933d072f6e0c04 Stephane Eranian 2022-01-26 683
933d072f6e0c04 Stephane Eranian 2022-01-26 684 /* only activate events which are marked as active */
933d072f6e0c04 Stephane Eranian 2022-01-26 685 if (!test_bit(idx, cpuc->active_mask))
933d072f6e0c04 Stephane Eranian 2022-01-26 686 continue;
933d072f6e0c04 Stephane Eranian 2022-01-26 687
933d072f6e0c04 Stephane Eranian 2022-01-26 688 amd_pmu_enable_event(cpuc->events[idx]);
933d072f6e0c04 Stephane Eranian 2022-01-26 689 }
933d072f6e0c04 Stephane Eranian 2022-01-26 690 }
933d072f6e0c04 Stephane Eranian 2022-01-26 691
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support 2022-01-28 8:35 [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support kernel test robot @ 2022-01-30 2:33 ` kernel test robot 0 siblings, 0 replies; 7+ messages in thread From: kernel test robot @ 2022-01-30 2:33 UTC (permalink / raw) To: Stephane Eranian; +Cc: llvm, kbuild-all Hi Stephane, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20220125] [cannot apply to tip/x86/core rafael-pm/linux-next tip/perf/core v5.17-rc1 v5.16 v5.16-rc8 v5.17-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 base: d25ee88530253138d0b20d43511ca5acbda4e9f7 config: x86_64-randconfig-c007-20220124 (https://download.01.org/0day-ci/archive/20220128/202201281639.FC1PUTSK-lkp@intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 33b45ee44b1f32ffdbc995e6fec806271b4b3ba4) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/933d072f6e0c0409115a8038a89a56979a042d30 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 git checkout 933d072f6e0c0409115a8038a89a56979a042d30 # save the config file to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 clang-analyzer If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <yujie.liu@intel.com> clang-analyzer warnings: (new ones prefixed by >>) >> arch/x86/events/amd/core.c:682:3: warning: Value stored to 'hwc' is never read [clang-analyzer-deadcode.DeadStores] hwc = &cpuc->events[idx]->hw; ^ ~~~~~~~~~~~~~~~~~~~~~~ vim +/hwc +682 arch/x86/events/amd/core.c 933d072f6e0c04 Stephane Eranian 2022-01-26 672 933d072f6e0c04 Stephane Eranian 2022-01-26 673 static void amd_pmu_enable_all(int added) 933d072f6e0c04 Stephane Eranian 2022-01-26 674 { 933d072f6e0c04 Stephane Eranian 2022-01-26 675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 933d072f6e0c04 Stephane Eranian 2022-01-26 @676 struct hw_perf_event *hwc; 933d072f6e0c04 Stephane Eranian 2022-01-26 677 int idx; 933d072f6e0c04 Stephane Eranian 2022-01-26 678 933d072f6e0c04 Stephane Eranian 2022-01-26 679 amd_brs_enable_all(); 933d072f6e0c04 Stephane Eranian 2022-01-26 680 933d072f6e0c04 Stephane Eranian 2022-01-26 681 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 933d072f6e0c04 Stephane Eranian 2022-01-26 @682 hwc = &cpuc->events[idx]->hw; 933d072f6e0c04 Stephane Eranian 2022-01-26 683 933d072f6e0c04 Stephane Eranian 2022-01-26 684 /* only activate events which are marked as active */ 933d072f6e0c04 Stephane Eranian 2022-01-26 685 if (!test_bit(idx, cpuc->active_mask)) 933d072f6e0c04 Stephane Eranian 2022-01-26 686 continue; 933d072f6e0c04 Stephane Eranian 2022-01-26 687 933d072f6e0c04 Stephane Eranian 2022-01-26 688 amd_pmu_enable_event(cpuc->events[idx]); 933d072f6e0c04 Stephane Eranian 2022-01-26 689 } 933d072f6e0c04 Stephane Eranian 2022-01-26 690 } 933d072f6e0c04 Stephane Eranian 2022-01-26 691 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support @ 2022-01-30 2:33 ` kernel test robot 0 siblings, 0 replies; 7+ messages in thread From: kernel test robot @ 2022-01-30 2:33 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 3501 bytes --] Hi Stephane, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20220125] [cannot apply to tip/x86/core rafael-pm/linux-next tip/perf/core v5.17-rc1 v5.16 v5.16-rc8 v5.17-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 base: d25ee88530253138d0b20d43511ca5acbda4e9f7 config: x86_64-randconfig-c007-20220124 (https://download.01.org/0day-ci/archive/20220128/202201281639.FC1PUTSK-lkp(a)intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 33b45ee44b1f32ffdbc995e6fec806271b4b3ba4) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/933d072f6e0c0409115a8038a89a56979a042d30 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 git checkout 933d072f6e0c0409115a8038a89a56979a042d30 # save the config file to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 clang-analyzer If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <yujie.liu@intel.com> clang-analyzer warnings: (new ones prefixed by >>) >> arch/x86/events/amd/core.c:682:3: warning: Value stored to 'hwc' is never read [clang-analyzer-deadcode.DeadStores] hwc = &cpuc->events[idx]->hw; ^ ~~~~~~~~~~~~~~~~~~~~~~ vim +/hwc +682 arch/x86/events/amd/core.c 933d072f6e0c04 Stephane Eranian 2022-01-26 672 933d072f6e0c04 Stephane Eranian 2022-01-26 673 static void amd_pmu_enable_all(int added) 933d072f6e0c04 Stephane Eranian 2022-01-26 674 { 933d072f6e0c04 Stephane Eranian 2022-01-26 675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 933d072f6e0c04 Stephane Eranian 2022-01-26 @676 struct hw_perf_event *hwc; 933d072f6e0c04 Stephane Eranian 2022-01-26 677 int idx; 933d072f6e0c04 Stephane Eranian 2022-01-26 678 933d072f6e0c04 Stephane Eranian 2022-01-26 679 amd_brs_enable_all(); 933d072f6e0c04 Stephane Eranian 2022-01-26 680 933d072f6e0c04 Stephane Eranian 2022-01-26 681 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 933d072f6e0c04 Stephane Eranian 2022-01-26 @682 hwc = &cpuc->events[idx]->hw; 933d072f6e0c04 Stephane Eranian 2022-01-26 683 933d072f6e0c04 Stephane Eranian 2022-01-26 684 /* only activate events which are marked as active */ 933d072f6e0c04 Stephane Eranian 2022-01-26 685 if (!test_bit(idx, cpuc->active_mask)) 933d072f6e0c04 Stephane Eranian 2022-01-26 686 continue; 933d072f6e0c04 Stephane Eranian 2022-01-26 687 933d072f6e0c04 Stephane Eranian 2022-01-26 688 amd_pmu_enable_event(cpuc->events[idx]); 933d072f6e0c04 Stephane Eranian 2022-01-26 689 } 933d072f6e0c04 Stephane Eranian 2022-01-26 690 } 933d072f6e0c04 Stephane Eranian 2022-01-26 691 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v5 00/14] perf/x86/amd: Add AMD Fam19h Branch Sampling support @ 2022-01-26 23:34 Stephane Eranian 2022-01-26 23:34 ` [PATCH v5 03/13] perf/x86/amd: add " Stephane Eranian 0 siblings, 1 reply; 7+ messages in thread From: Stephane Eranian @ 2022-01-26 23:34 UTC (permalink / raw) To: linux-kernel; +Cc: peterz, kim.phillips, acme, jolsa, songliubraving This patch series adds support for the AMD Fam19h 16-deep branch sampling feature as described in the AMD PPR Fam19h Model 01h Revision B1 section 2.1.13. This is a model specific extension. It is not an architected AMD feature. The Branch Sampling Feature (BRS) provides the statistical taken branch information necessary to enable autoFDO-style optimization by compilers, i.e., basic block execution counts. BRS operates with a 16-deep saturating buffer in MSR registers. There is no hardware branch type filtering. All control flow changes are captured. BRS relies on specific programming of the core PMU of Fam19h. In particular, the following requirements must be met: - the sampling period be greater than 16 (BRS depth) - the sampling period must use fixed and not frequency mode BRS interacts with the NMI interrupt as well. Because enabling BRS is expensive, it is only activated after P event occurrences, where P is the desired sampling period. At P occurrences of the event, the counter overflows, the CPU catches the NMI interrupt, activates BRS for 16 branches until it saturates, and then delivers the NMI to the kernel. Between the overflow and the time BRS activates more branches may be executed skewing the period. All along, the sampling event keeps counting. The skid may be attenuated by reducing the sampling period by 16. BRS is integrated into perf_events seamlessly via the same PERF_RECORD_BRANCH_STACK sample format. BRS generates branch perf_branch_entry records in the sampling buffer. There is no prediction or latency information supported. The branches are stored in reverse order of execution. The most recent branch is the first entry in each record. Because BRS must be stopped when a CPU goes into low power mode, the series includes patches to add callbacks on ACPI low power entry and exit which is used on AMD processors. Given that there is no privilege filterting with BRS, the kernel implements filtering on privlege level. This version adds a few simple modifications to perf record and report. 1. add the branch-brs event as a builtin such as it can used directly: perf record -e branch-brs ... 2. improve error handling for AMD IBS and is contributed by Kim Phillips. 3. use the better error handling to improve error handling for BRS. 4. add two new sort dimensions to help display the branch sampling information. Because there is no latency information associated with the branch sampling feature perf report would collapse all samples within a function into a single histogram entry. This is expected because the default sort mode for PERF_SAMPLE_BRANCH_STACK is symbol_from/symbol_to. This propagates to the annotation. For more detailed view of the branch samples, the new sort dimensions addr_from,addr_to can be used instead as follows: $ perf report --sort=overhead,comm,dso,addr_from,addr_to # Overhead Command Shared Object Source Address Target Address # ........ .......... .............. .............. .............. # 4.21% test_prg test_prg [.] test_threa+0x3c [.] test_threa+0x4 4.14% test_prg test_prg [.] test_threa+0x3e [.] test_threa+0x2 4.10% test_prg test_prg [.] test_threa+0x4 [.] test_threa+0x3a 4.07% test_prg test_prg [.] test_threa+0x2 [.] test_threa+0x3c Versus the default output: $ perf report # Overhead Command Source Shared Object Source Symbol Target Symbol Basic Block Cycles # ........ ......... .................... ................ ................. .................. # 99.52% test_prg test_prg [.] test_thread [.] test_thread - BRS can be used with any sampling event. However, it is recommended to use the RETIRED_BRANCH event because it matches what the BRS captures. For convenience, a pseudo event matching the branches captured by BRS is exported by the kernel (branch-brs): $ perf record -b -e cpu/branch-brs/ -c 1000037 test $ perf report -D 56531696056126 0x193c000 [0x1a8]: PERF_RECORD_SAMPLE(IP, 0x2): 18122/18230: 0x401d24 period: 1000037 addr: 0 ... branch stack: nr:16 ..... 0: 0000000000401d24 -> 0000000000401d5a 0 cycles 0 ..... 1: 0000000000401d5c -> 0000000000401d24 0 cycles 0 ..... 2: 0000000000401d22 -> 0000000000401d5c 0 cycles 0 ..... 3: 0000000000401d5e -> 0000000000401d22 0 cycles 0 ..... 4: 0000000000401d20 -> 0000000000401d5e 0 cycles 0 ..... 5: 0000000000401d3e -> 0000000000401d20 0 cycles 0 ..... 6: 0000000000401d42 -> 0000000000401d3e 0 cycles 0 ..... 7: 0000000000401d3c -> 0000000000401d42 0 cycles 0 ..... 8: 0000000000401d44 -> 0000000000401d3c 0 cycles 0 ..... 9: 0000000000401d3a -> 0000000000401d44 0 cycles 0 ..... 10: 0000000000401d46 -> 0000000000401d3a 0 cycles 0 ..... 11: 0000000000401d38 -> 0000000000401d46 0 cycles 0 ..... 12: 0000000000401d48 -> 0000000000401d38 0 cycles 0 ..... 13: 0000000000401d36 -> 0000000000401d48 0 cycles 0 ..... 14: 0000000000401d4a -> 0000000000401d36 0 cycles 0 ..... 15: 0000000000401d34 -> 0000000000401d4a 0 cycles 0 ... thread: test:18230 ...... dso: test Special thanks to Kim Phillips @ AMD for the testing, reviews and contributions. V2 makes the following changes: - the low power callback code has be reworked completly. It is not impacting the generic perf_events code anymore. This is all handled via x86 code and only for ACPI low power driver which seems to be the default on AMD. The change in acpi_pad.c and processor_idle.c has no impact on non x86 architectures, on Intel x86 or AMD without BRS, a jump label is used to void the code unless necessary - BRS is an opt-in compile time option for the kernel - branch_stack bit clearing helper is introduced - As for the fact that BRS holds the NMI and that it may conflict with other sampling events and introduced skid, this is not really a problem because AMD PMI skid is already very large prompting special handling in amd_pmu_wait_on_overflow(), so adding a few cycles while the CPU executes at most 16 taken branches is not a problem. V3 makes the following changes: - simplifies the handling of BRS enable/disable to mimic the Intel LBR code path more closely. That removes some callbacks in generic x86 code - add config option to compile BRS as an opt-in (off by default) - updated perf tool error reporting patch updates by Kim Phillips V4 makes the following changes: - rebase to latest tip.git (commit 6f5ac142e5df) - integrate Kim Phillips latest perf tool error handling patches V5 makes the following changes: - rebased to 5.17-rc1 - integrated feedback from PeterZ about AMD perf_events callbacks - fix cpufeature macros name X86_FEATURE_BRS - integrated all perf tool error handling from kim Phillips Kim Phillips (2): perf evsel: Make evsel__env always return a valid env perf tools: Improve IBS error handling Stephane Eranian (11): perf/core: add perf_clear_branch_entry_bitfields() helper x86/cpufeatures: add AMD Fam19h Branch Sampling feature perf/x86/amd: add AMD Fam19h Branch Sampling support perf/x86/amd: add branch-brs helper event for Fam19h BRS perf/x86/amd: enable branch sampling priv level filtering perf/x86/amd: add AMD branch sampling period adjustment perf/x86/amd: make Zen3 branch sampling opt-in ACPI: add perf low power callback perf/x86/amd: add idle hooks for branch sampling perf tools: Improve error handling of AMD Branch Sampling perf report: add addr_from/addr_to sort dimensions arch/x86/events/Kconfig | 8 + arch/x86/events/amd/Makefile | 1 + arch/x86/events/amd/brs.c | 363 +++++++++++++++++++++++++++++ arch/x86/events/amd/core.c | 217 ++++++++++++++++- arch/x86/events/core.c | 17 +- arch/x86/events/intel/lbr.c | 36 ++- arch/x86/events/perf_event.h | 143 ++++++++++-- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 4 + arch/x86/include/asm/perf_event.h | 21 ++ drivers/acpi/acpi_pad.c | 6 + drivers/acpi/processor_idle.c | 5 + include/linux/perf_event.h | 22 ++ tools/perf/util/evsel.c | 40 +++- tools/perf/util/hist.c | 2 + tools/perf/util/hist.h | 2 + tools/perf/util/sort.c | 128 ++++++++++ tools/perf/util/sort.h | 2 + 18 files changed, 977 insertions(+), 41 deletions(-) create mode 100644 arch/x86/events/amd/brs.c -- 2.35.0.rc0.227.g00780c9af4-goog ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support 2022-01-26 23:34 [PATCH v5 00/14] perf/x86/amd: Add " Stephane Eranian @ 2022-01-26 23:34 ` Stephane Eranian 2022-01-27 1:52 ` kernel test robot 2022-01-27 6:09 ` kernel test robot 0 siblings, 2 replies; 7+ messages in thread From: Stephane Eranian @ 2022-01-26 23:34 UTC (permalink / raw) To: linux-kernel; +Cc: peterz, kim.phillips, acme, jolsa, songliubraving This patch adds support for the AMD Fam19h 16-deep branch sampling feature as described in the AMD PPR Fam19h Model 01h Revision B1. This is a model specific extension. It is not an architected AMD feature. The Branch Sampling (BRS) operates with a 16-deep saturating buffer in MSR registers. There is no branch type filtering. All control flow changes are captured. BRS relies on specific programming of the core PMU of Fam19h. In particular, the following requirements must be met: - the sampling period be greater than 16 (BRS depth) - the sampling period must use a fixed and not frequency mode BRS interacts with the NMI interrupt as well. Because enabling BRS is expensive, it is only activated after P event occurrences, where P is the desired sampling period. At P occurrences of the event, the counter overflows, the CPU catches the interrupt, activates BRS for 16 branches until it saturates, and then delivers the NMI to the kernel. Between the overflow and the time BRS activates more branches may be executed skewing the period. All along, the sampling event keeps counting. The skid may be attenuated by reducing the sampling period by 16 (subsequent patch). BRS is integrated into perf_events seamlessly via the same PERF_RECORD_BRANCH_STACK sample format. BRS generates perf_branch_entry records in the sampling buffer. No prediction information is supported. The branches are stored in reverse order of execution. The most recent branch is the first entry in each record. No modification to the perf tool is necessary. BRS can be used with any sampling event. However, it is recommended to use the RETIRED_BRANCH_INSTRUCTIONS event because it matches what the BRS captures. $ perf record -b -c 1000037 -e cpu/event=0xc2,name=ret_br_instructions/ test $ perf report -D 56531696056126 0x193c000 [0x1a8]: PERF_RECORD_SAMPLE(IP, 0x2): 18122/18230: 0x401d24 period: 1000037 addr: 0 ... branch stack: nr:16 ..... 0: 0000000000401d24 -> 0000000000401d5a 0 cycles 0 ..... 1: 0000000000401d5c -> 0000000000401d24 0 cycles 0 ..... 2: 0000000000401d22 -> 0000000000401d5c 0 cycles 0 ..... 3: 0000000000401d5e -> 0000000000401d22 0 cycles 0 ..... 4: 0000000000401d20 -> 0000000000401d5e 0 cycles 0 ..... 5: 0000000000401d3e -> 0000000000401d20 0 cycles 0 ..... 6: 0000000000401d42 -> 0000000000401d3e 0 cycles 0 ..... 7: 0000000000401d3c -> 0000000000401d42 0 cycles 0 ..... 8: 0000000000401d44 -> 0000000000401d3c 0 cycles 0 ..... 9: 0000000000401d3a -> 0000000000401d44 0 cycles 0 ..... 10: 0000000000401d46 -> 0000000000401d3a 0 cycles 0 ..... 11: 0000000000401d38 -> 0000000000401d46 0 cycles 0 ..... 12: 0000000000401d48 -> 0000000000401d38 0 cycles 0 ..... 13: 0000000000401d36 -> 0000000000401d48 0 cycles 0 ..... 14: 0000000000401d4a -> 0000000000401d36 0 cycles 0 ..... 15: 0000000000401d34 -> 0000000000401d4a 0 cycles 0 ... thread: test:18230 ...... dso: test Signed-off-by: Stephane Eranian <eranian@google.com> --- arch/x86/events/amd/Makefile | 2 +- arch/x86/events/amd/brs.c | 317 +++++++++++++++++++++++++++++++ arch/x86/events/amd/core.c | 197 ++++++++++++++++++- arch/x86/events/core.c | 10 +- arch/x86/events/perf_event.h | 101 ++++++++-- arch/x86/include/asm/msr-index.h | 4 + 6 files changed, 609 insertions(+), 22 deletions(-) create mode 100644 arch/x86/events/amd/brs.c diff --git a/arch/x86/events/amd/Makefile b/arch/x86/events/amd/Makefile index 6cbe38d5fd9d..cf323ffab5cd 100644 --- a/arch/x86/events/amd/Makefile +++ b/arch/x86/events/amd/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_CPU_SUP_AMD) += core.o +obj-$(CONFIG_CPU_SUP_AMD) += core.o brs.o obj-$(CONFIG_PERF_EVENTS_AMD_POWER) += power.o obj-$(CONFIG_X86_LOCAL_APIC) += ibs.o obj-$(CONFIG_PERF_EVENTS_AMD_UNCORE) += amd-uncore.o diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c new file mode 100644 index 000000000000..3c13c484c637 --- /dev/null +++ b/arch/x86/events/amd/brs.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Implement support for AMD Fam19h Branch Sampling feature + * Based on specifications published in AMD PPR Fam19 Model 01 + * + * Copyright 2021 Google LLC + * Contributed by Stephane Eranian <eranian@google.com> + */ +#include <linux/kernel.h> +#include <asm/msr.h> +#include <asm/cpufeature.h> + +#include "../perf_event.h" + +#define BRS_POISON 0xFFFFFFFFFFFFFFFEULL /* mark limit of valid entries */ + +/* Debug Extension Configuration register layout */ +union amd_debug_extn_cfg { + __u64 val; + struct { + __u64 rsvd0:2, /* reserved */ + brsmen:1, /* branch sample enable */ + rsvd4_3:2,/* reserved - must be 0x3 */ + vb:1, /* valid branches recorded */ + rsvd2:10, /* reserved */ + msroff:4, /* index of next entry to write */ + rsvd3:4, /* reserved */ + pmc:3, /* #PMC holding the sampling event */ + rsvd4:37; /* reserved */ + }; +}; + +static inline unsigned int brs_from(int idx) +{ + return MSR_AMD_SAMP_BR_FROM + 2 * idx; +} + +static inline unsigned int brs_to(int idx) +{ + return MSR_AMD_SAMP_BR_FROM + 2 * idx + 1; +} + +static inline void set_debug_extn_cfg(u64 val) +{ + /* bits[4:3] must always be set to 11b */ + wrmsrl(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3); +} + +static inline u64 get_debug_extn_cfg(void) +{ + u64 val; + + rdmsrl(MSR_AMD_DBG_EXTN_CFG, val); + return val; +} + +static bool __init amd_brs_detect(void) +{ + if (!boot_cpu_has(X86_FEATURE_BRS)) + return false; + + switch (boot_cpu_data.x86) { + case 0x19: /* AMD Fam19h (Zen3) */ + x86_pmu.lbr_nr = 16; + + /* No hardware filtering supported */ + x86_pmu.lbr_sel_map = NULL; + x86_pmu.lbr_sel_mask = 0; + break; + default: + return false; + } + + return true; +} + +/* + * Current BRS implementation does not support branch type or privilege level + * filtering. Therefore, this function simply enforces these limitations. No need for + * a br_sel_map. Software filtering is not supported because it would not correlate well + * with a sampling period. + */ +int amd_brs_setup_filter(struct perf_event *event) +{ + u64 type = event->attr.branch_sample_type; + + /* No BRS support */ + if (!x86_pmu.lbr_nr) + return -EOPNOTSUPP; + + /* Can only capture all branches, i.e., no filtering */ + if ((type & ~PERF_SAMPLE_BRANCH_PLM_ALL) != PERF_SAMPLE_BRANCH_ANY) + return -EINVAL; + + /* can only capture at all priv levels due to the way BRS works */ + if ((type & PERF_SAMPLE_BRANCH_PLM_ALL) != PERF_SAMPLE_BRANCH_PLM_ALL) + return -EINVAL; + + return 0; +} + +/* tos = top of stack, i.e., last valid entry written */ +static inline int amd_brs_get_tos(union amd_debug_extn_cfg *cfg) +{ + /* + * msroff: index of next entry to write so top-of-stack is one off + * if BRS is full then msroff is set back to 0. + */ + return (cfg->msroff ? cfg->msroff : x86_pmu.lbr_nr) - 1; +} + +/* + * make sure we have a sane BRS offset to begin with + * especially with kexec + */ +void amd_brs_reset(void) +{ + /* + * Reset config + */ + set_debug_extn_cfg(0); + + /* + * Mark first entry as poisoned + */ + wrmsrl(brs_to(0), BRS_POISON); +} + +int __init amd_brs_init(void) +{ + if (!amd_brs_detect()) + return -EOPNOTSUPP; + + pr_cont("%d-deep BRS, ", x86_pmu.lbr_nr); + + return 0; +} + +void amd_brs_enable(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + union amd_debug_extn_cfg cfg; + + /* Activate only on first user */ + if (++cpuc->brs_active > 1) + return; + + cfg.val = 0; /* reset all fields */ + cfg.brsmen = 1; /* enable branch sampling */ + + /* Set enable bit */ + set_debug_extn_cfg(cfg.val); +} + +void amd_brs_enable_all(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + if (cpuc->lbr_users) + amd_brs_enable(); +} + +void amd_brs_disable(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + union amd_debug_extn_cfg cfg; + + /* Check if active (could be disabled via x86_pmu_disable_all()) */ + if (!cpuc->brs_active) + return; + + /* Only disable for last user */ + if (--cpuc->brs_active) + return; + + /* + * Clear the brsmen bit but preserve the others as they contain + * useful state such as vb and msroff + */ + cfg.val = get_debug_extn_cfg(); + + /* + * When coming in on interrupt and BRS is full, then hw will have + * already stopped BRS, no need to issue wrmsr again + */ + if (cfg.brsmen) { + cfg.brsmen = 0; + set_debug_extn_cfg(cfg.val); + } +} + +void amd_brs_disable_all(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + if (cpuc->lbr_users) + amd_brs_disable(); +} + +/* + * Caller must ensure amd_brs_inuse() is true before calling + * return: + */ +void amd_brs_drain(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + struct perf_event *event = cpuc->events[0]; + struct perf_branch_entry *br = cpuc->lbr_entries; + union amd_debug_extn_cfg cfg; + u32 i, nr = 0, num, tos, start; + u32 shift = 64 - boot_cpu_data.x86_virt_bits; + + /* + * BRS event forced on PMC0, + * so check if there is an event. + * It is possible to have lbr_users > 0 but the event + * not yet scheduled due to long latency PMU irq + */ + if (!event) + goto empty; + + cfg.val = get_debug_extn_cfg(); + + /* Sanity check [0-x86_pmu.lbr_nr] */ + if (WARN_ON_ONCE(cfg.msroff >= x86_pmu.lbr_nr)) + goto empty; + + /* No valid branch */ + if (cfg.vb == 0) + goto empty; + + /* + * msr.off points to next entry to be written + * tos = most recent entry index = msr.off - 1 + * BRS register buffer saturates, so we know we have + * start < tos and that we have to read from start to tos + */ + start = 0; + tos = amd_brs_get_tos(&cfg); + + num = tos - start + 1; + + /* + * BRS is only one pass (saturation) from MSROFF to depth-1 + * MSROFF wraps to zero when buffer is full + */ + for (i = 0; i < num; i++) { + u32 brs_idx = tos - i; + u64 from, to; + + rdmsrl(brs_to(brs_idx), to); + + /* Entry does not belong to us (as marked by kernel) */ + if (to == BRS_POISON) + break; + + rdmsrl(brs_from(brs_idx), from); + + /* + * Sign-extend SAMP_BR_TO to 64 bits, bits 61-63 are reserved. + * Necessary to generate proper virtual addresses suitable for + * symbolization + */ + to = (u64)(((s64)to << shift) >> shift); + + perf_clear_branch_entry_bitfields(br+nr); + + br[nr].from = from; + br[nr].to = to; + + nr++; + } +empty: + /* Record number of sampled branches */ + cpuc->lbr_stack.nr = nr; +} + +/* + * Poison most recent entry to prevent reuse by next task + * required because BRS entry are not tagged by PID + */ +static void amd_brs_poison_buffer(void) +{ + union amd_debug_extn_cfg cfg; + unsigned int idx; + + /* Get current state */ + cfg.val = get_debug_extn_cfg(); + + /* idx is most recently written entry */ + idx = amd_brs_get_tos(&cfg); + + /* Poison target of entry */ + wrmsrl(brs_to(idx), BRS_POISON); +} + +/* + * On context switch in, we need to make sure no samples from previous user + * are left in the BRS. + * + * On ctxswin, sched_in = true, called after the PMU has started + * On ctxswout, sched_in = false, called before the PMU is stopped + */ +void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + + /* no active users */ + if (!cpuc->lbr_users) + return; + + /* + * On context switch in, we need to ensure we do not use entries + * from previous BRS user on that CPU, so we poison the buffer as + * a faster way compared to resetting all entries. + */ + if (sched_in) + amd_brs_poison_buffer(); +} diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 9687a8aef01c..44d8f618bb3e 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -327,6 +327,8 @@ static inline bool amd_is_pair_event_code(struct hw_perf_event *hwc) static int amd_core_hw_config(struct perf_event *event) { + int ret = 0; + if (event->attr.exclude_host && event->attr.exclude_guest) /* * When HO == GO == 1 the hardware treats that as GO == HO == 0 @@ -343,7 +345,32 @@ static int amd_core_hw_config(struct perf_event *event) if ((x86_pmu.flags & PMU_FL_PAIR) && amd_is_pair_event_code(&event->hw)) event->hw.flags |= PERF_X86_EVENT_PAIR; - return 0; + /* + * if branch stack is requested + */ + if (has_branch_stack(event) && is_sampling_event(event)) { + /* + * BRS implementation does not work with frequency mode + * reprogramming of the period. + */ + if (event->attr.freq) + return -EINVAL; + /* + * The kernel subtracts BRS depth from period, so it must be big enough + */ + if (event->attr.sample_period <= x86_pmu.lbr_nr) + return -EINVAL; + + /* + * Check if we can allow PERF_SAMPLE_BRANCH_STACK + */ + ret = amd_brs_setup_filter(event); + + /* only set in case of success */ + if (!ret) + event->hw.flags |= PERF_X86_EVENT_AMD_BRS; + } + return ret; } static inline int amd_is_nb_event(struct hw_perf_event *hwc) @@ -366,7 +393,7 @@ static int amd_pmu_hw_config(struct perf_event *event) if (event->attr.precise_ip && get_ibs_caps()) return -ENOENT; - if (has_branch_stack(event)) + if (has_branch_stack(event) && !x86_pmu.lbr_nr) return -EOPNOTSUPP; ret = x86_pmu_hw_config(event); @@ -555,6 +582,8 @@ static void amd_pmu_cpu_starting(int cpu) cpuc->amd_nb->nb_id = nb_id; cpuc->amd_nb->refcnt++; + + amd_brs_reset(); } static void amd_pmu_cpu_dead(int cpu) @@ -610,6 +639,8 @@ static void amd_pmu_disable_all(void) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); int idx; + amd_brs_disable_all(); + x86_pmu_disable_all(); /* @@ -634,6 +665,30 @@ static void amd_pmu_disable_all(void) } } +static void amd_pmu_enable_event(struct perf_event *event) +{ + x86_pmu_enable_event(event); +} + +static void amd_pmu_enable_all(int added) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + struct hw_perf_event *hwc; + int idx; + + amd_brs_enable_all(); + + for (idx = 0; idx < x86_pmu.num_counters; idx++) { + hwc = &cpuc->events[idx]->hw; + + /* only activate events which are marked as active */ + if (!test_bit(idx, cpuc->active_mask)) + continue; + + amd_pmu_enable_event(cpuc->events[idx]); + } +} + static void amd_pmu_disable_event(struct perf_event *event) { x86_pmu_disable_event(event); @@ -651,6 +706,18 @@ static void amd_pmu_disable_event(struct perf_event *event) amd_pmu_wait_on_overflow(event->hw.idx); } +static void amd_pmu_add_event(struct perf_event *event) +{ + if (needs_branch_stack(event)) + amd_pmu_brs_add(event); +} + +static void amd_pmu_del_event(struct perf_event *event) +{ + if (needs_branch_stack(event)) + amd_pmu_brs_del(event); +} + /* * Because of NMI latency, if multiple PMC counters are active or other sources * of NMIs are received, the perf NMI handler can handle one or more overflowed @@ -671,11 +738,31 @@ static void amd_pmu_disable_event(struct perf_event *event) */ static int amd_pmu_handle_irq(struct pt_regs *regs) { + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); int handled; + int pmu_enabled; + + /* + * Save the PMU state. + * It needs to be restored when leaving the handler. + */ + pmu_enabled = cpuc->enabled; + cpuc->enabled = 0; + + /* stop everything (includes BRS) */ + amd_pmu_disable_all(); + + /* Drain BRS is in use (could be inactive) */ + if (cpuc->lbr_users) + amd_brs_drain(); /* Process any counter overflows */ handled = x86_pmu_handle_irq(regs); + cpuc->enabled = pmu_enabled; + if (pmu_enabled) + amd_pmu_enable_all(0); + /* * If a counter was handled, record a timestamp such that un-handled * NMIs will be claimed if arriving within that window. @@ -897,6 +984,51 @@ static void amd_put_event_constraints_f17h(struct cpu_hw_events *cpuc, --cpuc->n_pair; } +/* + * Because of the way BRS operates with an inactive and active phases, and + * the link to one counter, it is not possible to have two events using BRS + * scheduled at the same time. There would be an issue with enforcing the + * period of each one and given that the BRS saturates, it would not be possible + * to guarantee correlated content for all events. Therefore, in situations + * where multiple events want to use BRS, the kernel enforces mutual exclusion. + * Exclusion is enforced by chosing only one counter for events using BRS. + * The event scheduling logic will then automatically multiplex the + * events and ensure that at most one event is actively using BRS. + * + * The BRS counter could be any counter, but there is no constraint on Fam19h, + * therefore all counters are equal and thus we pick the first one: PMC0 + */ +static struct event_constraint amd_fam19h_brs_cntr0_constraint = + EVENT_CONSTRAINT(0, 0x1, AMD64_RAW_EVENT_MASK); + +static struct event_constraint amd_fam19h_brs_pair_cntr0_constraint = + __EVENT_CONSTRAINT(0, 0x1, AMD64_RAW_EVENT_MASK, 1, 0, PERF_X86_EVENT_PAIR); + +static struct event_constraint * +amd_get_event_constraints_f19h(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + bool has_brs = has_amd_brs(hwc); + + /* + * In case BRS is used with an event requiring a counter pair, + * the kernel allows it but only on counter 0 & 1 to enforce + * multiplexing requiring to protect BRS in case of multiple + * BRS users + */ + if (amd_is_pair_event_code(hwc)) { + return has_brs ? &amd_fam19h_brs_pair_cntr0_constraint + : &pair_constraint; + } + + if (has_brs) + return &amd_fam19h_brs_cntr0_constraint; + + return &unconstrained; +} + + static ssize_t amd_event_sysfs_show(char *page, u64 config) { u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT) | @@ -905,12 +1037,19 @@ static ssize_t amd_event_sysfs_show(char *page, u64 config) return x86_event_sysfs_show(page, config, event); } +static void amd_pmu_sched_task(struct perf_event_context *ctx, + bool sched_in) +{ + if (sched_in && x86_pmu.lbr_nr) + amd_pmu_brs_sched_task(ctx, sched_in); +} + static __initconst const struct x86_pmu amd_pmu = { .name = "AMD", .handle_irq = amd_pmu_handle_irq, .disable_all = amd_pmu_disable_all, - .enable_all = x86_pmu_enable_all, - .enable = x86_pmu_enable_event, + .enable_all = amd_pmu_enable_all, + .enable = amd_pmu_enable_event, .disable = amd_pmu_disable_event, .hw_config = amd_pmu_hw_config, .schedule_events = x86_schedule_events, @@ -920,6 +1059,8 @@ static __initconst const struct x86_pmu amd_pmu = { .event_map = amd_pmu_event_map, .max_events = ARRAY_SIZE(amd_perfmon_event_map), .num_counters = AMD64_NUM_COUNTERS, + .add = amd_pmu_add_event, + .del = amd_pmu_del_event, .cntval_bits = 48, .cntval_mask = (1ULL << 48) - 1, .apic = 1, @@ -938,6 +1079,37 @@ static __initconst const struct x86_pmu amd_pmu = { .amd_nb_constraints = 1, }; +static ssize_t branches_show(struct device *cdev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr); +} + +static DEVICE_ATTR_RO(branches); + +static struct attribute *amd_pmu_brs_attrs[] = { + &dev_attr_branches.attr, + NULL, +}; + +static umode_t +amd_brs_is_visible(struct kobject *kobj, struct attribute *attr, int i) +{ + return x86_pmu.lbr_nr ? attr->mode : 0; +} + +static struct attribute_group group_caps_amd_brs = { + .name = "caps", + .attrs = amd_pmu_brs_attrs, + .is_visible = amd_brs_is_visible, +}; + +static const struct attribute_group *amd_attr_update[] = { + &group_caps_amd_brs, + NULL, +}; + static int __init amd_core_pmu_init(void) { u64 even_ctr_mask = 0ULL; @@ -989,6 +1161,23 @@ static int __init amd_core_pmu_init(void) x86_pmu.flags |= PMU_FL_PAIR; } + if (boot_cpu_data.x86 >= 0x19) { + /* + * On AMD, invoking pmu_disable_all() is very expensive and the function is + * invoked on context-switch in via sched_task_in(), so enable only when necessary + */ + if (!amd_brs_init()) { + x86_pmu.get_event_constraints = amd_get_event_constraints_f19h; + x86_pmu.sched_task = amd_pmu_sched_task; + /* + * The put_event_constraints callback is shared with + * Fam17h, set above + */ + } + } + + x86_pmu.attr_update = amd_attr_update; + pr_cont("core perfctr, "); return 0; } diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e686c5e0537b..c2a890caeb0a 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1338,6 +1338,10 @@ static void x86_pmu_enable(struct pmu *pmu) if (hwc->state & PERF_HES_ARCH) continue; + /* + * if cpuc->enabled = 0, then no wrmsr as + * per x86_pmu_enable_event() + */ x86_pmu_start(event, PERF_EF_RELOAD); } cpuc->n_added = 0; @@ -1704,11 +1708,15 @@ int x86_pmu_handle_irq(struct pt_regs *regs) * event overflow */ handled++; - perf_sample_data_init(&data, 0, event->hw.last_period); if (!x86_perf_event_set_period(event)) continue; + perf_sample_data_init(&data, 0, event->hw.last_period); + + if (has_branch_stack(event)) + data.br_stack = &cpuc->lbr_stack; + if (perf_event_overflow(event, &data, regs)) x86_pmu_stop(event, 0); } diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 150261d929b9..3485a4cf0241 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -67,22 +67,23 @@ static inline bool constraint_match(struct event_constraint *c, u64 ecode) /* * struct hw_perf_event.flags flags */ -#define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */ -#define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */ -#define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */ -#define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */ -#define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */ -#define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */ -#define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */ - -#define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */ -#define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */ -#define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */ -#define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */ -#define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */ -#define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */ -#define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */ -#define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */ +#define PERF_X86_EVENT_PEBS_LDLAT 0x00001 /* ld+ldlat data address sampling */ +#define PERF_X86_EVENT_PEBS_ST 0x00002 /* st data address sampling */ +#define PERF_X86_EVENT_PEBS_ST_HSW 0x00004 /* haswell style datala, store */ +#define PERF_X86_EVENT_PEBS_LD_HSW 0x00008 /* haswell style datala, load */ +#define PERF_X86_EVENT_PEBS_NA_HSW 0x00010 /* haswell style datala, unknown */ +#define PERF_X86_EVENT_EXCL 0x00020 /* HT exclusivity on counter */ +#define PERF_X86_EVENT_DYNAMIC 0x00040 /* dynamic alloc'd constraint */ + +#define PERF_X86_EVENT_EXCL_ACCT 0x00100 /* accounted EXCL event */ +#define PERF_X86_EVENT_AUTO_RELOAD 0x00200 /* use PEBS auto-reload */ +#define PERF_X86_EVENT_LARGE_PEBS 0x00400 /* use large PEBS */ +#define PERF_X86_EVENT_PEBS_VIA_PT 0x00800 /* use PT buffer for PEBS */ +#define PERF_X86_EVENT_PAIR 0x01000 /* Large Increment per Cycle */ +#define PERF_X86_EVENT_LBR_SELECT 0x02000 /* Save/Restore MSR_LBR_SELECT */ +#define PERF_X86_EVENT_TOPDOWN 0x04000 /* Count Topdown slots/metrics events */ +#define PERF_X86_EVENT_PEBS_STLAT 0x08000 /* st+stlat data address sampling */ +#define PERF_X86_EVENT_AMD_BRS 0x10000 /* AMD Branch Sampling */ static inline bool is_topdown_count(struct perf_event *event) { @@ -325,6 +326,8 @@ struct cpu_hw_events { * AMD specific bits */ struct amd_nb *amd_nb; + int brs_active; /* BRS is enabled */ + /* Inverted mask of bits to clear in the perf_ctr ctrl registers */ u64 perf_ctr_virt_mask; int n_pair; /* Large increment events */ @@ -1105,6 +1108,11 @@ int x86_pmu_hw_config(struct perf_event *event); void x86_pmu_disable_all(void); +static inline bool has_amd_brs(struct hw_perf_event *hwc) +{ + return hwc->flags & PERF_X86_EVENT_AMD_BRS; +} + static inline bool is_counter_pair(struct hw_perf_event *hwc) { return hwc->flags & PERF_X86_EVENT_PAIR; @@ -1210,6 +1218,50 @@ static inline bool fixed_counter_disabled(int i, struct pmu *pmu) #ifdef CONFIG_CPU_SUP_AMD int amd_pmu_init(void); +int amd_brs_init(void); +void amd_brs_disable(void); +void amd_brs_enable(void); +void amd_brs_enable_all(void); +void amd_brs_disable_all(void); +void amd_brs_drain(void); +void amd_brs_disable_all(void); +int amd_brs_setup_filter(struct perf_event *event); +void amd_brs_reset(void); + +static inline void amd_pmu_brs_add(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + + perf_sched_cb_inc(event->ctx->pmu); + cpuc->lbr_users++; + /* + * No need to reset BRS because it is reset + * on brs_enable() and it is saturating + */ +} + +static inline void amd_pmu_brs_del(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + + cpuc->lbr_users--; + WARN_ON_ONCE(cpuc->lbr_users < 0); + + perf_sched_cb_dec(event->ctx->pmu); +} + +void amd_pmu_brs_sched_task(struct perf_event_context *ctx, bool sched_in); + +/* + * check if BRS is activated on the CPU + * active defined as it has non-zero users and DBG_EXT_CFG.BRSEN=1 + */ +static inline bool amd_brs_active(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + + return cpuc->brs_active; +} #else /* CONFIG_CPU_SUP_AMD */ @@ -1218,6 +1270,23 @@ static inline int amd_pmu_init(void) return 0; } +static inline int amd_brs_init(void) +{ + return 0; +} + +static inline void amd_brs_drain(void) +{ +} + +static inline void amd_brs_enable_all(void) +{ +} + +static inline void amd_brs_disable_all(void) +{ +} + #endif /* CONFIG_CPU_SUP_AMD */ static inline int is_pebs_pt(struct perf_event *event) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3faf0f97edb1..d44bc769dd6f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -667,6 +667,10 @@ #define MSR_IA32_PERF_CTL 0x00000199 #define INTEL_PERF_CTL_MASK 0xffff +/* AMD Branch Sampling configuration */ +#define MSR_AMD_DBG_EXTN_CFG 0xc000010f +#define MSR_AMD_SAMP_BR_FROM 0xc0010300 + #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 -- 2.35.0.rc0.227.g00780c9af4-goog ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support 2022-01-26 23:34 ` [PATCH v5 03/13] perf/x86/amd: add " Stephane Eranian @ 2022-01-27 1:52 ` kernel test robot 2022-01-27 6:09 ` kernel test robot 1 sibling, 0 replies; 7+ messages in thread From: kernel test robot @ 2022-01-27 1:52 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 2481 bytes --] Hi Stephane, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20220125] [cannot apply to tip/x86/core rafael-pm/linux-next tip/perf/core v5.17-rc1 v5.16 v5.16-rc8 v5.17-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 base: d25ee88530253138d0b20d43511ca5acbda4e9f7 config: i386-buildonly-randconfig-r002-20220124 (https://download.01.org/0day-ci/archive/20220127/202201270923.FG90uMou-lkp(a)intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/933d072f6e0c0409115a8038a89a56979a042d30 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 git checkout 933d072f6e0c0409115a8038a89a56979a042d30 # save the config file to linux build tree mkdir build_dir make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash arch/x86/events/amd/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): arch/x86/events/amd/core.c: In function 'amd_pmu_enable_all': >> arch/x86/events/amd/core.c:676:24: warning: variable 'hwc' set but not used [-Wunused-but-set-variable] 676 | struct hw_perf_event *hwc; | ^~~ vim +/hwc +676 arch/x86/events/amd/core.c 672 673 static void amd_pmu_enable_all(int added) 674 { 675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > 676 struct hw_perf_event *hwc; 677 int idx; 678 679 amd_brs_enable_all(); 680 681 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 682 hwc = &cpuc->events[idx]->hw; 683 684 /* only activate events which are marked as active */ 685 if (!test_bit(idx, cpuc->active_mask)) 686 continue; 687 688 amd_pmu_enable_event(cpuc->events[idx]); 689 } 690 } 691 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support 2022-01-26 23:34 ` [PATCH v5 03/13] perf/x86/amd: add " Stephane Eranian @ 2022-01-27 6:09 ` kernel test robot 2022-01-27 6:09 ` kernel test robot 1 sibling, 0 replies; 7+ messages in thread From: kernel test robot @ 2022-01-27 6:09 UTC (permalink / raw) To: Stephane Eranian; +Cc: llvm, kbuild-all Hi Stephane, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20220125] [cannot apply to tip/x86/core rafael-pm/linux-next tip/perf/core v5.17-rc1 v5.16 v5.16-rc8 v5.17-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 base: d25ee88530253138d0b20d43511ca5acbda4e9f7 config: i386-randconfig-a011-20220124 (https://download.01.org/0day-ci/archive/20220127/202201271410.cro07bYq-lkp@intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f400a6012c668dfaa73462caf067ceb074e66c47) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/933d072f6e0c0409115a8038a89a56979a042d30 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 git checkout 933d072f6e0c0409115a8038a89a56979a042d30 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash arch/x86/events/amd/ drivers/acpi/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> arch/x86/events/amd/core.c:676:24: warning: variable 'hwc' set but not used [-Wunused-but-set-variable] struct hw_perf_event *hwc; ^ 1 warning generated. vim +/hwc +676 arch/x86/events/amd/core.c 672 673 static void amd_pmu_enable_all(int added) 674 { 675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > 676 struct hw_perf_event *hwc; 677 int idx; 678 679 amd_brs_enable_all(); 680 681 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 682 hwc = &cpuc->events[idx]->hw; 683 684 /* only activate events which are marked as active */ 685 if (!test_bit(idx, cpuc->active_mask)) 686 continue; 687 688 amd_pmu_enable_event(cpuc->events[idx]); 689 } 690 } 691 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support @ 2022-01-27 6:09 ` kernel test robot 0 siblings, 0 replies; 7+ messages in thread From: kernel test robot @ 2022-01-27 6:09 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 2707 bytes --] Hi Stephane, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20220125] [cannot apply to tip/x86/core rafael-pm/linux-next tip/perf/core v5.17-rc1 v5.16 v5.16-rc8 v5.17-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 base: d25ee88530253138d0b20d43511ca5acbda4e9f7 config: i386-randconfig-a011-20220124 (https://download.01.org/0day-ci/archive/20220127/202201271410.cro07bYq-lkp(a)intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f400a6012c668dfaa73462caf067ceb074e66c47) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/933d072f6e0c0409115a8038a89a56979a042d30 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Stephane-Eranian/perf-core-add-perf_clear_branch_entry_bitfields-helper/20220127-083516 git checkout 933d072f6e0c0409115a8038a89a56979a042d30 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash arch/x86/events/amd/ drivers/acpi/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> arch/x86/events/amd/core.c:676:24: warning: variable 'hwc' set but not used [-Wunused-but-set-variable] struct hw_perf_event *hwc; ^ 1 warning generated. vim +/hwc +676 arch/x86/events/amd/core.c 672 673 static void amd_pmu_enable_all(int added) 674 { 675 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > 676 struct hw_perf_event *hwc; 677 int idx; 678 679 amd_brs_enable_all(); 680 681 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 682 hwc = &cpuc->events[idx]->hw; 683 684 /* only activate events which are marked as active */ 685 if (!test_bit(idx, cpuc->active_mask)) 686 continue; 687 688 amd_pmu_enable_event(cpuc->events[idx]); 689 } 690 } 691 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-01-30 2:34 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-28 8:35 [PATCH v5 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support kernel test robot 2022-01-30 2:33 ` kernel test robot 2022-01-30 2:33 ` kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2022-01-26 23:34 [PATCH v5 00/14] perf/x86/amd: Add " Stephane Eranian 2022-01-26 23:34 ` [PATCH v5 03/13] perf/x86/amd: add " Stephane Eranian 2022-01-27 1:52 ` kernel test robot 2022-01-27 6:09 ` kernel test robot 2022-01-27 6:09 ` kernel test robot
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