* [PATCH 01/11] target/ppc: Merge exception model IDs for 6xx CPUs
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 02/11] target/ppc: Introduce powerpc_excp_6xx Fabiano Rosas
` (11 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
We don't need three separate exception model IDs for the 603, 604 and
G2.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/cpu-qom.h | 8 ++------
target/ppc/cpu_init.c | 18 +++++++++---------
target/ppc/excp_helper.c | 5 ++---
3 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 5d591ff6c5..3880fb3337 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -88,12 +88,8 @@ enum powerpc_excp_t {
POWERPC_EXCP_STD,
/* PowerPC 40x exception model */
POWERPC_EXCP_40x,
- /* PowerPC 603 exception model */
- POWERPC_EXCP_603,
- /* PowerPC G2 exception model */
- POWERPC_EXCP_G2,
- /* PowerPC 604 exception model */
- POWERPC_EXCP_604,
+ /* PowerPC 603/604/G2 exception model */
+ POWERPC_EXCP_6xx,
/* PowerPC 7x0 exception model */
POWERPC_EXCP_7x0,
/* PowerPC 7x5 exception model */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index a5e1f5a3b2..95c5831ba6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2782,7 +2782,7 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_REAL;
- pcc->excp_model = POWERPC_EXCP_603;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
pcc->bfd_mach = bfd_mach_ppc_505;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -2825,7 +2825,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_MPC8xx;
- pcc->excp_model = POWERPC_EXCP_603;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
pcc->bfd_mach = bfd_mach_ppc_860;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -2906,7 +2906,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
(1ull << MSR_DR) |
(1ull << MSR_RI);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_G2;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_ec603e;
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
@@ -2988,7 +2988,7 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_G2;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_ec603e;
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
@@ -3243,7 +3243,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_603;
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
@@ -3772,7 +3772,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_603;
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
@@ -3811,7 +3811,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_603;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_ec603e;
pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
@@ -3872,7 +3872,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_604;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_604;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
@@ -3953,7 +3953,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
(1ull << MSR_RI) |
(1ull << MSR_LE);
pcc->mmu_model = POWERPC_MMU_32B;
- pcc->excp_model = POWERPC_EXCP_604;
+ pcc->excp_model = POWERPC_EXCP_6xx;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_604;
pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index ae6871a3c0..935f547f25 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1357,7 +1357,7 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
srr0 = SPR_BOOKE_CSRR0;
srr1 = SPR_BOOKE_CSRR1;
break;
- case POWERPC_EXCP_G2:
+ case POWERPC_EXCP_6xx:
break;
default:
goto excp_invalid;
@@ -1645,8 +1645,7 @@ static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
switch (excp_model) {
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_G2:
+ case POWERPC_EXCP_6xx:
/* Swap temporary saved registers with GPRs */
if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
new_msr |= (target_ulong)1 << MSR_TGPR;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 02/11] target/ppc: Introduce powerpc_excp_6xx
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
2022-02-03 20:09 ` [PATCH 01/11] target/ppc: Merge exception model IDs for 6xx CPUs Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 03/11] target/ppc: Simplify powerpc_excp_6xx Fabiano Rosas
` (10 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Introduce a new powerpc_excp function specific for PowerPC 6xx CPUs
(603, 604, G2, MPC5xx, MCP8xx). This commit copies powerpc_excp_legacy
verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 469 +++++++++++++++++++++++++++++++++++++++
1 file changed, 469 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 935f547f25..daa11e7368 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -549,6 +549,472 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ int excp_model = env->excp_model;
+ target_ulong msr, new_msr, vector;
+ int srr0, srr1, lev = -1;
+
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
+ /* new srr1 value excluding must-be-zero bits */
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr = env->msr;
+ } else {
+ msr = env->msr & ~0x783f0000ULL;
+ }
+
+ /*
+ * new interrupt handler msr preserves existing HV and ME unless
+ * explicitly overriden
+ */
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+ /* target registers */
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
+ if (env->resume_as_sreset) {
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+ }
+
+ /*
+ * Hypervisor emulation assistance interrupt only exists on server
+ * arch 2.05 server or later. We also don't want to generate it if
+ * we don't have HVB in msr_mask (PAPR mode).
+ */
+ if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+ && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+ ) {
+ excp = POWERPC_EXCP_PROGRAM;
+ }
+
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1ULL) {
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+
+ vector |= env->excp_prefix;
+
+ switch (excp) {
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_6xx:
+ break;
+ default:
+ goto excp_invalid;
+ }
+ break;
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
+ if (msr_me == 0) {
+ /*
+ * Machine check exception is not enabled. Enter
+ * checkstop state.
+ */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+
+ /* machine check exceptions don't have ME set */
+ new_msr &= ~((target_ulong)1 << MSR_ME);
+
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ break;
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
+ trace_ppc_excp_isi(msr, env->nip);
+ msr |= env->error_code;
+ break;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
+ cs = CPU(cpu);
+
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
+ if (!lpes0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ }
+ if (env->mpic_proxy) {
+ /* IACK the IRQ on delivery */
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ }
+ break;
+ }
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ break;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
+ switch (env->error_code & ~0xF) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ trace_ppc_excp_fp_ignore();
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ return;
+ }
+
+ /*
+ * FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
+ msr |= 0x00100000;
+ env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ break;
+ case POWERPC_EXCP_INVAL:
+ trace_ppc_excp_inval(env->nip);
+ msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ break;
+ default:
+ /* Should never occur */
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ lev = env->error_code;
+
+ if ((lev == 1) && cpu->vhyp) {
+ dump_hcall(env);
+ } else {
+ dump_syscall(env);
+ }
+
+ /*
+ * We need to correct the NIP which in this case is supposed
+ * to point to the next instruction
+ */
+ env->nip += 4;
+
+ /* "PAPR mode" built-in hypercall emulation */
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
+ return;
+ }
+ if (lev == 1) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
+ lev = env->error_code;
+ dump_syscall(env);
+ env->nip += 4;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+ vector += lev * 0x20;
+
+ env->lr = env->nip;
+ env->ctr = msr;
+ break;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ break;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+ trace_ppc_excp_print("FIT");
+ break;
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
+ trace_ppc_excp_print("WDT");
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ if (env->flags & POWERPC_FLAG_DE) {
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
+ /* DBSR already modified by caller */
+ } else {
+ cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ }
+ break;
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+ break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
+ if (msr_pow) {
+ /* indicate that we resumed from power save mode */
+ msr |= 0x10000;
+ new_msr |= ((target_ulong)1 << MSR_ME);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ } else {
+ if (msr_pow) {
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
+ }
+ }
+ break;
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ break;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ msr |= env->error_code;
+ /* fall through */
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
+ case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ break;
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+ break;
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+ break;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
+ trace_ppc_excp_print("PIT");
+ break;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ switch (excp_model) {
+ case POWERPC_EXCP_6xx:
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
+ }
+ /* fall through */
+ case POWERPC_EXCP_7x5:
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(cs, "Invalid TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
+ default:
+ excp_invalid:
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
+ }
+
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB)) {
+ if (new_msr & MSR_HVB) {
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+ "no HV support\n", excp);
+ }
+ if (srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+ }
+
+ /*
+ * Sort out endianness of interrupt, this differs depending on the
+ * CPU, the HV mode, etc...
+ */
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
+ } else {
+ vector = (uint32_t)vector;
+ }
+ } else {
+ if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+ vector = (uint32_t)vector;
+ } else {
+ new_msr |= (target_ulong)1 << MSR_SF;
+ }
+ }
+#endif
+
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+ /* Save PC */
+ env->spr[srr0] = env->nip;
+
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
@@ -1747,6 +2213,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_40x:
powerpc_excp_40x(cpu, excp);
break;
+ case POWERPC_EXCP_6xx:
+ powerpc_excp_6xx(cpu, excp);
+ break;
case POWERPC_EXCP_74xx:
powerpc_excp_74xx(cpu, excp);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 03/11] target/ppc: Simplify powerpc_excp_6xx
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
2022-02-03 20:09 ` [PATCH 01/11] target/ppc: Merge exception model IDs for 6xx CPUs Fabiano Rosas
2022-02-03 20:09 ` [PATCH 02/11] target/ppc: Introduce powerpc_excp_6xx Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup Fabiano Rosas
` (9 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_CRITICAL
POWERPC_EXCP_DABR
POWERPC_EXCP_DECR
POWERPC_EXCP_DLTLB
POWERPC_EXCP_DSI
POWERPC_EXCP_DSTLB
POWERPC_EXCP_DTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPA
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_IFTLB
POWERPC_EXCP_ISI
POWERPC_EXCP_ITLB
POWERPC_EXCP_MCHECK
POWERPC_EXCP_MEXTBR
POWERPC_EXCP_NMEXTBR
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 163 +++------------------------------------
1 file changed, 9 insertions(+), 154 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index daa11e7368..d855a275ca 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -566,54 +566,26 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
+ * new interrupt handler msr preserves existing ME unless
* explicitly overriden
*/
- new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- /*
- * check for special resume at 0x100 from doze/nap/sleep/winkle on
- * P7/P8/P9
- */
- if (env->resume_as_sreset) {
- excp = powerpc_reset_wakeup(cs, env, excp, &msr);
- }
-
/*
* Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * arch 2.05 server or later.
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -802,63 +774,12 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
break;
- case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
- lev = env->error_code;
- dump_syscall(env);
- env->nip += 4;
- new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
- vector += lev * 0x20;
-
- env->lr = env->nip;
- env->ctr = msr;
- break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
- break;
case POWERPC_EXCP_DTLB: /* Data TLB error */
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
@@ -879,44 +800,8 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
}
}
break;
- case POWERPC_EXCP_DSEG: /* Data segment exception */
- case POWERPC_EXCP_ISEG: /* Instruction segment exception */
case POWERPC_EXCP_TRACE: /* Trace exception */
break;
- case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
- msr |= env->error_code;
- /* fall through */
- case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
- case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
- case POWERPC_EXCP_HV_EMU:
- case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- break;
- case POWERPC_EXCP_VPU: /* Vector unavailable exception */
- case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
- case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
- break;
- case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
@@ -941,18 +826,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
}
break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_FPA: /* Floating-point assist exception */
case POWERPC_EXCP_DABR: /* Data address breakpoint */
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
- case POWERPC_EXCP_THERM: /* Thermal interrupt */
- case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- case POWERPC_EXCP_MAINT: /* Maintenance exception */
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
cpu_abort(cs, "%s exception not implemented\n",
@@ -984,33 +861,11 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)1 << MSR_LE;
}
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
+ /* Save PC */
+ env->spr[srr0] = env->nip;
- if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
- env->spr[srr0] = env->nip;
-
- /* Save MSR */
- env->spr[srr1] = msr;
- }
-
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+ /* Save MSR */
+ env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (2 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 03/11] target/ppc: Simplify powerpc_excp_6xx Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-04 12:43 ` BALATON Zoltan
2022-02-03 20:09 ` [PATCH 05/11] target/ppc: 6xx: Machine Check " Fabiano Rosas
` (8 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This only applies to the G2s, the other 6xx CPUs will not have this
vector registered.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d855a275ca..e27e1c3c70 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -596,20 +596,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_6xx:
- break;
- default:
- goto excp_invalid;
- }
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
@@ -836,7 +822,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
powerpc_excp_name(excp));
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup
2022-02-03 20:09 ` [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup Fabiano Rosas
@ 2022-02-04 12:43 ` BALATON Zoltan
2022-02-04 15:42 ` Fabiano Rosas
0 siblings, 1 reply; 20+ messages in thread
From: BALATON Zoltan @ 2022-02-04 12:43 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david, clg
On Thu, 3 Feb 2022, Fabiano Rosas wrote:
> This only applies to the G2s, the other 6xx CPUs will not have this
> vector registered.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 15 ---------------
> 1 file changed, 15 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index d855a275ca..e27e1c3c70 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -596,20 +596,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>
> switch (excp) {
> case POWERPC_EXCP_CRITICAL: /* Critical input */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_6xx:
> - break;
> - default:
> - goto excp_invalid;
It may not be a problem but this seems to change previous behaviour. To
keep that you may need to test for G2 here, or rather move this whole case
before the default case to avoid goto and be able to just fall through to
invalid if CPU is not a G2 (unless we're Ok with an if the default case).
Regards,
BALATON Zoltan
> - }
> break;
> case POWERPC_EXCP_MCHECK: /* Machine check exception */
> if (msr_me == 0) {
> @@ -836,7 +822,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> powerpc_excp_name(excp));
> break;
> default:
> - excp_invalid:
> cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> break;
> }
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup
2022-02-04 12:43 ` BALATON Zoltan
@ 2022-02-04 15:42 ` Fabiano Rosas
0 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-04 15:42 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: clg, danielhb413, qemu-ppc, qemu-devel, david
BALATON Zoltan <balaton@eik.bme.hu> writes:
> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>> This only applies to the G2s, the other 6xx CPUs will not have this
>> vector registered.
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 15 ---------------
>> 1 file changed, 15 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index d855a275ca..e27e1c3c70 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -596,20 +596,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>>
>> switch (excp) {
>> case POWERPC_EXCP_CRITICAL: /* Critical input */
>> - switch (excp_model) {
>> - case POWERPC_EXCP_40x:
>> - srr0 = SPR_40x_SRR2;
>> - srr1 = SPR_40x_SRR3;
>> - break;
>> - case POWERPC_EXCP_BOOKE:
>> - srr0 = SPR_BOOKE_CSRR0;
>> - srr1 = SPR_BOOKE_CSRR1;
>> - break;
>> - case POWERPC_EXCP_6xx:
>> - break;
>> - default:
>> - goto excp_invalid;
>
> It may not be a problem but this seems to change previous behaviour. To
> keep that you may need to test for G2 here, or rather move this whole case
> before the default case to avoid goto and be able to just fall through to
> invalid if CPU is not a G2 (unless we're Ok with an if the default case).
I should have been more explicit in the commit message, but that is on
purpose. If another 6xx CPU incorrectly registers the CRITICAL
exception, then we'll let it crash. This code needs to assume the work
done in cpu_init is correct. Otherwise we'd have to check everything
twice.
This whole exception work is walking towards removing the POWERPC_EXCP
identifiers because we have been misusing them as a way to identify
individual CPUs.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 05/11] target/ppc: 6xx: Machine Check exception cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (3 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 04/11] target/ppc: 6xx: Critical exception cleanup Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 06/11] target/ppc: 6xx: External interrupt cleanup Fabiano Rosas
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no MSR_HV in the 6xx CPUs.
Also remove the 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e27e1c3c70..734170d4c2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -612,34 +612,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
cs->halted = 1;
cpu_interrupt_exittb(cs);
}
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR).
- */
- new_msr |= (target_ulong)MSR_HVB;
- }
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 06/11] target/ppc: 6xx: External interrupt cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (4 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 05/11] target/ppc: 6xx: Machine Check " Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 07/11] target/ppc: 6xx: Program exception cleanup Fabiano Rosas
` (6 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no Hypervisor mode in the 6xx, so remove all LPES0 logic.
Also remove BookE IRQ code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 734170d4c2..a008115e5f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -625,44 +625,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 07/11] target/ppc: 6xx: Program exception cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (5 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 06/11] target/ppc: 6xx: External interrupt cleanup Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 08/11] target/ppc: 6xx: System Call " Fabiano Rosas
` (5 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no ESR in the 6xx CPUs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a008115e5f..a195288dda 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -651,20 +651,16 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
* precise in the MSR.
*/
msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
break;
case POWERPC_EXCP_TRAP:
msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break;
default:
/* Should never occur */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 08/11] target/ppc: 6xx: System Call exception cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (6 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 07/11] target/ppc: 6xx: Program exception cleanup Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 09/11] target/ppc: 6xx: System Reset interrupt cleanup Fabiano Rosas
` (4 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no Hypervisor mode in the 6xx CPUs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a195288dda..28d9a9a887 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -555,7 +555,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -670,30 +670,13 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
}
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
- lev = env->error_code;
-
- if ((lev == 1) && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
+ dump_syscall(env);
/*
* We need to correct the NIP which in this case is supposed
* to point to the next instruction
*/
env->nip += 4;
-
- /* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->hypercall(cpu->vhyp, cpu);
- return;
- }
- if (lev == 1) {
- new_msr |= (target_ulong)MSR_HVB;
- }
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_DECR: /* Decrementer exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 09/11] target/ppc: 6xx: System Reset interrupt cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (7 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 08/11] target/ppc: 6xx: System Call " Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-03 20:09 ` [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup Fabiano Rosas
` (3 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no HV support in the 6xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 28d9a9a887..538905c4dd 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -685,23 +685,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- /* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
- /* indicate that we resumed from power save mode */
- msr |= 0x10000;
- new_msr |= ((target_ulong)1 << MSR_ME);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
- */
- new_msr |= (target_ulong)MSR_HVB;
- } else {
- if (msr_pow) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
- }
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (8 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 09/11] target/ppc: 6xx: System Reset interrupt cleanup Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-04 12:51 ` BALATON Zoltan
2022-02-03 20:09 ` [PATCH 11/11] target/ppc: 6xx: Set SRRs directly in exception code Fabiano Rosas
` (2 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
This code applies only to the 6xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 31 +++++++++++--------------------
1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 538905c4dd..80168355bd 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_6xx:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
}
+
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
break;
case POWERPC_EXCP_FPA: /* Floating-point assist exception */
case POWERPC_EXCP_DABR: /* Data address breakpoint */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup
2022-02-03 20:09 ` [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup Fabiano Rosas
@ 2022-02-04 12:51 ` BALATON Zoltan
2022-02-04 15:46 ` Fabiano Rosas
0 siblings, 1 reply; 20+ messages in thread
From: BALATON Zoltan @ 2022-02-04 12:51 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david, clg
On Thu, 3 Feb 2022, Fabiano Rosas wrote:
> This code applies only to the 6xx CPUs, so we can remove the switch
> statement.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 31 +++++++++++--------------------
> 1 file changed, 11 insertions(+), 20 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 538905c4dd..80168355bd 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> {
> CPUState *cs = CPU(cpu);
> CPUPPCState *env = &cpu->env;
> - int excp_model = env->excp_model;
> target_ulong msr, new_msr, vector;
> int srr0, srr1;
>
> @@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> - switch (excp_model) {
> - case POWERPC_EXCP_6xx:
> - /* Swap temporary saved registers with GPRs */
> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> - new_msr |= (target_ulong)1 << MSR_TGPR;
> - hreg_swap_gpr_tgpr(env);
> - }
> - /* fall through */
> - case POWERPC_EXCP_7x5:
> - ppc_excp_debug_sw_tlb(env, excp);
> -
> - msr |= env->crf[0] << 28;
> - msr |= env->error_code; /* key, D/I, S/L bits */
> - /* Set way using a LRU mechanism */
> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> - break;
> - default:
> - cpu_abort(cs, "Invalid TLB miss exception\n");
> - break;
> + /* Swap temporary saved registers with GPRs */
> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> + new_msr |= (target_ulong)1 << MSR_TGPR;
> + hreg_swap_gpr_tgpr(env);
I get this one...
> }
> +
> + ppc_excp_debug_sw_tlb(env, excp);
> +
> + msr |= env->crf[0] << 28;
> + msr |= env->error_code; /* key, D/I, S/L bits */
> + /* Set way using a LRU mechanism */
> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
...but not why this can be moved out from case or if. Is POWERPC_EXCP_7x5
the same as POWERPC_EXCP_6xx now?
Regards,
BALATON Zoltan
> break;
> case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> case POWERPC_EXCP_DABR: /* Data address breakpoint */
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup
2022-02-04 12:51 ` BALATON Zoltan
@ 2022-02-04 15:46 ` Fabiano Rosas
2022-02-04 16:36 ` BALATON Zoltan
0 siblings, 1 reply; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-04 15:46 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: clg, danielhb413, qemu-ppc, qemu-devel, david
BALATON Zoltan <balaton@eik.bme.hu> writes:
> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>> This code applies only to the 6xx CPUs, so we can remove the switch
>> statement.
>>
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 31 +++++++++++--------------------
>> 1 file changed, 11 insertions(+), 20 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 538905c4dd..80168355bd 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>> {
>> CPUState *cs = CPU(cpu);
>> CPUPPCState *env = &cpu->env;
>> - int excp_model = env->excp_model;
>> target_ulong msr, new_msr, vector;
>> int srr0, srr1;
>>
>> @@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
>> case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
>> case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
>> - switch (excp_model) {
>> - case POWERPC_EXCP_6xx:
>> - /* Swap temporary saved registers with GPRs */
>> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
>> - new_msr |= (target_ulong)1 << MSR_TGPR;
>> - hreg_swap_gpr_tgpr(env);
>> - }
>> - /* fall through */
>> - case POWERPC_EXCP_7x5:
>> - ppc_excp_debug_sw_tlb(env, excp);
>> -
>> - msr |= env->crf[0] << 28;
>> - msr |= env->error_code; /* key, D/I, S/L bits */
>> - /* Set way using a LRU mechanism */
>> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
>> - break;
>> - default:
>> - cpu_abort(cs, "Invalid TLB miss exception\n");
>> - break;
>> + /* Swap temporary saved registers with GPRs */
>> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
>> + new_msr |= (target_ulong)1 << MSR_TGPR;
>> + hreg_swap_gpr_tgpr(env);
>
> I get this one...
>
>> }
>> +
>> + ppc_excp_debug_sw_tlb(env, excp);
>> +
>> + msr |= env->crf[0] << 28;
>> + msr |= env->error_code; /* key, D/I, S/L bits */
>> + /* Set way using a LRU mechanism */
>> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
>
> ...but not why this can be moved out from case or if. Is POWERPC_EXCP_7x5
> the same as POWERPC_EXCP_6xx now?
There is a fallthrough in the original code after the first block. So
POWERPC_EXCP_6xx does the TGPR work and then falls through to the debug
print and SRR1 setting.
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup
2022-02-04 15:46 ` Fabiano Rosas
@ 2022-02-04 16:36 ` BALATON Zoltan
0 siblings, 0 replies; 20+ messages in thread
From: BALATON Zoltan @ 2022-02-04 16:36 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, clg, david, qemu-devel
On Fri, 4 Feb 2022, Fabiano Rosas wrote:
> BALATON Zoltan <balaton@eik.bme.hu> writes:
>> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>>> This code applies only to the 6xx CPUs, so we can remove the switch
>>> statement.
>>>
>>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>>> ---
>>> target/ppc/excp_helper.c | 31 +++++++++++--------------------
>>> 1 file changed, 11 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>>> index 538905c4dd..80168355bd 100644
>>> --- a/target/ppc/excp_helper.c
>>> +++ b/target/ppc/excp_helper.c
>>> @@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>>> {
>>> CPUState *cs = CPU(cpu);
>>> CPUPPCState *env = &cpu->env;
>>> - int excp_model = env->excp_model;
>>> target_ulong msr, new_msr, vector;
>>> int srr0, srr1;
>>>
>>> @@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>>> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
>>> case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
>>> case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
>>> - switch (excp_model) {
>>> - case POWERPC_EXCP_6xx:
>>> - /* Swap temporary saved registers with GPRs */
>>> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
>>> - new_msr |= (target_ulong)1 << MSR_TGPR;
>>> - hreg_swap_gpr_tgpr(env);
>>> - }
>>> - /* fall through */
>>> - case POWERPC_EXCP_7x5:
>>> - ppc_excp_debug_sw_tlb(env, excp);
>>> -
>>> - msr |= env->crf[0] << 28;
>>> - msr |= env->error_code; /* key, D/I, S/L bits */
>>> - /* Set way using a LRU mechanism */
>>> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
>>> - break;
>>> - default:
>>> - cpu_abort(cs, "Invalid TLB miss exception\n");
>>> - break;
>>> + /* Swap temporary saved registers with GPRs */
>>> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
>>> + new_msr |= (target_ulong)1 << MSR_TGPR;
>>> + hreg_swap_gpr_tgpr(env);
>>
>> I get this one...
>>
>>> }
>>> +
>>> + ppc_excp_debug_sw_tlb(env, excp);
>>> +
>>> + msr |= env->crf[0] << 28;
>>> + msr |= env->error_code; /* key, D/I, S/L bits */
>>> + /* Set way using a LRU mechanism */
>>> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
>>
>> ...but not why this can be moved out from case or if. Is POWERPC_EXCP_7x5
>> the same as POWERPC_EXCP_6xx now?
>
> There is a fallthrough in the original code after the first block. So
> POWERPC_EXCP_6xx does the TGPR work and then falls through to the debug
> print and SRR1 setting.
Indeed, I've missed that.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 11/11] target/ppc: 6xx: Set SRRs directly in exception code
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (9 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 10/11] target/ppc: 6xx: Software TLB exceptions cleanup Fabiano Rosas
@ 2022-02-03 20:09 ` Fabiano Rosas
2022-02-04 6:42 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Cédric Le Goater
2022-02-09 7:44 ` Cédric Le Goater
12 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-03 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 80168355bd..7bdda6f165 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -554,7 +554,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -573,10 +572,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
*/
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* Hypervisor emulation assistance interrupt only exists on server
* arch 2.05 server or later.
@@ -727,10 +722,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
"no HV support\n", excp);
}
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
}
/*
@@ -742,10 +733,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
}
/* Save PC */
- env->spr[srr0] = env->nip;
+ env->spr[SPR_SRR0] = env->nip;
/* Save MSR */
- env->spr[srr1] = msr;
+ env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n)
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (10 preceding siblings ...)
2022-02-03 20:09 ` [PATCH 11/11] target/ppc: 6xx: Set SRRs directly in exception code Fabiano Rosas
@ 2022-02-04 6:42 ` Cédric Le Goater
2022-02-04 15:50 ` Fabiano Rosas
2022-02-09 7:44 ` Cédric Le Goater
12 siblings, 1 reply; 20+ messages in thread
From: Cédric Le Goater @ 2022-02-04 6:42 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 2/3/22 21:09, Fabiano Rosas wrote:
> This series handles the 6xx family: 603, 604, G2, G2LE,
What about the e300 ? I guess it's only a 603 variant for QEMU.
> MPC5xx and MPC8xx.
These are linux-user only, no MMU. I wonder if we shouldn't simply
drop support. At least we could remove POWERPC_MMU_MPC8xx.
C.
> There is a patch upfront to move them all into the same
> POWERPC_EXCP_6xx, but otherwise the rest of the series is pretty much
> the same as I have done for the other CPUs.
>
> This was tested with the 604 only. But I'm not too worried because
> these 32 bit CPUs are quite similar to one another.
>
> Fabiano Rosas (11):
> target/ppc: Merge exception model IDs for 6xx CPUs
> target/ppc: Introduce powerpc_excp_6xx
> target/ppc: Simplify powerpc_excp_6xx
> target/ppc: 6xx: Critical exception cleanup
> target/ppc: 6xx: Machine Check exception cleanup
> target/ppc: 6xx: External interrupt cleanup
> target/ppc: 6xx: Program exception cleanup
> target/ppc: 6xx: System Call exception cleanup
> target/ppc: 6xx: System Reset interrupt cleanup
> target/ppc: 6xx: Software TLB exceptions cleanup
> target/ppc: 6xx: Set SRRs directly in exception code
>
> target/ppc/cpu-qom.h | 8 +-
> target/ppc/cpu_init.c | 18 ++--
> target/ppc/excp_helper.c | 200 ++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 208 insertions(+), 18 deletions(-)
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n)
2022-02-04 6:42 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Cédric Le Goater
@ 2022-02-04 15:50 ` Fabiano Rosas
0 siblings, 0 replies; 20+ messages in thread
From: Fabiano Rosas @ 2022-02-04 15:50 UTC (permalink / raw)
To: Cédric Le Goater, qemu-devel; +Cc: danielhb413, qemu-ppc, david
Cédric Le Goater <clg@kaod.org> writes:
> On 2/3/22 21:09, Fabiano Rosas wrote:
>
>> This series handles the 6xx family: 603, 604, G2, G2LE,
>
> What about the e300 ? I guess it's only a 603 variant for QEMU.
I forgot to mention.
>> MPC5xx and MPC8xx.
>
> These are linux-user only, no MMU. I wonder if we shouldn't simply
> drop support. At least we could remove POWERPC_MMU_MPC8xx.
I know nothing about linux-user use cases, sorry. We have other CPUs
that are linux-user only, though. And there's this TODO_USER_ONLY mess
in cpu-models as well. We could probably tackle all of it at once.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n)
2022-02-03 20:09 [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Fabiano Rosas
` (11 preceding siblings ...)
2022-02-04 6:42 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [6xx] (7/n) Cédric Le Goater
@ 2022-02-09 7:44 ` Cédric Le Goater
12 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2022-02-09 7:44 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 2/3/22 21:09, Fabiano Rosas wrote:
> This series handles the 6xx family: 603, 604, G2, G2LE, MPC5xx and
> MPC8xx.
>
> There is a patch upfront to move them all into the same
> POWERPC_EXCP_6xx, but otherwise the rest of the series is pretty much
> the same as I have done for the other CPUs.
>
> This was tested with the 604 only. But I'm not too worried because
> these 32 bit CPUs are quite similar to one another.
>
> Fabiano Rosas (11):
> target/ppc: Merge exception model IDs for 6xx CPUs
> target/ppc: Introduce powerpc_excp_6xx
> target/ppc: Simplify powerpc_excp_6xx
> target/ppc: 6xx: Critical exception cleanup
> target/ppc: 6xx: Machine Check exception cleanup
> target/ppc: 6xx: External interrupt cleanup
> target/ppc: 6xx: Program exception cleanup
> target/ppc: 6xx: System Call exception cleanup
> target/ppc: 6xx: System Reset interrupt cleanup
> target/ppc: 6xx: Software TLB exceptions cleanup
> target/ppc: 6xx: Set SRRs directly in exception code
>
> target/ppc/cpu-qom.h | 8 +-
> target/ppc/cpu_init.c | 18 ++--
> target/ppc/excp_helper.c | 200 ++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 208 insertions(+), 18 deletions(-)
>
Applied to ppc-7.0.
Thanks,
C.
^ permalink raw reply [flat|nested] 20+ messages in thread