From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org,
david@gibson.dropbear.id.au
Subject: [PATCH 09/10] target/ppc: 7xx: Software TLB cleanup
Date: Thu, 3 Feb 2022 19:42:45 -0300 [thread overview]
Message-ID: <20220203224246.1446652-10-farosas@linux.ibm.com> (raw)
In-Reply-To: <20220203224246.1446652-1-farosas@linux.ibm.com>
This code applies only to the 7xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 26 ++++++--------------------
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f29f2ecefb..3872f3b7ad 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -745,7 +745,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -882,26 +881,13 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_6xx:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7xx:
- ppc_excp_debug_sw_tlb(env, excp);
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
--
2.34.1
next prev parent reply other threads:[~2022-02-03 23:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
2022-02-03 22:42 ` [PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs Fabiano Rosas
2022-02-03 22:42 ` [PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx Fabiano Rosas
2022-02-03 22:42 ` [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx Fabiano Rosas
2022-02-04 13:05 ` BALATON Zoltan
2022-02-04 16:10 ` Fabiano Rosas
2022-02-04 16:42 ` BALATON Zoltan
2022-02-03 22:42 ` [PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 05/10] target/ppc: 7xx: External interrupt cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 06/10] target/ppc: 7xx: Program exception cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 07/10] target/ppc: 7xx: System Call " Fabiano Rosas
2022-02-03 22:42 ` [PATCH 08/10] target/ppc: 7xx: System Reset cleanup Fabiano Rosas
2022-02-03 22:42 ` Fabiano Rosas [this message]
2022-02-03 22:42 ` [PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code Fabiano Rosas
2022-02-04 8:00 ` [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Cédric Le Goater
2022-02-04 16:13 ` Fabiano Rosas
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