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From: BALATON Zoltan <balaton@eik.bme.hu>
To: Fabiano Rosas <farosas@linux.ibm.com>
Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org,
	david@gibson.dropbear.id.au, qemu-devel@nongnu.org
Subject: Re: [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx
Date: Fri, 4 Feb 2022 17:42:29 +0100 (CET)	[thread overview]
Message-ID: <33ad21b4-8b80-151e-eb43-2d497d5fe66@eik.bme.hu> (raw)
In-Reply-To: <87o83m8ve9.fsf@linux.ibm.com>

On Fri, 4 Feb 2022, Fabiano Rosas wrote:
> BALATON Zoltan <balaton@eik.bme.hu> writes:
>> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>>> Differences from the generic powerpc_excp code:
>>>
>>> - Not BookE, so some MSR bits are cleared at interrupt dispatch;
>>> - No MSR_HV;
>>> - No power saving states;
>>> - No Hypervisor Emulation Assistance;
>>
>> The pegasos2 can run with -cpu G3 as the real hardware had a processor
>> card either with a G3 or a G4 so this will break VOF with that. I'm not
>> sure if it's worth keeping support for this though as long as the default
>> G4 works because most people would want to use a G4 anyway and those who
>> want a G3 for some reason could still use a firmware rom image instead but
>
> I'll bring 'sc 1' back then. I shouldn't mix the refactoring with
> dropping support of things.
>
> If you think we can drop support for the pegasos2 on the G3 let me know
> and I'll send a follow up patch. Or you can send one yourself if you'd
> like.

I think the G3 is probably rarely used on pegasos2, G4 being the default 
and preferred CPU so maybe only needed if somebody wants to test something 
specifically with G3. That's why I said this is not critical, because 
using a firmware rom image would still boot with -cpu G3 if sc 1 is 
removed for G3 and older. We've made sure it still works with G4 so that's 
fine. However leaving this around for now to keep previous behaviour until 
VOF is changed to support a different hypercall method is nice to have if 
it's not much trouble for you so I'm OK with any decision on this.

Regards,
BALATON Zoltan

>> I wonder if there's another better place where sc 1 could be handled so it
>> could work for these cpus without needing to change these excp helpers.
>
> I spoke to Alexey and the way forward here is to have a MMIO address for
> VOF to use and remove the sc 1 usage altogether. At least for the CPUs
> that wouldn't support it otherwise. I created a GitLab issue to track
> that: https://gitlab.com/qemu-project/qemu/-/issues/859



  reply	other threads:[~2022-02-04 16:44 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
2022-02-03 22:42 ` [PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs Fabiano Rosas
2022-02-03 22:42 ` [PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx Fabiano Rosas
2022-02-03 22:42 ` [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx Fabiano Rosas
2022-02-04 13:05   ` BALATON Zoltan
2022-02-04 16:10     ` Fabiano Rosas
2022-02-04 16:42       ` BALATON Zoltan [this message]
2022-02-03 22:42 ` [PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 05/10] target/ppc: 7xx: External interrupt cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 06/10] target/ppc: 7xx: Program exception cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 07/10] target/ppc: 7xx: System Call " Fabiano Rosas
2022-02-03 22:42 ` [PATCH 08/10] target/ppc: 7xx: System Reset cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 09/10] target/ppc: 7xx: Software TLB cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code Fabiano Rosas
2022-02-04  8:00 ` [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Cédric Le Goater
2022-02-04 16:13   ` Fabiano Rosas

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