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From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org,
	david@gibson.dropbear.id.au
Subject: [PATCH 05/10] target/ppc: 7xx: External interrupt cleanup
Date: Thu,  3 Feb 2022 19:42:41 -0300	[thread overview]
Message-ID: <20220203224246.1446652-6-farosas@linux.ibm.com> (raw)
In-Reply-To: <20220203224246.1446652-1-farosas@linux.ibm.com>

There is no MSR_HV in the 7xx so remove the LPES0 handling.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 37 -------------------------------------
 1 file changed, 37 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4996b96616..5e2c2aa544 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -815,44 +815,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
         msr |= env->error_code;
         break;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
-    {
-        bool lpes0;
-
-        cs = CPU(cpu);
-
-        /*
-         * Exception targeting modifiers
-         *
-         * LPES0 is supported on POWER7/8/9
-         * LPES1 is not supported (old iSeries mode)
-         *
-         * On anything else, we behave as if LPES0 is 1
-         * (externals don't alter MSR:HV)
-         */
-#if defined(TARGET_PPC64)
-        if (excp_model == POWERPC_EXCP_POWER7 ||
-            excp_model == POWERPC_EXCP_POWER8 ||
-            excp_model == POWERPC_EXCP_POWER9 ||
-            excp_model == POWERPC_EXCP_POWER10) {
-            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-        } else
-#endif /* defined(TARGET_PPC64) */
-        {
-            lpes0 = true;
-        }
-
-        if (!lpes0) {
-            new_msr |= (target_ulong)MSR_HVB;
-            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-            srr0 = SPR_HSRR0;
-            srr1 = SPR_HSRR1;
-        }
-        if (env->mpic_proxy) {
-            /* IACK the IRQ on delivery */
-            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
-        }
         break;
-    }
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
         /* Get rS/rD and rA from faulting opcode */
         /*
-- 
2.34.1



  parent reply	other threads:[~2022-02-03 23:02 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-03 22:42 [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Fabiano Rosas
2022-02-03 22:42 ` [PATCH 01/10] target/ppc: Merge 7x5 and 7x0 exception model IDs Fabiano Rosas
2022-02-03 22:42 ` [PATCH 02/10] target/ppc: Introduce powerpc_excp_7xx Fabiano Rosas
2022-02-03 22:42 ` [PATCH 03/10] target/ppc: Simplify powerpc_excp_7xx Fabiano Rosas
2022-02-04 13:05   ` BALATON Zoltan
2022-02-04 16:10     ` Fabiano Rosas
2022-02-04 16:42       ` BALATON Zoltan
2022-02-03 22:42 ` [PATCH 04/10] target/ppc: 7xx: Machine Check exception cleanup Fabiano Rosas
2022-02-03 22:42 ` Fabiano Rosas [this message]
2022-02-03 22:42 ` [PATCH 06/10] target/ppc: 7xx: Program " Fabiano Rosas
2022-02-03 22:42 ` [PATCH 07/10] target/ppc: 7xx: System Call " Fabiano Rosas
2022-02-03 22:42 ` [PATCH 08/10] target/ppc: 7xx: System Reset cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 09/10] target/ppc: 7xx: Software TLB cleanup Fabiano Rosas
2022-02-03 22:42 ` [PATCH 10/10] target/ppc: 7xx: Set SRRs directly in exception code Fabiano Rosas
2022-02-04  8:00 ` [PATCH 00/10] target/ppc: powerpc_excp improvements [7xx] (8/n) Cédric Le Goater
2022-02-04 16:13   ` Fabiano Rosas

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