* [PATCH 1/5] ARM: dts: Add clock-output-names for omap4
2022-02-04 8:43 [PATCH 0/5] Unify omap4/5 clocks with clock-output-names Tony Lindgren
@ 2022-02-04 8:43 ` Tony Lindgren
2022-03-11 3:34 ` Stephen Boyd
2022-02-04 8:43 ` [PATCH 2/5] ARM: dts: Drop custom clkctrl compatible and update omap4 l4per Tony Lindgren
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Tony Lindgren @ 2022-02-04 8:43 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, devicetree, Stephen Boyd, Tero Kristo, linux-clk
To stop using the non-standard node name based clock naming, let's
first add the clock-output-names property. This allows us to stop using
the internal legacy clock naming and unify the naming for the TI SoCs in
the following patches.
Note that we must wait on fixing the node naming issues until after the
internal clock names have been updated to avoid adding name translation
unnecessarily.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap443x-clocks.dtsi | 1 +
arch/arm/boot/dts/omap446x-clocks.dtsi | 2 +
arch/arm/boot/dts/omap44xx-clocks.dtsi | 165 +++++++++++++++++++++++++
3 files changed, 168 insertions(+)
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
--- a/arch/arm/boot/dts/omap443x-clocks.dtsi
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -8,6 +8,7 @@ &prm_clocks {
bandgap_fclk: bandgap_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "bandgap_fclk";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
--- a/arch/arm/boot/dts/omap446x-clocks.dtsi
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -8,6 +8,7 @@ &prm_clocks {
div_ts_ck: div_ts_ck@1888 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_ts_ck";
clocks = <&l4_wkup_clk_mux_ck>;
ti,bit-shift = <24>;
reg = <0x1888>;
@@ -17,6 +18,7 @@ div_ts_ck: div_ts_ck@1888 {
bandgap_ts_fclk: bandgap_ts_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "bandgap_ts_fclk";
clocks = <&div_ts_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -8,18 +8,21 @@ &cm1_clocks {
extalt_clkin_ck: extalt_clkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "extalt_clkin_ck";
clock-frequency = <59000000>;
};
pad_clks_src_ck: pad_clks_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_clks_src_ck";
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "pad_clks_ck";
clocks = <&pad_clks_src_ck>;
ti,bit-shift = <8>;
reg = <0x0108>;
@@ -28,24 +31,28 @@ pad_clks_ck: pad_clks_ck@108 {
pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_slimbus_core_clks_ck";
clock-frequency = <12000000>;
};
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
slimbus_src_clk: slimbus_src_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "slimbus_src_clk";
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus_clk";
clocks = <&slimbus_src_clk>;
ti,bit-shift = <10>;
reg = <0x0108>;
@@ -54,84 +61,98 @@ slimbus_clk: slimbus_clk@108 {
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_32k_ck";
clock-frequency = <32768>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
tie_low_clock_ck: tie_low_clock_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "tie_low_clock_ck";
clock-frequency = <0>;
};
utmi_phy_clkout_ck: utmi_phy_clkout_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "utmi_phy_clkout_ck";
clock-frequency = <60000000>;
};
xclk60mhsp1_ck: xclk60mhsp1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp1_ck";
clock-frequency = <60000000>;
};
xclk60mhsp2_ck: xclk60mhsp2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp2_ck";
clock-frequency = <60000000>;
};
xclk60motg_ck: xclk60motg_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60motg_ck";
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
@@ -139,6 +160,7 @@ dpll_abe_ck: dpll_abe_ck@1e0 {
dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
reg = <0x01f0>;
};
@@ -146,6 +168,7 @@ dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -157,6 +180,7 @@ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -165,6 +189,7 @@ abe_24m_fclk: abe_24m_fclk {
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
@@ -175,6 +200,7 @@ abe_clk: abe_clk@108 {
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -186,6 +212,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "core_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
@@ -194,6 +221,7 @@ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@@ -201,12 +229,14 @@ dpll_core_ck: dpll_core_ck@120 {
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m6x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -218,6 +248,7 @@ dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -229,6 +260,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 {
ddrphy_ck: ddrphy_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "ddrphy_ck";
clocks = <&dpll_core_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -237,6 +269,7 @@ ddrphy_ck: ddrphy_ck {
dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m5x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -248,6 +281,7 @@ dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
div_core_ck: div_core_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_core_ck";
clocks = <&dpll_core_m5x2_ck>;
reg = <0x0100>;
ti,max-div = <2>;
@@ -256,6 +290,7 @@ div_core_ck: div_core_ck@100 {
div_iva_hs_clk: div_iva_hs_clk@1dc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_iva_hs_clk";
clocks = <&dpll_core_m5x2_ck>;
ti,max-div = <4>;
reg = <0x01dc>;
@@ -265,6 +300,7 @@ div_iva_hs_clk: div_iva_hs_clk@1dc {
div_mpu_hs_clk: div_mpu_hs_clk@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "div_mpu_hs_clk";
clocks = <&dpll_core_m5x2_ck>;
ti,max-div = <4>;
reg = <0x019c>;
@@ -274,6 +310,7 @@ div_mpu_hs_clk: div_mpu_hs_clk@19c {
dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m4x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -285,6 +322,7 @@ dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
dll_clk_div_ck: dll_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dll_clk_div_ck";
clocks = <&dpll_core_m4x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -293,6 +331,7 @@ dll_clk_div_ck: dll_clk_div_ck {
dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2_ck";
clocks = <&dpll_abe_ck>;
ti,max-div = <31>;
reg = <0x01f0>;
@@ -302,6 +341,7 @@ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "dpll_core_m3x2_gate_ck";
clocks = <&dpll_core_x2_ck>;
ti,bit-shift = <8>;
reg = <0x0134>;
@@ -310,6 +350,7 @@ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
+ clock-output-names = "dpll_core_m3x2_div_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
@@ -319,12 +360,14 @@ dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
dpll_core_m3x2_ck: dpll_core_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "dpll_core_m3x2_ck";
clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
};
dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m7x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -336,6 +379,7 @@ dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "iva_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
ti,bit-shift = <23>;
reg = <0x01ac>;
@@ -344,6 +388,7 @@ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
@@ -353,12 +398,14 @@ dpll_iva_ck: dpll_iva_ck@1a0 {
dpll_iva_x2_ck: dpll_iva_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_iva_x2_ck";
clocks = <&dpll_iva_ck>;
};
dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m4x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -372,6 +419,7 @@ dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_m5x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -385,6 +433,7 @@ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
@@ -392,6 +441,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -403,6 +453,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
per_hs_clk_div_ck: per_hs_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_hs_clk_div_ck";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -411,6 +462,7 @@ per_hs_clk_div_ck: per_hs_clk_div_ck {
usb_hs_clk_div_ck: usb_hs_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_hs_clk_div_ck";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
@@ -419,6 +471,7 @@ usb_hs_clk_div_ck: usb_hs_clk_div_ck {
l3_div_ck: l3_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_div_ck";
clocks = <&div_core_ck>;
ti,bit-shift = <4>;
ti,max-div = <2>;
@@ -428,6 +481,7 @@ l3_div_ck: l3_div_ck@100 {
l4_div_ck: l4_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l4_div_ck";
clocks = <&l3_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <2>;
@@ -437,6 +491,7 @@ l4_div_ck: l4_div_ck@100 {
lp_clk_div_ck: lp_clk_div_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "lp_clk_div_ck";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -445,6 +500,7 @@ lp_clk_div_ck: lp_clk_div_ck {
mpu_periphclk: mpu_periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_periphclk";
clocks = <&dpll_mpu_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -453,6 +509,7 @@ mpu_periphclk: mpu_periphclk {
ocp_abe_iclk: ocp_abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "ocp_abe_iclk";
clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
ti,bit-shift = <24>;
reg = <0x0528>;
@@ -462,6 +519,7 @@ ocp_abe_iclk: ocp_abe_iclk@528 {
per_abe_24m_fclk: per_abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_abe_24m_fclk";
clocks = <&dpll_abe_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -470,6 +528,7 @@ per_abe_24m_fclk: per_abe_24m_fclk {
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
@@ -478,6 +537,7 @@ &prm_clocks {
sys_clkin_ck: sys_clkin_ck@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin_ck";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
@@ -486,6 +546,7 @@ sys_clkin_ck: sys_clkin_ck@110 {
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
reg = <0x0108>;
@@ -494,6 +555,7 @@ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_refclk_mux_ck";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
reg = <0x010c>;
};
@@ -501,6 +563,7 @@ abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
dbgclk_mux_ck: dbgclk_mux_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dbgclk_mux_ck";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -509,6 +572,7 @@ dbgclk_mux_ck: dbgclk_mux_ck {
l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "l4_wkup_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
reg = <0x0108>;
};
@@ -516,6 +580,7 @@ l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
syc_clk_div_ck: syc_clk_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "syc_clk_div_ck";
clocks = <&sys_clkin_ck>;
reg = <0x0100>;
ti,max-div = <2>;
@@ -524,6 +589,7 @@ syc_clk_div_ck: syc_clk_div_ck@100 {
usim_ck: usim_ck@1858 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "usim_ck";
clocks = <&dpll_per_m4x2_ck>;
ti,bit-shift = <24>;
reg = <0x1858>;
@@ -533,6 +599,7 @@ usim_ck: usim_ck@1858 {
usim_fclk: usim_fclk@1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usim_fclk";
clocks = <&usim_ck>;
ti,bit-shift = <8>;
reg = <0x1858>;
@@ -541,6 +608,7 @@ usim_fclk: usim_fclk@1858 {
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
+ clock-output-names = "trace_clk_div_ck";
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
};
};
@@ -548,6 +616,7 @@ trace_clk_div_ck: trace_clk_div_ck {
&prm_clockdomains {
emu_sys_clkdm: emu_sys_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "emu_sys_clkdm";
clocks = <&trace_clk_div_ck>;
};
};
@@ -556,6 +625,7 @@ &cm2_clocks {
per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "per_hsd_byp_clk_mux_ck";
clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
ti,bit-shift = <23>;
reg = <0x014c>;
@@ -564,6 +634,7 @@ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@@ -571,6 +642,7 @@ dpll_per_ck: dpll_per_ck@140 {
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -580,6 +652,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 {
dpll_per_x2_ck: dpll_per_x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
reg = <0x0150>;
};
@@ -587,6 +660,7 @@ dpll_per_x2_ck: dpll_per_x2_ck@150 {
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -598,6 +672,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "dpll_per_m3x2_gate_ck";
clocks = <&dpll_per_x2_ck>;
ti,bit-shift = <8>;
reg = <0x0154>;
@@ -606,6 +681,7 @@ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
+ clock-output-names = "dpll_per_m3x2_div_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0154>;
@@ -615,12 +691,14 @@ dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "dpll_per_m3x2_ck";
clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
};
dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m4x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -632,6 +710,7 @@ dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m5x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -643,6 +722,7 @@ dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m6x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -654,6 +734,7 @@ dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m7x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
ti,autoidle-shift = <8>;
@@ -665,6 +746,7 @@ dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
@@ -672,6 +754,7 @@ dpll_usb_ck: dpll_usb_ck@180 {
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo_ck";
clocks = <&dpll_usb_ck>;
ti,clock-div = <1>;
ti,autoidle-shift = <8>;
@@ -683,6 +766,7 @@ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
ti,autoidle-shift = <8>;
@@ -694,6 +778,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "ducati_clk_mux_ck";
clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
reg = <0x0100>;
};
@@ -701,6 +786,7 @@ ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -709,6 +795,7 @@ func_12m_fclk: func_12m_fclk {
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -717,6 +804,7 @@ func_24m_clk: func_24m_clk {
func_24mc_fclk: func_24mc_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24mc_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -725,6 +813,7 @@ func_24mc_fclk: func_24mc_fclk {
func_48m_fclk: func_48m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
reg = <0x0108>;
ti,dividers = <4>, <8>;
@@ -733,6 +822,7 @@ func_48m_fclk: func_48m_fclk@108 {
func_48mc_fclk: func_48mc_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48mc_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -741,6 +831,7 @@ func_48mc_fclk: func_48mc_fclk {
func_64m_fclk: func_64m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_64m_fclk";
clocks = <&dpll_per_m4x2_ck>;
reg = <0x0108>;
ti,dividers = <2>, <4>;
@@ -749,6 +840,7 @@ func_64m_fclk: func_64m_fclk@108 {
func_96m_fclk: func_96m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
reg = <0x0108>;
ti,dividers = <2>, <4>;
@@ -757,6 +849,7 @@ func_96m_fclk: func_96m_fclk@108 {
init_60m_fclk: init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
@@ -765,6 +858,7 @@ init_60m_fclk: init_60m_fclk@104 {
per_abe_nc_fclk: per_abe_nc_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "per_abe_nc_fclk";
clocks = <&dpll_abe_m2_ck>;
reg = <0x0108>;
ti,max-div = <2>;
@@ -773,6 +867,7 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 {
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy_cm_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
@@ -782,6 +877,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "l3_init_clkdm";
clocks = <&dpll_usb_ck>;
};
};
@@ -790,6 +886,7 @@ &scrm_clocks {
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk0_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0310>;
@@ -798,6 +895,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk0_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0310>;
@@ -806,12 +904,14 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
auxclk0_src_ck: auxclk0_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk0_src_ck";
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk0_ck";
clocks = <&auxclk0_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -821,6 +921,7 @@ auxclk0_ck: auxclk0_ck@310 {
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk1_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0314>;
@@ -829,6 +930,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk1_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0314>;
@@ -837,12 +939,14 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
auxclk1_src_ck: auxclk1_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk1_src_ck";
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk1_ck";
clocks = <&auxclk1_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -852,6 +956,7 @@ auxclk1_ck: auxclk1_ck@314 {
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk2_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0318>;
@@ -860,6 +965,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk2_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0318>;
@@ -868,12 +974,14 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
auxclk2_src_ck: auxclk2_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk2_src_ck";
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk2_ck";
clocks = <&auxclk2_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -883,6 +991,7 @@ auxclk2_ck: auxclk2_ck@318 {
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk3_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x031c>;
@@ -891,6 +1000,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk3_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x031c>;
@@ -899,12 +1009,14 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
auxclk3_src_ck: auxclk3_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk3_src_ck";
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk3_ck";
clocks = <&auxclk3_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -914,6 +1026,7 @@ auxclk3_ck: auxclk3_ck@31c {
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk4_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0320>;
@@ -922,6 +1035,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk4_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0320>;
@@ -930,12 +1044,14 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
auxclk4_src_ck: auxclk4_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk4_src_ck";
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk4_ck";
clocks = <&auxclk4_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -945,6 +1061,7 @@ auxclk4_ck: auxclk4_ck@320 {
auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk5_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0324>;
@@ -953,6 +1070,7 @@ auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk5_src_mux_ck";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0324>;
@@ -961,12 +1079,14 @@ auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
auxclk5_src_ck: auxclk5_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk5_src_ck";
clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
};
auxclk5_ck: auxclk5_ck@324 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk5_ck";
clocks = <&auxclk5_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -976,6 +1096,7 @@ auxclk5_ck: auxclk5_ck@324 {
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq0_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0210>;
@@ -984,6 +1105,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 {
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq1_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0214>;
@@ -992,6 +1114,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 {
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq2_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0218>;
@@ -1000,6 +1123,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 {
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq3_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x021c>;
@@ -1008,6 +1132,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c {
auxclkreq4_ck: auxclkreq4_ck@220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq4_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0220>;
@@ -1016,6 +1141,7 @@ auxclkreq4_ck: auxclkreq4_ck@220 {
auxclkreq5_ck: auxclkreq5_ck@224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq5_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
ti,bit-shift = <2>;
reg = <0x0224>;
@@ -1025,6 +1151,7 @@ auxclkreq5_ck: auxclkreq5_ck@224 {
&cm1 {
mpuss_cm: mpuss_cm@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpuss_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1032,6 +1159,7 @@ mpuss_cm: mpuss_cm@300 {
mpuss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpuss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1039,6 +1167,7 @@ mpuss_clkctrl: clk@20 {
tesla_cm: tesla_cm@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "tesla_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1046,6 +1175,7 @@ tesla_cm: tesla_cm@400 {
tesla_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "tesla_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1053,6 +1183,7 @@ tesla_clkctrl: clk@20 {
abe_cm: abe_cm@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "abe_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1060,6 +1191,7 @@ abe_cm: abe_cm@500 {
abe_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "abe_clkctrl";
reg = <0x20 0x6c>;
#clock-cells = <2>;
};
@@ -1070,6 +1202,7 @@ abe_clkctrl: clk@20 {
&cm2 {
l4_ao_cm: l4_ao_cm@600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_ao_cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1077,6 +1210,7 @@ l4_ao_cm: l4_ao_cm@600 {
l4_ao_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_ao_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1084,6 +1218,7 @@ l4_ao_clkctrl: clk@20 {
l3_1_cm: l3_1_cm@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1091,6 +1226,7 @@ l3_1_cm: l3_1_cm@700 {
l3_1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1098,6 +1234,7 @@ l3_1_clkctrl: clk@20 {
l3_2_cm: l3_2_cm@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_2_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1105,6 +1242,7 @@ l3_2_cm: l3_2_cm@800 {
l3_2_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_2_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1112,6 +1250,7 @@ l3_2_clkctrl: clk@20 {
ducati_cm: ducati_cm@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ducati_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1119,6 +1258,7 @@ ducati_cm: ducati_cm@900 {
ducati_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ducati_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1126,6 +1266,7 @@ ducati_clkctrl: clk@20 {
l3_dma_cm: l3_dma_cm@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1133,6 +1274,7 @@ l3_dma_cm: l3_dma_cm@a00 {
l3_dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1140,6 +1282,7 @@ l3_dma_clkctrl: clk@20 {
l3_emif_cm: l3_emif_cm@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1147,6 +1290,7 @@ l3_emif_cm: l3_emif_cm@b00 {
l3_emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_emif_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1154,6 +1298,7 @@ l3_emif_clkctrl: clk@20 {
d2d_cm: d2d_cm@c00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "d2d_cm";
reg = <0xc00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1161,6 +1306,7 @@ d2d_cm: d2d_cm@c00 {
d2d_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "d2d_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1168,6 +1314,7 @@ d2d_clkctrl: clk@20 {
l4_cfg_cm: l4_cfg_cm@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1175,6 +1322,7 @@ l4_cfg_cm: l4_cfg_cm@d00 {
l4_cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_cfg_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1182,6 +1330,7 @@ l4_cfg_clkctrl: clk@20 {
l3_instr_cm: l3_instr_cm@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1189,6 +1338,7 @@ l3_instr_cm: l3_instr_cm@e00 {
l3_instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_instr_clkctrl";
reg = <0x20 0x24>;
#clock-cells = <2>;
};
@@ -1196,6 +1346,7 @@ l3_instr_clkctrl: clk@20 {
ivahd_cm: ivahd_cm@f00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ivahd_cm";
reg = <0xf00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1203,6 +1354,7 @@ ivahd_cm: ivahd_cm@f00 {
ivahd_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ivahd_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1210,6 +1362,7 @@ ivahd_clkctrl: clk@20 {
iss_cm: iss_cm@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "iss_cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1217,6 +1370,7 @@ iss_cm: iss_cm@1000 {
iss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "iss_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1224,6 +1378,7 @@ iss_clkctrl: clk@20 {
l3_dss_cm: l3_dss_cm@1100 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_dss_cm";
reg = <0x1100 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1231,6 +1386,7 @@ l3_dss_cm: l3_dss_cm@1100 {
l3_dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_dss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1238,6 +1394,7 @@ l3_dss_clkctrl: clk@20 {
l3_gfx_cm: l3_gfx_cm@1200 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_gfx_cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1245,6 +1402,7 @@ l3_gfx_cm: l3_gfx_cm@1200 {
l3_gfx_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_gfx_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1252,6 +1410,7 @@ l3_gfx_clkctrl: clk@20 {
l3_init_cm: l3_init_cm@1300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3_init_cm";
reg = <0x1300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1259,6 +1418,7 @@ l3_init_cm: l3_init_cm@1300 {
l3_init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3_init_clkctrl";
reg = <0x20 0xc4>;
#clock-cells = <2>;
};
@@ -1266,6 +1426,7 @@ l3_init_clkctrl: clk@20 {
l4_per_cm: l4_per_cm@1400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_per_cm";
reg = <0x1400 0x200>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1288,6 +1449,7 @@ l4_secure_clkctrl: clock@1a0 {
&prm {
l4_wkup_cm: l4_wkup_cm@1800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4_wkup_cm";
reg = <0x1800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1295,6 +1457,7 @@ l4_wkup_cm: l4_wkup_cm@1800 {
l4_wkup_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4_wkup_clkctrl";
reg = <0x20 0x5c>;
#clock-cells = <2>;
};
@@ -1302,6 +1465,7 @@ l4_wkup_clkctrl: clk@20 {
emu_sys_cm: emu_sys_cm@1a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emu_sys_cm";
reg = <0x1a00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1309,6 +1473,7 @@ emu_sys_cm: emu_sys_cm@1a00 {
emu_sys_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emu_sys_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
--
2.35.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/5] ARM: dts: Add clock-output-names for omap5
2022-02-04 8:43 [PATCH 0/5] Unify omap4/5 clocks with clock-output-names Tony Lindgren
2022-02-04 8:43 ` [PATCH 1/5] ARM: dts: Add clock-output-names for omap4 Tony Lindgren
2022-02-04 8:43 ` [PATCH 2/5] ARM: dts: Drop custom clkctrl compatible and update omap4 l4per Tony Lindgren
@ 2022-02-04 8:43 ` Tony Lindgren
2022-02-04 8:43 ` [PATCH 4/5] ARM: dts: Drop custom clkctrl compatible and update omap5 l4per Tony Lindgren
2022-02-04 8:43 ` [PATCH 5/5] clk: ti: Stop using legacy clkctrl names for omap4 and 5 Tony Lindgren
4 siblings, 0 replies; 9+ messages in thread
From: Tony Lindgren @ 2022-02-04 8:43 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, devicetree, Stephen Boyd, Tero Kristo, linux-clk
To stop using the non-standard node name based clock naming, let's
first add the clock-output-names property. This allows us to stop using
the internal legacy clock naming and unify the naming for the TI SoCs in
the following patches.
Note that we must wait on fixing the node naming issues until after the
internal clock names have been updated to avoid adding name translation
unnecessarily.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 152 +++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -8,12 +8,14 @@ &cm_core_aon_clocks {
pad_clks_src_ck: pad_clks_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "pad_clks_src_ck";
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "pad_clks_ck";
clocks = <&pad_clks_src_ck>;
ti,bit-shift = <8>;
reg = <0x0108>;
@@ -22,18 +24,21 @@ pad_clks_ck: pad_clks_ck@108 {
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "secure_32k_clk_src_ck";
clock-frequency = <32768>;
};
slimbus_src_clk: slimbus_src_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "slimbus_src_clk";
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus_clk";
clocks = <&slimbus_src_clk>;
ti,bit-shift = <10>;
reg = <0x0108>;
@@ -42,66 +47,77 @@ slimbus_clk: slimbus_clk@108 {
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "sys_32k_ck";
clock-frequency = <32768>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_12000000_ck";
clock-frequency = <12000000>;
};
virt_13000000_ck: virt_13000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_13000000_ck";
clock-frequency = <13000000>;
};
virt_16800000_ck: virt_16800000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_16800000_ck";
clock-frequency = <16800000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_19200000_ck";
clock-frequency = <19200000>;
};
virt_26000000_ck: virt_26000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_26000000_ck";
clock-frequency = <26000000>;
};
virt_27000000_ck: virt_27000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_27000000_ck";
clock-frequency = <27000000>;
};
virt_38400000_ck: virt_38400000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "virt_38400000_ck";
clock-frequency = <38400000>;
};
xclk60mhsp1_ck: xclk60mhsp1_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp1_ck";
clock-frequency = <60000000>;
};
xclk60mhsp2_ck: xclk60mhsp2_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "xclk60mhsp2_ck";
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
+ clock-output-names = "dpll_abe_ck";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
@@ -109,12 +125,14 @@ dpll_abe_ck: dpll_abe_ck@1e0 {
dpll_abe_x2_ck: dpll_abe_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_abe_x2_ck";
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m2x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
reg = <0x01f0>;
@@ -124,6 +142,7 @@ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
abe_24m_fclk: abe_24m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_24m_fclk";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <8>;
@@ -132,6 +151,7 @@ abe_24m_fclk: abe_24m_fclk {
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_clk";
clocks = <&dpll_abe_m2x2_ck>;
ti,max-div = <4>;
reg = <0x0108>;
@@ -141,6 +161,7 @@ abe_clk: abe_clk@108 {
abe_iclk: abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "abe_iclk";
clocks = <&aess_fclk>;
ti,bit-shift = <24>;
reg = <0x0528>;
@@ -150,6 +171,7 @@ abe_iclk: abe_iclk@528 {
abe_lp_clk_div: abe_lp_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "abe_lp_clk_div";
clocks = <&dpll_abe_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -158,6 +180,7 @@ abe_lp_clk_div: abe_lp_clk_div {
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_abe_m3x2_ck";
clocks = <&dpll_abe_x2_ck>;
ti,max-div = <31>;
reg = <0x01f4>;
@@ -167,6 +190,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
ti,bit-shift = <23>;
reg = <0x012c>;
@@ -175,6 +199,7 @@ dpll_core_byp_mux: dpll_core_byp_mux@12c {
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
+ clock-output-names = "dpll_core_ck";
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
};
@@ -182,12 +207,14 @@ dpll_core_ck: dpll_core_ck@120 {
dpll_core_x2_ck: dpll_core_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_core_x2_ck";
clocks = <&dpll_core_ck>;
};
dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h21x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0150>;
@@ -197,6 +224,7 @@ dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
c2c_fclk: c2c_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "c2c_fclk";
clocks = <&dpll_core_h21x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -205,6 +233,7 @@ c2c_fclk: c2c_fclk {
c2c_iclk: c2c_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "c2c_iclk";
clocks = <&c2c_fclk>;
clock-mult = <1>;
clock-div = <2>;
@@ -213,6 +242,7 @@ c2c_iclk: c2c_iclk {
dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h11x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0138>;
@@ -222,6 +252,7 @@ dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h12x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x013c>;
@@ -231,6 +262,7 @@ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h13x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0140>;
@@ -240,6 +272,7 @@ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h14x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0144>;
@@ -249,6 +282,7 @@ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h22x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0154>;
@@ -258,6 +292,7 @@ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h23x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x0158>;
@@ -267,6 +302,7 @@ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_h24x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <63>;
reg = <0x015c>;
@@ -276,6 +312,7 @@ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m2_ck";
clocks = <&dpll_core_ck>;
ti,max-div = <31>;
reg = <0x0130>;
@@ -285,6 +322,7 @@ dpll_core_m2_ck: dpll_core_m2_ck@130 {
dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_core_m3x2_ck";
clocks = <&dpll_core_x2_ck>;
ti,max-div = <31>;
reg = <0x0134>;
@@ -294,6 +332,7 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "iva_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -302,6 +341,7 @@ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x01ac>;
@@ -310,6 +350,7 @@ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_iva_ck";
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
assigned-clocks = <&dpll_iva_ck>;
@@ -319,12 +360,14 @@ dpll_iva_ck: dpll_iva_ck@1a0 {
dpll_iva_x2_ck: dpll_iva_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_iva_x2_ck";
clocks = <&dpll_iva_ck>;
};
dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_h11x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
reg = <0x01b8>;
@@ -336,6 +379,7 @@ dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_iva_h12x2_ck";
clocks = <&dpll_iva_x2_ck>;
ti,max-div = <63>;
reg = <0x01bc>;
@@ -347,6 +391,7 @@ dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "mpu_dpll_hs_clk_div";
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -355,6 +400,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
+ clock-output-names = "dpll_mpu_ck";
clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
@@ -362,6 +408,7 @@ dpll_mpu_ck: dpll_mpu_ck@160 {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_mpu_m2_ck";
clocks = <&dpll_mpu_ck>;
ti,max-div = <31>;
reg = <0x0170>;
@@ -371,6 +418,7 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
per_dpll_hs_clk_div: per_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "per_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -379,6 +427,7 @@ per_dpll_hs_clk_div: per_dpll_hs_clk_div {
usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "usb_dpll_hs_clk_div";
clocks = <&dpll_abe_m3x2_ck>;
clock-mult = <1>;
clock-div = <3>;
@@ -387,6 +436,7 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x100>;
@@ -397,6 +447,7 @@ l3_iclk_div: l3_iclk_div@100 {
gpu_l3_iclk: gpu_l3_iclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "gpu_l3_iclk";
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <1>;
@@ -405,6 +456,7 @@ gpu_l3_iclk: gpu_l3_iclk {
l4_root_clk_div: l4_root_clk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l4_root_clk_div";
ti,max-div = <2>;
ti,bit-shift = <8>;
reg = <0x100>;
@@ -415,6 +467,7 @@ l4_root_clk_div: l4_root_clk_div@100 {
slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "slimbus1_slimbus_clk";
clocks = <&slimbus_clk>;
ti,bit-shift = <11>;
reg = <0x0560>;
@@ -423,6 +476,7 @@ slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "aess_fclk";
clocks = <&abe_clk>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -432,6 +486,7 @@ aess_fclk: aess_fclk@528 {
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mcasp_sync_mux_ck";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
ti,bit-shift = <26>;
reg = <0x0540>;
@@ -440,6 +495,7 @@ mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
mcasp_gfclk: mcasp_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "mcasp_gfclk";
clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
ti,bit-shift = <24>;
reg = <0x0540>;
@@ -448,6 +504,7 @@ mcasp_gfclk: mcasp_gfclk@540 {
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
+ clock-output-names = "dummy_ck";
clock-frequency = <0>;
};
};
@@ -455,6 +512,7 @@ &prm_clocks {
sys_clkin: sys_clkin@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "sys_clkin";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
@@ -463,6 +521,7 @@ sys_clkin: sys_clkin@110 {
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_bypass_clk_mux";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x0108>;
};
@@ -470,6 +529,7 @@ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_clk_mux";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x010c>;
};
@@ -477,6 +537,7 @@ abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "custefuse_sys_gfclk_div";
clocks = <&sys_clkin>;
clock-mult = <1>;
clock-div = <2>;
@@ -485,6 +546,7 @@ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
dss_syc_gfclk_div: dss_syc_gfclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dss_syc_gfclk_div";
clocks = <&sys_clkin>;
clock-mult = <1>;
clock-div = <1>;
@@ -493,6 +555,7 @@ dss_syc_gfclk_div: dss_syc_gfclk_div {
wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "wkupaon_iclk_mux";
clocks = <&sys_clkin>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
@@ -500,6 +563,7 @@ wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
l3instr_ts_gclk_div: l3instr_ts_gclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "l3instr_ts_gclk_div";
clocks = <&wkupaon_iclk_mux>;
clock-mult = <1>;
clock-div = <1>;
@@ -511,6 +575,7 @@ &cm_core_clocks {
dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x014c>;
@@ -519,6 +584,7 @@ dpll_per_byp_mux: dpll_per_byp_mux@14c {
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_per_ck";
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
@@ -526,12 +592,14 @@ dpll_per_ck: dpll_per_ck@140 {
dpll_per_x2_ck: dpll_per_x2_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h11x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x0158>;
@@ -541,6 +609,7 @@ dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h12x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x015c>;
@@ -550,6 +619,7 @@ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_h14x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <63>;
reg = <0x0164>;
@@ -559,6 +629,7 @@ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2_ck";
clocks = <&dpll_per_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -568,6 +639,7 @@ dpll_per_m2_ck: dpll_per_m2_ck@150 {
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0150>;
@@ -577,6 +649,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m3x2_ck";
clocks = <&dpll_per_x2_ck>;
ti,max-div = <31>;
reg = <0x0154>;
@@ -586,6 +659,7 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
dpll_unipro1_ck: dpll_unipro1_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_unipro1_ck";
clocks = <&sys_clkin>, <&sys_clkin>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
@@ -593,6 +667,7 @@ dpll_unipro1_ck: dpll_unipro1_ck@200 {
dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_unipro1_clkdcoldo";
clocks = <&dpll_unipro1_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -601,6 +676,7 @@ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_unipro1_m2_ck";
clocks = <&dpll_unipro1_ck>;
ti,max-div = <127>;
reg = <0x0210>;
@@ -610,6 +686,7 @@ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
+ clock-output-names = "dpll_unipro2_ck";
clocks = <&sys_clkin>, <&sys_clkin>;
reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
};
@@ -617,6 +694,7 @@ dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_unipro2_clkdcoldo";
clocks = <&dpll_unipro2_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -625,6 +703,7 @@ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_unipro2_m2_ck";
clocks = <&dpll_unipro2_ck>;
ti,max-div = <127>;
reg = <0x01d0>;
@@ -634,6 +713,7 @@ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
ti,bit-shift = <23>;
reg = <0x018c>;
@@ -642,6 +722,7 @@ dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
+ clock-output-names = "dpll_usb_ck";
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
@@ -649,6 +730,7 @@ dpll_usb_ck: dpll_usb_ck@180 {
dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "dpll_usb_clkdcoldo";
clocks = <&dpll_usb_ck>;
clock-mult = <1>;
clock-div = <1>;
@@ -657,6 +739,7 @@ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "dpll_usb_m2_ck";
clocks = <&dpll_usb_ck>;
ti,max-div = <127>;
reg = <0x0190>;
@@ -666,6 +749,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
func_128m_clk: func_128m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_128m_clk";
clocks = <&dpll_per_h11x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -674,6 +758,7 @@ func_128m_clk: func_128m_clk {
func_12m_fclk: func_12m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_12m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <16>;
@@ -682,6 +767,7 @@ func_12m_fclk: func_12m_fclk {
func_24m_clk: func_24m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_24m_clk";
clocks = <&dpll_per_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -690,6 +776,7 @@ func_24m_clk: func_24m_clk {
func_48m_fclk: func_48m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_48m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <4>;
@@ -698,6 +785,7 @@ func_48m_fclk: func_48m_fclk {
func_96m_fclk: func_96m_fclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
+ clock-output-names = "func_96m_fclk";
clocks = <&dpll_per_m2x2_ck>;
clock-mult = <1>;
clock-div = <2>;
@@ -706,6 +794,7 @@ func_96m_fclk: func_96m_fclk {
l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "l3init_60m_fclk";
clocks = <&dpll_usb_m2_ck>;
reg = <0x0104>;
ti,dividers = <1>, <8>;
@@ -714,6 +803,7 @@ l3init_60m_fclk: l3init_60m_fclk@104 {
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "iss_ctrlclk";
clocks = <&func_96m_fclk>;
ti,bit-shift = <8>;
reg = <0x1320>;
@@ -722,6 +812,7 @@ iss_ctrlclk: iss_ctrlclk@1320 {
lli_txphy_clk: lli_txphy_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "lli_txphy_clk";
clocks = <&dpll_unipro1_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x0f20>;
@@ -730,6 +821,7 @@ lli_txphy_clk: lli_txphy_clk@f20 {
lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "lli_txphy_ls_clk";
clocks = <&dpll_unipro1_m2_ck>;
ti,bit-shift = <9>;
reg = <0x0f20>;
@@ -738,6 +830,7 @@ lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "usb_phy_cm_clk32k";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x0640>;
@@ -746,6 +839,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
fdif_fclk: fdif_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "fdif_fclk";
clocks = <&dpll_per_h11x2_ck>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -755,6 +849,7 @@ fdif_fclk: fdif_fclk@1328 {
gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_core_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
ti,bit-shift = <24>;
reg = <0x1520>;
@@ -763,6 +858,7 @@ gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "gpu_hyd_gclk_mux";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
ti,bit-shift = <25>;
reg = <0x1520>;
@@ -771,6 +867,7 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
hsi_fclk: hsi_fclk@1638 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "hsi_fclk";
clocks = <&dpll_per_m2x2_ck>;
ti,bit-shift = <24>;
ti,max-div = <2>;
@@ -781,6 +878,7 @@ hsi_fclk: hsi_fclk@1638 {
&cm_core_clockdomains {
l3init_clkdm: l3init_clkdm {
compatible = "ti,clockdomain";
+ clock-output-names = "l3init_clkdm";
clocks = <&dpll_usb_ck>;
};
};
@@ -789,6 +887,7 @@ &scrm_clocks {
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk0_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0310>;
@@ -797,6 +896,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk0_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0310>;
@@ -805,12 +905,14 @@ auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
auxclk0_src_ck: auxclk0_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk0_src_ck";
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk0_ck";
clocks = <&auxclk0_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -820,6 +922,7 @@ auxclk0_ck: auxclk0_ck@310 {
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk1_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0314>;
@@ -828,6 +931,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk1_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0314>;
@@ -836,12 +940,14 @@ auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
auxclk1_src_ck: auxclk1_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk1_src_ck";
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk1_ck";
clocks = <&auxclk1_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -851,6 +957,7 @@ auxclk1_ck: auxclk1_ck@314 {
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk2_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0318>;
@@ -859,6 +966,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk2_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0318>;
@@ -867,12 +975,14 @@ auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
auxclk2_src_ck: auxclk2_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk2_src_ck";
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk2_ck";
clocks = <&auxclk2_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -882,6 +992,7 @@ auxclk2_ck: auxclk2_ck@318 {
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk3_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x031c>;
@@ -890,6 +1001,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk3_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x031c>;
@@ -898,12 +1010,14 @@ auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
auxclk3_src_ck: auxclk3_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk3_src_ck";
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk3_ck";
clocks = <&auxclk3_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -913,6 +1027,7 @@ auxclk3_ck: auxclk3_ck@31c {
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
+ clock-output-names = "auxclk4_src_gate_ck";
clocks = <&dpll_core_m3x2_ck>;
ti,bit-shift = <8>;
reg = <0x0320>;
@@ -921,6 +1036,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
+ clock-output-names = "auxclk4_src_mux_ck";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
ti,bit-shift = <1>;
reg = <0x0320>;
@@ -929,12 +1045,14 @@ auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
auxclk4_src_ck: auxclk4_src_ck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
+ clock-output-names = "auxclk4_src_ck";
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
+ clock-output-names = "auxclk4_ck";
clocks = <&auxclk4_src_ck>;
ti,bit-shift = <16>;
ti,max-div = <16>;
@@ -944,6 +1062,7 @@ auxclk4_ck: auxclk4_ck@320 {
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq0_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0210>;
@@ -952,6 +1071,7 @@ auxclkreq0_ck: auxclkreq0_ck@210 {
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq1_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0214>;
@@ -960,6 +1080,7 @@ auxclkreq1_ck: auxclkreq1_ck@214 {
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq2_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x0218>;
@@ -968,6 +1089,7 @@ auxclkreq2_ck: auxclkreq2_ck@218 {
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
+ clock-output-names = "auxclkreq3_ck";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
ti,bit-shift = <2>;
reg = <0x021c>;
@@ -977,6 +1099,7 @@ auxclkreq3_ck: auxclkreq3_ck@21c {
&cm_core_aon {
mpu_cm: mpu_cm@300 {
compatible = "ti,omap4-cm";
+ clock-output-names = "mpu_cm";
reg = <0x300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -984,6 +1107,7 @@ mpu_cm: mpu_cm@300 {
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "mpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -991,6 +1115,7 @@ mpu_clkctrl: clk@20 {
dsp_cm: dsp_cm@400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dsp_cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -998,6 +1123,7 @@ dsp_cm: dsp_cm@400 {
dsp_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dsp_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1005,6 +1131,7 @@ dsp_clkctrl: clk@20 {
abe_cm: abe_cm@500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "abe_cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1012,6 +1139,7 @@ abe_cm: abe_cm@500 {
abe_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "abe_clkctrl";
reg = <0x20 0x64>;
#clock-cells = <2>;
};
@@ -1022,6 +1150,7 @@ abe_clkctrl: clk@20 {
&cm_core {
l3main1_cm: l3main1_cm@700 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main1_cm";
reg = <0x700 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1029,6 +1158,7 @@ l3main1_cm: l3main1_cm@700 {
l3main1_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main1_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1036,6 +1166,7 @@ l3main1_clkctrl: clk@20 {
l3main2_cm: l3main2_cm@800 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3main2_cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1043,6 +1174,7 @@ l3main2_cm: l3main2_cm@800 {
l3main2_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3main2_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1050,6 +1182,7 @@ l3main2_clkctrl: clk@20 {
ipu_cm: ipu_cm@900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "ipu_cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1057,6 +1190,7 @@ ipu_cm: ipu_cm@900 {
ipu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "ipu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1064,6 +1198,7 @@ ipu_clkctrl: clk@20 {
dma_cm: dma_cm@a00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dma_cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1071,6 +1206,7 @@ dma_cm: dma_cm@a00 {
dma_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dma_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1078,6 +1214,7 @@ dma_clkctrl: clk@20 {
emif_cm: emif_cm@b00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "emif_cm";
reg = <0xb00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1085,6 +1222,7 @@ emif_cm: emif_cm@b00 {
emif_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "emif_clkctrl";
reg = <0x20 0x1c>;
#clock-cells = <2>;
};
@@ -1092,6 +1230,7 @@ emif_clkctrl: clk@20 {
l4cfg_cm: l4cfg_cm@d00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4cfg_cm";
reg = <0xd00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1099,6 +1238,7 @@ l4cfg_cm: l4cfg_cm@d00 {
l4cfg_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l4cfg_clkctrl";
reg = <0x20 0x14>;
#clock-cells = <2>;
};
@@ -1106,6 +1246,7 @@ l4cfg_clkctrl: clk@20 {
l3instr_cm: l3instr_cm@e00 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3instr_cm";
reg = <0xe00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1113,6 +1254,7 @@ l3instr_cm: l3instr_cm@e00 {
l3instr_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3instr_clkctrl";
reg = <0x20 0xc>;
#clock-cells = <2>;
};
@@ -1120,6 +1262,7 @@ l3instr_clkctrl: clk@20 {
l4per_cm: l4per_cm@1000 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l4per_cm";
reg = <0x1000 0x200>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1140,6 +1283,7 @@ l4sec_clkctrl: clock@1a0 {
dss_cm: dss_cm@1400 {
compatible = "ti,omap4-cm";
+ clock-output-names = "dss_cm";
reg = <0x1400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1147,6 +1291,7 @@ dss_cm: dss_cm@1400 {
dss_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "dss_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1154,6 +1299,7 @@ dss_clkctrl: clk@20 {
gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm";
+ clock-output-names = "gpu_cm";
reg = <0x1500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1161,6 +1307,7 @@ gpu_cm: gpu_cm@1500 {
gpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "gpu_clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
@@ -1168,6 +1315,7 @@ gpu_clkctrl: clk@20 {
l3init_cm: l3init_cm@1600 {
compatible = "ti,omap4-cm";
+ clock-output-names = "l3init_cm";
reg = <0x1600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1175,6 +1323,7 @@ l3init_cm: l3init_cm@1600 {
l3init_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "l3init_clkctrl";
reg = <0x20 0xd4>;
#clock-cells = <2>;
};
@@ -1184,6 +1333,7 @@ l3init_clkctrl: clk@20 {
&prm {
wkupaon_cm: wkupaon_cm@1900 {
compatible = "ti,omap4-cm";
+ clock-output-names = "wkupaon_cm";
reg = <0x1900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1191,6 +1341,7 @@ wkupaon_cm: wkupaon_cm@1900 {
wkupaon_clkctrl: clk@20 {
compatible = "ti,clkctrl";
+ clock-output-names = "wkupaon_clkctrl";
reg = <0x20 0x5c>;
#clock-cells = <2>;
};
@@ -1201,6 +1352,7 @@ &scm_wkup_pad_conf_clocks {
fref_xtal_ck: fref_xtal_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
+ clock-output-names = "fref_xtal_ck";
clocks = <&sys_clkin>;
ti,bit-shift = <28>;
reg = <0x14>;
--
2.35.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 5/5] clk: ti: Stop using legacy clkctrl names for omap4 and 5
2022-02-04 8:43 [PATCH 0/5] Unify omap4/5 clocks with clock-output-names Tony Lindgren
` (3 preceding siblings ...)
2022-02-04 8:43 ` [PATCH 4/5] ARM: dts: Drop custom clkctrl compatible and update omap5 l4per Tony Lindgren
@ 2022-02-04 8:43 ` Tony Lindgren
4 siblings, 0 replies; 9+ messages in thread
From: Tony Lindgren @ 2022-02-04 8:43 UTC (permalink / raw)
To: linux-omap
Cc: Benoît Cousson, devicetree, linux-clk, Stephen Boyd, Tero Kristo
With the addition of clock-output-names, we can now unify the internal
clock naming for omap4 and 5 to follow the other TI SoCs.
We are still using legacy clkctrl names for omap4 and 5 based on the clock
manager name which is wrong. Instead, we want to use the clkctrl clock
based naming.
We must now also drop the legacy TI_CLK_CLKCTRL_COMPAT quirk for the
clkctrl clock.
Cc: linux-clk@vger.kernel.org
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <kristo@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
drivers/clk/ti/clk-44xx.c | 210 +++++++++++++++++++-------------------
drivers/clk/ti/clk-54xx.c | 160 ++++++++++++++---------------
drivers/clk/ti/clkctrl.c | 4 -
3 files changed, 185 insertions(+), 189 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
};
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
- "abe_cm:clk:0018:26",
+ "abe-clkctrl:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
};
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
- "abe_cm:clk:0020:26",
+ "abe-clkctrl:0020:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
};
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
- "abe_cm:clk:0028:26",
+ "abe-clkctrl:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
};
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
- "abe_cm:clk:0030:26",
+ "abe-clkctrl:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
};
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
- "abe_cm:clk:0038:26",
+ "abe-clkctrl:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
- { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
+ { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
- { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
- { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
- { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
- { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
- { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
- { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
- { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
- { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
- { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
- { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
+ { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
+ { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
+ { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
+ { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
+ { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
+ { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
+ { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
+ { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
+ { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
+ { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
@@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
- { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
+ { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
{ 0 },
};
@@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
- { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
+ { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
{ 0 },
};
@@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
- { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
+ { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
{ 0 },
};
@@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
};
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
- "l3_init_cm:clk:0038:24",
+ "l3-init-clkctrl:0038:24",
NULL,
};
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
- "l3_init_cm:clk:0038:25",
+ "l3-init-clkctrl:0038:25",
NULL,
};
@@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
};
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
- "l3_init_cm:clk:0040:24",
+ "l3-init-clkctrl:0040:24",
NULL,
};
@@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
};
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
- { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
- { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
- { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
+ { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
+ { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
+ { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
- { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
+ { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
{ 0 },
};
@@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
};
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
- "l4_per_cm:clk:00c0:26",
+ "l4-per-clkctrl:00c0:26",
"pad_clks_ck",
NULL,
};
@@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
- { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
- { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
- { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
- { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
- { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
- { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
+ { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
+ { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
+ { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
+ { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
+ { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
+ { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
@@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
- { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
+ { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
+ { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
@@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
- { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
+ { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
@@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
};
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
- "emu_sys_cm:clk:0000:22",
+ "emu-sys-clkctrl:0000:22",
NULL,
};
@@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
};
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
- "emu_sys_cm:clk:0000:20",
+ "emu-sys-clkctrl:0000:20",
NULL,
};
@@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = {
* hwmod support. Once hwmod is removed, these can be removed
* also.
*/
- DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
- DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
- DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
- DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
- DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
- DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
- DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
- DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
- DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
- DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
- DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
- DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
- DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
- DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
- DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
- DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
- DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
- DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
- DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
- DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
- DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
- DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
- DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
- DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
- DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
- DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
- DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
- DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
- DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
- DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
- DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
- DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
- DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
- DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
- DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
- DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
- DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
- DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
- DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
- DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
- DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
- DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
- DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
- DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
- DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
- DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
- DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
- DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
- DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
- DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
- DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
- DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
- DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
+ DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
+ DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
+ DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
+ DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
+ DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
+ DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
+ DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
+ DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
+ DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
+ DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
+ DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
+ DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
+ DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
+ DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
+ DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
+ DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
+ DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
+ DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
+ DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
+ DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
+ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
+ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
+ DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
+ DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
+ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
+ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
+ DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
+ DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
+ DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
+ DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
+ DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
+ DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
+ DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
+ DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
+ DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
+ DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
+ DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
+ DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
+ DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
+ DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
+ DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
{ .node_name = NULL },
};
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -50,7 +50,7 @@ static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
};
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
- "abe_cm:clk:0018:26",
+ "abe-clkctrl:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -70,7 +70,7 @@ static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
};
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
- "abe_cm:clk:0028:26",
+ "abe-clkctrl:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -83,7 +83,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst =
};
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
- "abe_cm:clk:0030:26",
+ "abe-clkctrl:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -96,7 +96,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst =
};
static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
- "abe_cm:clk:0038:26",
+ "abe-clkctrl:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -136,16 +136,16 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
- { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
+ { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
- { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
- { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
- { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
- { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
- { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
- { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
- { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
- { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
+ { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
+ { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
+ { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
+ { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
+ { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
+ { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
+ { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
+ { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
{ 0 },
};
@@ -268,12 +268,12 @@ static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
- { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
- { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
- { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
- { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
- { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
- { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
+ { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
+ { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
+ { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
+ { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
+ { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
+ { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
@@ -345,7 +345,7 @@ static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
- { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
+ { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
{ 0 },
};
@@ -378,7 +378,7 @@ static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
- { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
+ { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
{ 0 },
};
@@ -389,7 +389,7 @@ static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
};
static const char * const omap5_mmc1_fclk_parents[] __initconst = {
- "l3init_cm:clk:0008:24",
+ "l3init-clkctrl:0008:24",
NULL,
};
@@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
};
static const char * const omap5_mmc2_fclk_parents[] __initconst = {
- "l3init_cm:clk:0010:24",
+ "l3init-clkctrl:0010:24",
NULL,
};
@@ -430,12 +430,12 @@ static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initcons
};
static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
- "l3init_cm:clk:0038:24",
+ "l3init-clkctrl:0038:24",
NULL,
};
static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
- "l3init_cm:clk:0038:25",
+ "l3init-clkctrl:0038:25",
NULL,
};
@@ -494,8 +494,8 @@ static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initcons
};
static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
- { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
- { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
+ { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
+ { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
@@ -519,7 +519,7 @@ static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initcon
{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
- { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
+ { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
@@ -549,58 +549,58 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
- DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
- DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
- DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
- DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
- DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
- DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
- DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
- DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
- DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
- DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
- DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
- DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
- DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
- DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
- DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
- DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
- DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
- DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
- DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
- DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
- DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
- DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
- DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
- DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
- DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
- DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
- DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
- DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
- DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
- DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
- DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
- DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
- DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
- DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
- DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
+ DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
+ DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
+ DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
+ DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
+ DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
+ DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
+ DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
+ DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
+ DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
+ DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
+ DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
+ DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
+ DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
{ .node_name = NULL },
};
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -529,10 +529,6 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
char *c;
u16 soc_mask = 0;
- if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
- of_node_name_eq(node, "clk"))
- ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
-
addrp = of_get_address(node, 0, NULL, NULL);
addr = (u32)of_translate_address(node, addrp);
--
2.35.1
^ permalink raw reply [flat|nested] 9+ messages in thread