Re: [PATCH v4 03/11] hte: Add tegra194 HTE kernel provider

From: kernel test robot <lkp@intel.com>
To: Dipen Patel <dipenp@nvidia.com>
Cc: llvm@lists.linux.dev, kbuild-all@lists.01.org
Subject: Re: [PATCH v4 03/11] hte: Add tegra194 HTE kernel provider
Date: Sat, 5 Feb 2022 01:58:56 +0800	[thread overview]
Message-ID: <202202050111.cOZMMgeY-lkp@intel.com> (raw)
In-Reply-To: <20220201222630.21246-4-dipenp@nvidia.com>

Hi Dipen,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on 07f8c60fe60f84977dc815ec8a6b1100827c34dd]

url:    https://github.com/0day-ci/linux/commits/Dipen-Patel/Intro-to-Hardware-timestamping-engine/20220202-062447
base:   07f8c60fe60f84977dc815ec8a6b1100827c34dd
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20220205/202202050111.cOZMMgeY-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project a73e4ce6a59b01f0e37037761c1e6889d539d233)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/6a6a517b6866ae7e4b1b878ab82312a9a2dc5b90
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dipen-Patel/Intro-to-Hardware-timestamping-engine/20220202-062447
        git checkout 6a6a517b6866ae7e4b1b878ab82312a9a2dc5b90
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/hte/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/hte/hte-tegra194.c:379:9: error: implicit declaration of function 'gpiod_enable_hw_timestamp' [-Werror,-Wimplicit-function-declaration]
                   ret = gpiod_enable_hw_timestamp(attr->line_data,
                         ^
   drivers/hte/hte-tegra194.c:405:9: error: implicit declaration of function 'gpiod_disable_hw_timestamp' [-Werror,-Wimplicit-function-declaration]
                   ret = gpiod_disable_hw_timestamp(attr->line_data,
                         ^
>> drivers/hte/hte-tegra194.c:431:5: warning: no previous prototype for function 'tegra_hte_get_level' [-Wmissing-prototypes]
   int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id)
       ^
   drivers/hte/hte-tegra194.c:431:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id)
   ^
   static 
>> drivers/hte/hte-tegra194.c:486:6: warning: no previous prototype for function 'tegra_hte_match_from_linedata' [-Wmissing-prototypes]
   bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
        ^
   drivers/hte/hte-tegra194.c:486:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
   ^
   static 
   2 warnings and 2 errors generated.

vim +/tegra_hte_get_level +431 drivers/hte/hte-tegra194.c

   430	
 > 431	int tegra_hte_get_level(struct tegra_hte_soc *gs, u32 line_id)
   432	{
   433		struct gpio_desc *desc;
   434	
   435		if (gs->prov_data->type == HTE_TEGRA_TYPE_GPIO) {
   436			desc = gs->line_data[line_id].data;
   437			if (desc)
   438				return gpiod_get_raw_value(desc);
   439		}
   440	
   441		return -1;
   442	}
   443	
   444	static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)
   445	{
   446		u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;
   447		u64 tsc;
   448		struct hte_ts_data el;
   449	
   450		while ((tegra_hte_readl(gs, HTE_TESTATUS) >>
   451			HTE_TESTATUS_OCCUPANCY_SHIFT) &
   452			HTE_TESTATUS_OCCUPANCY_MASK) {
   453			tsh = tegra_hte_readl(gs, HTE_TETSCH);
   454			tsl = tegra_hte_readl(gs, HTE_TETSCL);
   455			tsc = (((u64)tsh << 32) | tsl);
   456	
   457			src = tegra_hte_readl(gs, HTE_TESRC);
   458			slice = (src >> HTE_TESRC_SLICE_SHIFT) &
   459				    HTE_TESRC_SLICE_DEFAULT_MASK;
   460	
   461			pv = tegra_hte_readl(gs, HTE_TEPCV);
   462			cv = tegra_hte_readl(gs, HTE_TECCV);
   463			acv = pv ^ cv;
   464			while (acv) {
   465				bit_index = __builtin_ctz(acv);
   466				line_id = bit_index + (slice << 5);
   467				el.tsc = tsc << HTE_TS_NS_SHIFT;
   468				el.raw_level = tegra_hte_get_level(gs, line_id);
   469				hte_push_ts_ns(gs->chip, line_id, &el);
   470				acv &= ~BIT(bit_index);
   471			}
   472			tegra_hte_writel(gs, HTE_TECMD, HTE_TECMD_CMD_POP);
   473		}
   474	}
   475	
   476	static irqreturn_t tegra_hte_isr(int irq, void *dev_id)
   477	{
   478		struct tegra_hte_soc *gs = dev_id;
   479		(void)irq;
   480	
   481		tegra_hte_read_fifo(gs);
   482	
   483		return IRQ_HANDLED;
   484	}
   485	
 > 486	bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
   487					   const struct hte_ts_desc *hdesc)
   488	{
   489		struct tegra_hte_soc *hte_dev = chip->data;
   490	
   491		if (!hte_dev || (hte_dev->prov_data->type != HTE_TEGRA_TYPE_GPIO))
   492			return false;
   493	
   494		return hte_dev->c == gpiod_to_chip(hdesc->attr.line_data);
   495	}
   496	

---
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