From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v6 02/14] riscv: integrate alternatives better into the main architecture Date: Wed, 9 Feb 2022 13:37:48 +0100 [thread overview] Message-ID: <20220209123800.269774-3-heiko@sntech.de> (raw) In-Reply-To: <20220209123800.269774-1-heiko@sntech.de> Right now the alternatives need to be explicitly enabled and erratas are limited to SiFive ones. Over time with more SoCs and additional RiscV extensions, many more erratas or other patch-worthy features will emerge, so it doesn't really make sense to have the core alternatives able to get deactivated. So make it part of the core RiscV kernel and drop the main RISCV_ERRATA_ALTERNATIVES config symbol. This mimics how i.e. arm64 handles its alternatives implementation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/Kconfig.erratas | 10 ---------- arch/riscv/Kconfig.socs | 1 - arch/riscv/Makefile | 2 +- arch/riscv/errata/Makefile | 1 - arch/riscv/include/asm/alternative-macros.h | 22 --------------------- arch/riscv/kernel/Makefile | 1 + arch/riscv/{errata => kernel}/alternative.c | 0 arch/riscv/kernel/smpboot.c | 2 -- arch/riscv/kernel/traps.c | 2 +- 9 files changed, 3 insertions(+), 38 deletions(-) rename arch/riscv/{errata => kernel}/alternative.c (100%) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index b44d6ecdb46e..d18be8ff0245 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,17 +1,7 @@ menu "CPU errata selection" -config RISCV_ERRATA_ALTERNATIVE - bool "RISC-V alternative scheme" - default y - help - This Kconfig allows the kernel to automatically patch the - errata required by the execution platform at run time. The - code patching is performed once in the boot stages. It means - that the overhead from this mechanism is just taken once. - config ERRATA_SIFIVE bool "SiFive errata" - depends on RISCV_ERRATA_ALTERNATIVE help All SiFive errata Kconfig depend on this Kconfig. Disabling this Kconfig will disable all SiFive errata. Please say "Y" diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6ec44a22278a..3df7f7ed0d81 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -14,7 +14,6 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_PRCI select SIFIVE_PLIC - select RISCV_ERRATA_ALTERNATIVE select ERRATA_SIFIVE help This enables support for SiFive SoC platform hardware. diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8a107ed18b0d..194220889969 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -97,7 +97,7 @@ endif head-y := arch/riscv/kernel/head.o -core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/ +core-y += arch/riscv/errata/ core-$(CONFIG_KVM) += arch/riscv/kvm/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index b8f8740a3e44..0ca1c5281a2d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1 @@ -obj-y += alternative.o obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 67406c376389..92da6b3920a3 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -2,8 +2,6 @@ #ifndef __ASM_ALTERNATIVE_MACROS_H #define __ASM_ALTERNATIVE_MACROS_H -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE - #ifdef __ASSEMBLY__ .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len @@ -76,26 +74,6 @@ #endif /* __ASSEMBLY__ */ -#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/ -#ifdef __ASSEMBLY__ - -.macro __ALTERNATIVE_CFG old_c - \old_c -.endm - -#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ - __ALTERNATIVE_CFG old_c - -#else /* !__ASSEMBLY__ */ - -#define __ALTERNATIVE_CFG(old_c) \ - old_c "\n" - -#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ - __ALTERNATIVE_CFG(old_c) - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */ /* * Usage: * ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 612556faa527..3ea2d133887d 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -18,6 +18,7 @@ extra-y += head.o extra-y += vmlinux.lds obj-y += soc.o +obj-y += alternative.o obj-y += cpu.o obj-y += cpufeature.o obj-y += entry.o diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c similarity index 100% rename from arch/riscv/errata/alternative.c rename to arch/riscv/kernel/alternative.c diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..a6d13dca1403 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE apply_boot_alternatives(); -#endif } void __init smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index fe92e119e6a3..9984c8622c3b 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, } } -#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE) +#if defined (CONFIG_XIP_KERNEL) #define __trap_section __section(".xip.traps") #else #define __trap_section -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v6 02/14] riscv: integrate alternatives better into the main architecture Date: Wed, 9 Feb 2022 13:37:48 +0100 [thread overview] Message-ID: <20220209123800.269774-3-heiko@sntech.de> (raw) In-Reply-To: <20220209123800.269774-1-heiko@sntech.de> Right now the alternatives need to be explicitly enabled and erratas are limited to SiFive ones. Over time with more SoCs and additional RiscV extensions, many more erratas or other patch-worthy features will emerge, so it doesn't really make sense to have the core alternatives able to get deactivated. So make it part of the core RiscV kernel and drop the main RISCV_ERRATA_ALTERNATIVES config symbol. This mimics how i.e. arm64 handles its alternatives implementation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/Kconfig.erratas | 10 ---------- arch/riscv/Kconfig.socs | 1 - arch/riscv/Makefile | 2 +- arch/riscv/errata/Makefile | 1 - arch/riscv/include/asm/alternative-macros.h | 22 --------------------- arch/riscv/kernel/Makefile | 1 + arch/riscv/{errata => kernel}/alternative.c | 0 arch/riscv/kernel/smpboot.c | 2 -- arch/riscv/kernel/traps.c | 2 +- 9 files changed, 3 insertions(+), 38 deletions(-) rename arch/riscv/{errata => kernel}/alternative.c (100%) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index b44d6ecdb46e..d18be8ff0245 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -1,17 +1,7 @@ menu "CPU errata selection" -config RISCV_ERRATA_ALTERNATIVE - bool "RISC-V alternative scheme" - default y - help - This Kconfig allows the kernel to automatically patch the - errata required by the execution platform at run time. The - code patching is performed once in the boot stages. It means - that the overhead from this mechanism is just taken once. - config ERRATA_SIFIVE bool "SiFive errata" - depends on RISCV_ERRATA_ALTERNATIVE help All SiFive errata Kconfig depend on this Kconfig. Disabling this Kconfig will disable all SiFive errata. Please say "Y" diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6ec44a22278a..3df7f7ed0d81 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -14,7 +14,6 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_PRCI select SIFIVE_PLIC - select RISCV_ERRATA_ALTERNATIVE select ERRATA_SIFIVE help This enables support for SiFive SoC platform hardware. diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8a107ed18b0d..194220889969 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -97,7 +97,7 @@ endif head-y := arch/riscv/kernel/head.o -core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/ +core-y += arch/riscv/errata/ core-$(CONFIG_KVM) += arch/riscv/kvm/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index b8f8740a3e44..0ca1c5281a2d 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1,2 +1 @@ -obj-y += alternative.o obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 67406c376389..92da6b3920a3 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -2,8 +2,6 @@ #ifndef __ASM_ALTERNATIVE_MACROS_H #define __ASM_ALTERNATIVE_MACROS_H -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE - #ifdef __ASSEMBLY__ .macro ALT_ENTRY oldptr newptr vendor_id errata_id new_len @@ -76,26 +74,6 @@ #endif /* __ASSEMBLY__ */ -#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/ -#ifdef __ASSEMBLY__ - -.macro __ALTERNATIVE_CFG old_c - \old_c -.endm - -#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ - __ALTERNATIVE_CFG old_c - -#else /* !__ASSEMBLY__ */ - -#define __ALTERNATIVE_CFG(old_c) \ - old_c "\n" - -#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ - __ALTERNATIVE_CFG(old_c) - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */ /* * Usage: * ALTERNATIVE(old_content, new_content, vendor_id, errata_id, CONFIG_k) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 612556faa527..3ea2d133887d 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -18,6 +18,7 @@ extra-y += head.o extra-y += vmlinux.lds obj-y += soc.o +obj-y += alternative.o obj-y += cpu.o obj-y += cpufeature.o obj-y += entry.o diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/kernel/alternative.c similarity index 100% rename from arch/riscv/errata/alternative.c rename to arch/riscv/kernel/alternative.c diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..a6d13dca1403 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -41,9 +41,7 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); -#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE apply_boot_alternatives(); -#endif } void __init smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index fe92e119e6a3..9984c8622c3b 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -86,7 +86,7 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, } } -#if defined (CONFIG_XIP_KERNEL) && defined (CONFIG_RISCV_ERRATA_ALTERNATIVE) +#if defined (CONFIG_XIP_KERNEL) #define __trap_section __section(".xip.traps") #else #define __trap_section -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-02-09 12:39 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-09 12:37 [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-11 1:59 ` Atish Patra 2022-02-11 1:59 ` Atish Patra 2022-02-09 12:37 ` Heiko Stuebner [this message] 2022-02-09 12:37 ` [PATCH v6 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 03/14] riscv: allow different stages with alternatives Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 04/14] riscv: implement module alternatives Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-03-08 0:47 ` Palmer Dabbelt 2022-03-08 0:47 ` Palmer Dabbelt 2022-02-09 12:37 ` [PATCH v6 08/14] riscv: move boot alternatives to a slightly earlier position Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-10 22:42 ` Atish Patra 2022-02-10 22:42 ` Atish Patra 2022-02-11 1:11 ` Heiko Stübner 2022-02-11 1:11 ` Heiko Stübner 2022-02-11 1:57 ` Atish Patra 2022-02-11 1:57 ` Atish Patra 2022-02-11 9:34 ` Heiko Stübner 2022-02-11 9:34 ` Heiko Stübner 2022-03-08 0:47 ` Palmer Dabbelt 2022-03-08 0:47 ` Palmer Dabbelt 2022-03-23 16:51 ` Heiko Stübner 2022-03-23 16:51 ` Heiko Stübner 2022-02-09 12:37 ` [PATCH v6 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 18:47 ` Rob Herring 2022-02-09 18:47 ` Rob Herring 2022-02-09 12:37 ` [PATCH v6 12/14] riscv: add RISC-V Svpbmt extension support Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:37 ` [PATCH v6 13/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner 2022-02-09 12:37 ` Heiko Stuebner 2022-02-09 12:38 ` [PATCH v6 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner 2022-02-09 12:38 ` Heiko Stuebner 2022-02-11 0:12 ` Atish Patra 2022-02-11 0:12 ` Atish Patra 2022-02-11 9:25 ` Heiko Stübner 2022-02-11 9:25 ` Heiko Stübner 2022-02-12 0:27 ` Atish Patra 2022-02-12 0:27 ` Atish Patra 2022-02-11 2:01 ` Atish Patra 2022-02-11 2:01 ` Atish Patra 2022-02-14 3:42 ` Samuel Holland 2022-02-14 3:42 ` Samuel Holland 2022-02-09 17:49 ` [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types Jisheng Zhang 2022-02-09 17:49 ` Jisheng Zhang 2022-02-09 23:44 ` Heiko Stübner 2022-02-09 23:44 ` Heiko Stübner 2022-02-10 16:01 ` Jisheng Zhang 2022-02-10 16:01 ` Jisheng Zhang 2022-02-11 0:25 ` Atish Patra 2022-02-11 0:25 ` Atish Patra 2022-02-11 1:48 ` Atish Patra 2022-02-11 1:48 ` Atish Patra 2022-02-11 2:04 ` Heiko Stübner 2022-02-11 2:04 ` Heiko Stübner 2022-02-12 0:25 ` Atish Patra 2022-02-12 0:25 ` Atish Patra 2022-02-14 20:02 ` Heiko Stübner 2022-02-14 20:02 ` Heiko Stübner 2022-02-14 20:25 ` Atish Patra 2022-02-14 20:25 ` Atish Patra 2022-02-14 20:37 ` Heiko Stübner 2022-02-14 20:37 ` Heiko Stübner 2022-03-09 7:56 ` Guo Ren 2022-03-09 7:56 ` Guo Ren
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220209123800.269774-3-heiko@sntech.de \ --to=heiko@sntech.de \ --cc=allen.baum@esperantotech.com \ --cc=andrea.mondelli@huawei.com \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=arnd@arndb.de \ --cc=atishp@atishpatra.org \ --cc=behrensj@mit.edu \ --cc=cmuellner@linux.com \ --cc=devicetree@vger.kernel.org \ --cc=drew@beagleboard.org \ --cc=gfavor@ventanamicro.com \ --cc=guoren@kernel.org \ --cc=hch@lst.de \ --cc=huffman@cadence.com \ --cc=jscheid@ventanamicro.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=liush@allwinnertech.com \ --cc=maxime@cerno.tech \ --cc=mick@ics.forth.gr \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=philipp.tomsich@vrull.eu \ --cc=robh+dt@kernel.org \ --cc=rtrauben@gmail.com \ --cc=samuel@sholland.org \ --cc=wefu@redhat.com \ --cc=wens@csie.org \ --cc=xinhaoqu@huawei.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.