From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>, lazyparser@gmail.com, ardxwe@gmail.com Subject: [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Date: Fri, 11 Feb 2022 12:39:14 +0800 [thread overview] Message-ID: <20220211043920.28981-1-liweiwei@iscas.ac.cn> (raw) This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. Specification: https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v6 To test this implementation, specify cpu argument with 'zfinx =true,zdinx=true,zhinx=true,zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/. v6: * rename flags Z*inx to z*inx * rebase on apply-to-riscv.next v5: * put definition of ftemp and nftemp together, add comments for them * sperate the declare of variable i from loop v4: * combine register pair check for rv32 zdinx * clear mstatus.FS when RVF is disabled by write_misa v3: * delete unused reset for mstatus.FS * use positive test for RVF instead of negative test for ZFINX * replace get_ol with get_xl * use tcg_gen_concat_tl_i64 to unify tcg_gen_concat_i32_i64 and tcg_gen_deposit_i64 v2: * hardwire mstatus.FS to zero when enable zfinx * do register-pair check at the begin of translation * optimize partial implemention as suggested Weiwei Li (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv/cpu.c | 17 ++ target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c | 25 +- target/riscv/fpu_helper.c | 178 ++++++------ target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 285 ++++++++++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- target/riscv/internals.h | 32 ++- target/riscv/translate.c | 149 +++++++++- 11 files changed, 974 insertions(+), 372 deletions(-) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, ardxwe@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Date: Fri, 11 Feb 2022 12:39:14 +0800 [thread overview] Message-ID: <20220211043920.28981-1-liweiwei@iscas.ac.cn> (raw) This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. Specification: https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v6 To test this implementation, specify cpu argument with 'zfinx =true,zdinx=true,zhinx=true,zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/. v6: * rename flags Z*inx to z*inx * rebase on apply-to-riscv.next v5: * put definition of ftemp and nftemp together, add comments for them * sperate the declare of variable i from loop v4: * combine register pair check for rv32 zdinx * clear mstatus.FS when RVF is disabled by write_misa v3: * delete unused reset for mstatus.FS * use positive test for RVF instead of negative test for ZFINX * replace get_ol with get_xl * use tcg_gen_concat_tl_i64 to unify tcg_gen_concat_i32_i64 and tcg_gen_deposit_i64 v2: * hardwire mstatus.FS to zero when enable zfinx * do register-pair check at the begin of translation * optimize partial implemention as suggested Weiwei Li (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv/cpu.c | 17 ++ target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c | 25 +- target/riscv/fpu_helper.c | 178 ++++++------ target/riscv/helper.h | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 285 ++++++++++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- target/riscv/internals.h | 32 ++- target/riscv/translate.c | 149 +++++++++- 11 files changed, 974 insertions(+), 372 deletions(-) -- 2.17.1
next reply other threads:[~2022-02-11 4:50 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-11 4:39 Weiwei Li [this message] 2022-02-11 4:39 ` [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li 2022-02-11 4:39 ` [PATCH v6 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-11 4:39 ` [PATCH v6 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-11 4:39 ` [PATCH v6 3/6] target/riscv: add support for zfinx Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 3:55 ` Alistair Francis 2022-02-28 3:55 ` Alistair Francis 2022-02-11 4:39 ` [PATCH v6 4/6] target/riscv: add support for zdinx Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 4:01 ` Alistair Francis 2022-02-28 4:01 ` Alistair Francis 2022-02-11 4:39 ` [PATCH v6 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 4:09 ` Alistair Francis 2022-02-28 4:09 ` Alistair Francis 2022-02-11 4:39 ` [PATCH v6 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 8:27 ` [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Alistair Francis 2022-02-28 8:27 ` Alistair Francis
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