From: Alistair Francis <alistair23@gmail.com> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: "Wei Wu (吴伟)" <lazyparser@gmail.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, wangjunqiang <wangjunqiang@iscas.ac.cn>, "Bin Meng" <bin.meng@windriver.com>, "Richard Henderson" <richard.henderson@linaro.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, ardxwe@gmail.com, "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com> Subject: Re: [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Date: Mon, 28 Feb 2022 18:27:25 +1000 [thread overview] Message-ID: <CAKmqyKOAwdwcCMqAYZ+EjZmLaHg8mVOxf+_MYxx05rVLSzBUjA@mail.gmail.com> (raw) In-Reply-To: <20220211043920.28981-1-liweiwei@iscas.ac.cn> On Fri, Feb 11, 2022 at 2:49 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. > > Specification: > https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v6 > > To test this implementation, specify cpu argument with 'zfinx =true,zdinx=true,zhinx=true,zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' > This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/. > > v6: > * rename flags Z*inx to z*inx > * rebase on apply-to-riscv.next > > v5: > * put definition of ftemp and nftemp together, add comments for them > * sperate the declare of variable i from loop > > v4: > * combine register pair check for rv32 zdinx > * clear mstatus.FS when RVF is disabled by write_misa > > v3: > * delete unused reset for mstatus.FS > * use positive test for RVF instead of negative test for ZFINX > * replace get_ol with get_xl > * use tcg_gen_concat_tl_i64 to unify tcg_gen_concat_i32_i64 and tcg_gen_deposit_i64 > > v2: > * hardwire mstatus.FS to zero when enable zfinx > * do register-pair check at the begin of translation > * optimize partial implemention as suggested > > Weiwei Li (6): > target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} > target/riscv: hardwire mstatus.FS to zero when enable zfinx > target/riscv: add support for zfinx > target/riscv: add support for zdinx > target/riscv: add support for zhinx/zhinxmin > target/riscv: expose zfinx, zdinx, zhinx{min} properties Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 17 ++ > target/riscv/cpu.h | 4 + > target/riscv/cpu_helper.c | 6 +- > target/riscv/csr.c | 25 +- > target/riscv/fpu_helper.c | 178 ++++++------ > target/riscv/helper.h | 4 +- > target/riscv/insn_trans/trans_rvd.c.inc | 285 ++++++++++++++----- > target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- > target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- > target/riscv/internals.h | 32 ++- > target/riscv/translate.c | 149 +++++++++- > 11 files changed, 974 insertions(+), 372 deletions(-) > > -- > 2.17.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Weiwei Li <liweiwei@iscas.ac.cn> Cc: "Richard Henderson" <richard.henderson@linaro.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" <alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wangjunqiang <wangjunqiang@iscas.ac.cn>, "Wei Wu (吴伟)" <lazyparser@gmail.com>, ardxwe@gmail.com Subject: Re: [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Date: Mon, 28 Feb 2022 18:27:25 +1000 [thread overview] Message-ID: <CAKmqyKOAwdwcCMqAYZ+EjZmLaHg8mVOxf+_MYxx05rVLSzBUjA@mail.gmail.com> (raw) In-Reply-To: <20220211043920.28981-1-liweiwei@iscas.ac.cn> On Fri, Feb 11, 2022 at 2:49 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. > > Specification: > https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v6 > > To test this implementation, specify cpu argument with 'zfinx =true,zdinx=true,zhinx=true,zhinxmin=true' with 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' > This implementation can pass gcc tests, ci result can be found in https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/. > > v6: > * rename flags Z*inx to z*inx > * rebase on apply-to-riscv.next > > v5: > * put definition of ftemp and nftemp together, add comments for them > * sperate the declare of variable i from loop > > v4: > * combine register pair check for rv32 zdinx > * clear mstatus.FS when RVF is disabled by write_misa > > v3: > * delete unused reset for mstatus.FS > * use positive test for RVF instead of negative test for ZFINX > * replace get_ol with get_xl > * use tcg_gen_concat_tl_i64 to unify tcg_gen_concat_i32_i64 and tcg_gen_deposit_i64 > > v2: > * hardwire mstatus.FS to zero when enable zfinx > * do register-pair check at the begin of translation > * optimize partial implemention as suggested > > Weiwei Li (6): > target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} > target/riscv: hardwire mstatus.FS to zero when enable zfinx > target/riscv: add support for zfinx > target/riscv: add support for zdinx > target/riscv: add support for zhinx/zhinxmin > target/riscv: expose zfinx, zdinx, zhinx{min} properties Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 17 ++ > target/riscv/cpu.h | 4 + > target/riscv/cpu_helper.c | 6 +- > target/riscv/csr.c | 25 +- > target/riscv/fpu_helper.c | 178 ++++++------ > target/riscv/helper.h | 4 +- > target/riscv/insn_trans/trans_rvd.c.inc | 285 ++++++++++++++----- > target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- > target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- > target/riscv/internals.h | 32 ++- > target/riscv/translate.c | 149 +++++++++- > 11 files changed, 974 insertions(+), 372 deletions(-) > > -- > 2.17.1 > >
next prev parent reply other threads:[~2022-02-28 8:31 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-11 4:39 [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-11 4:39 ` [PATCH v6 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-11 4:39 ` [PATCH v6 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-11 4:39 ` [PATCH v6 3/6] target/riscv: add support for zfinx Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 3:55 ` Alistair Francis 2022-02-28 3:55 ` Alistair Francis 2022-02-11 4:39 ` [PATCH v6 4/6] target/riscv: add support for zdinx Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 4:01 ` Alistair Francis 2022-02-28 4:01 ` Alistair Francis 2022-02-11 4:39 ` [PATCH v6 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 4:09 ` Alistair Francis 2022-02-28 4:09 ` Alistair Francis 2022-02-11 4:39 ` [PATCH v6 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties Weiwei Li 2022-02-11 4:39 ` Weiwei Li 2022-02-28 8:27 ` Alistair Francis [this message] 2022-02-28 8:27 ` [PATCH v6 0/6] support subsets of Float-Point in Integer Registers extensions Alistair Francis
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=CAKmqyKOAwdwcCMqAYZ+EjZmLaHg8mVOxf+_MYxx05rVLSzBUjA@mail.gmail.com \ --to=alistair23@gmail.com \ --cc=alistair.francis@wdc.com \ --cc=ardxwe@gmail.com \ --cc=bin.meng@windriver.com \ --cc=lazyparser@gmail.com \ --cc=liweiwei@iscas.ac.cn \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ --cc=wangjunqiang@iscas.ac.cn \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.