From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: Stephen Boyd <swboyd@chromium.org>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v5 2/5] drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link") Date: Thu, 17 Feb 2022 08:55:26 +0300 [thread overview] Message-ID: <20220217055529.499829-3-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20220217055529.499829-1-dmitry.baryshkov@linaro.org> "ctrl_link" is the clock from DP_CTRL_PM module. The result of setting the rate for it would be a call to dev_pm_opp_set_rate(). Instead of saving the rate inside struct dss_module_power, call the devm_pm_opp_set_rate() directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 7 +++++-- drivers/gpu/drm/msm/dp/dp_power.c | 33 +------------------------------ 2 files changed, 6 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index c724cb0bde9d..07f6bf7e1acb 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1332,12 +1332,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100; opts_dp->ssc = drm_dp_max_downspread(dpcd); - dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", - ctrl->link->link_params.rate * 1000); phy_configure(phy, &dp_io->phy_opts); phy_power_on(phy); + dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); if (ret) DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); @@ -1451,6 +1450,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) * link clock might have been adjusted as part of the * link maintenance. */ + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); @@ -1482,6 +1482,7 @@ static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_reset(ctrl->catalog); + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); @@ -1887,6 +1888,7 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) } } + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); @@ -1942,6 +1944,7 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl) if (ret) DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index b48b45e92bfa..893a57dd97d9 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -150,44 +150,13 @@ static int dp_power_clk_deinit(struct dp_power_private *power) return 0; } -static int dp_power_clk_set_link_rate(struct dp_power_private *power, - struct dss_clk *clk_arry, int num_clk, int enable) -{ - u32 rate; - int i, rc = 0; - - for (i = 0; i < num_clk; i++) { - if (clk_arry[i].clk) { - if (clk_arry[i].type == DSS_CLK_PCLK) { - if (enable) - rate = clk_arry[i].rate; - else - rate = 0; - - rc = dev_pm_opp_set_rate(power->dev, rate); - if (rc) - break; - } - - } - } - return rc; -} - static int dp_power_clk_set_rate(struct dp_power_private *power, enum dp_pm_type module, bool enable) { int rc = 0; struct dss_module_power *mp = &power->parser->mp[module]; - if (module == DP_CTRL_PM) { - rc = dp_power_clk_set_link_rate(power, mp->clk_config, mp->num_clk, enable); - if (rc) { - DRM_ERROR("failed to set link clks rate\n"); - return rc; - } - } else { - + if (module != DP_CTRL_PM) { if (enable) { rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); if (rc) { -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Bjorn Andersson <bjorn.andersson@linaro.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Abhinav Kumar <quic_abhinavk@quicinc.com> Cc: David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd <swboyd@chromium.org>, freedreno@lists.freedesktop.org Subject: [PATCH v5 2/5] drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link") Date: Thu, 17 Feb 2022 08:55:26 +0300 [thread overview] Message-ID: <20220217055529.499829-3-dmitry.baryshkov@linaro.org> (raw) In-Reply-To: <20220217055529.499829-1-dmitry.baryshkov@linaro.org> "ctrl_link" is the clock from DP_CTRL_PM module. The result of setting the rate for it would be a call to dev_pm_opp_set_rate(). Instead of saving the rate inside struct dss_module_power, call the devm_pm_opp_set_rate() directly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 7 +++++-- drivers/gpu/drm/msm/dp/dp_power.c | 33 +------------------------------ 2 files changed, 6 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index c724cb0bde9d..07f6bf7e1acb 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1332,12 +1332,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100; opts_dp->ssc = drm_dp_max_downspread(dpcd); - dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", - ctrl->link->link_params.rate * 1000); phy_configure(phy, &dp_io->phy_opts); phy_power_on(phy); + dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); if (ret) DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); @@ -1451,6 +1450,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) * link clock might have been adjusted as part of the * link maintenance. */ + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); @@ -1482,6 +1482,7 @@ static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_reset(ctrl->catalog); + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); @@ -1887,6 +1888,7 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) } } + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); @@ -1942,6 +1944,7 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl) if (ret) DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index b48b45e92bfa..893a57dd97d9 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -150,44 +150,13 @@ static int dp_power_clk_deinit(struct dp_power_private *power) return 0; } -static int dp_power_clk_set_link_rate(struct dp_power_private *power, - struct dss_clk *clk_arry, int num_clk, int enable) -{ - u32 rate; - int i, rc = 0; - - for (i = 0; i < num_clk; i++) { - if (clk_arry[i].clk) { - if (clk_arry[i].type == DSS_CLK_PCLK) { - if (enable) - rate = clk_arry[i].rate; - else - rate = 0; - - rc = dev_pm_opp_set_rate(power->dev, rate); - if (rc) - break; - } - - } - } - return rc; -} - static int dp_power_clk_set_rate(struct dp_power_private *power, enum dp_pm_type module, bool enable) { int rc = 0; struct dss_module_power *mp = &power->parser->mp[module]; - if (module == DP_CTRL_PM) { - rc = dp_power_clk_set_link_rate(power, mp->clk_config, mp->num_clk, enable); - if (rc) { - DRM_ERROR("failed to set link clks rate\n"); - return rc; - } - } else { - + if (module != DP_CTRL_PM) { if (enable) { rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); if (rc) { -- 2.34.1
next prev parent reply other threads:[~2022-02-17 5:55 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-17 5:55 [PATCH v5 0/5] drm/msm: rework clock handling Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-02-17 5:55 ` [PATCH v5 1/5] drm/msm/dpu: simplify clocks handling Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:24 ` Stephen Boyd 2022-03-03 22:24 ` Stephen Boyd 2022-02-17 5:55 ` Dmitry Baryshkov [this message] 2022-02-17 5:55 ` [PATCH v5 2/5] drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link") Dmitry Baryshkov 2022-03-03 22:25 ` Stephen Boyd 2022-03-03 22:25 ` Stephen Boyd 2022-02-17 5:55 ` [PATCH v5 3/5] drm/msm/dp: set stream_pixel rate directly Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:32 ` Stephen Boyd 2022-03-03 22:32 ` Stephen Boyd 2022-03-04 4:23 ` Dmitry Baryshkov 2022-03-04 4:23 ` Dmitry Baryshkov 2022-03-04 4:31 ` Stephen Boyd 2022-03-04 4:31 ` Stephen Boyd 2022-03-04 7:58 ` Dmitry Baryshkov 2022-03-04 7:58 ` Dmitry Baryshkov 2022-03-08 20:46 ` Stephen Boyd 2022-03-08 20:46 ` Stephen Boyd 2022-04-19 16:34 ` Dmitry Baryshkov 2022-04-19 16:34 ` Dmitry Baryshkov 2022-04-28 21:49 ` Stephen Boyd 2022-04-28 21:49 ` Stephen Boyd 2022-04-28 21:51 ` Dmitry Baryshkov 2022-04-28 21:51 ` Dmitry Baryshkov 2022-04-29 1:20 ` Stephen Boyd 2022-04-29 1:20 ` Stephen Boyd 2022-04-29 9:44 ` Dmitry Baryshkov 2022-04-29 9:44 ` Dmitry Baryshkov 2022-02-17 5:55 ` [PATCH v5 4/5] drm/msm/dp: inline dp_power_clk_set_rate() Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:32 ` Stephen Boyd 2022-03-03 22:32 ` Stephen Boyd 2022-02-17 5:55 ` [PATCH v5 5/5] drm/msm/dp: rewrite dss_module_power to use bulk clock functions Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:33 ` Stephen Boyd 2022-03-03 22:33 ` Stephen Boyd
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