From: Stephen Boyd <swboyd@chromium.org> To: Abhinav Kumar <quic_abhinavk@quicinc.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH v5 3/5] drm/msm/dp: set stream_pixel rate directly Date: Thu, 3 Mar 2022 14:32:12 -0800 [thread overview] Message-ID: <CAE-0n529mx1ke89iw8xXZEDcs0z84hA09B31cWeVQSTU9RAAYg@mail.gmail.com> (raw) In-Reply-To: <20220217055529.499829-4-dmitry.baryshkov@linaro.org> Quoting Dmitry Baryshkov (2022-02-16 21:55:27) > The only clock for which we set the rate is the "stream_pixel". Rather > than storing the rate and then setting it by looping over all the > clocks, set the clock rate directly. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [...] > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 07f6bf7e1acb..8e6361dedd77 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1315,7 +1315,7 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, > DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); > > if (num) > - cfg->rate = rate; > + clk_set_rate(cfg->clk, rate); This looks bad. From what I can tell we set the rate of the pixel clk after enabling the phy and configuring it. See the order of operations in dp_ctrl_enable_mainlink_clocks() and note how dp_power_clk_enable() is the one that eventually sets a rate through dp_power_clk_set_rate() dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000); phy_configure(phy, &dp_io->phy_opts); phy_power_on(phy); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); and I vaguely recall that the DP phy needs to be configured for some frequency so that the pixel clk can use it when determining the rate to set. > else > DRM_ERROR("%s clock doesn't exit to set rate %lu\n", > name, rate);
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <swboyd@chromium.org> To: Abhinav Kumar <quic_abhinavk@quicinc.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v5 3/5] drm/msm/dp: set stream_pixel rate directly Date: Thu, 3 Mar 2022 14:32:12 -0800 [thread overview] Message-ID: <CAE-0n529mx1ke89iw8xXZEDcs0z84hA09B31cWeVQSTU9RAAYg@mail.gmail.com> (raw) In-Reply-To: <20220217055529.499829-4-dmitry.baryshkov@linaro.org> Quoting Dmitry Baryshkov (2022-02-16 21:55:27) > The only clock for which we set the rate is the "stream_pixel". Rather > than storing the rate and then setting it by looping over all the > clocks, set the clock rate directly. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [...] > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 07f6bf7e1acb..8e6361dedd77 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1315,7 +1315,7 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, > DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); > > if (num) > - cfg->rate = rate; > + clk_set_rate(cfg->clk, rate); This looks bad. From what I can tell we set the rate of the pixel clk after enabling the phy and configuring it. See the order of operations in dp_ctrl_enable_mainlink_clocks() and note how dp_power_clk_enable() is the one that eventually sets a rate through dp_power_clk_set_rate() dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", ctrl->link->link_params.rate * 1000); phy_configure(phy, &dp_io->phy_opts); phy_power_on(phy); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); and I vaguely recall that the DP phy needs to be configured for some frequency so that the pixel clk can use it when determining the rate to set. > else > DRM_ERROR("%s clock doesn't exit to set rate %lu\n", > name, rate);
next prev parent reply other threads:[~2022-03-03 22:32 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-17 5:55 [PATCH v5 0/5] drm/msm: rework clock handling Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-02-17 5:55 ` [PATCH v5 1/5] drm/msm/dpu: simplify clocks handling Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:24 ` Stephen Boyd 2022-03-03 22:24 ` Stephen Boyd 2022-02-17 5:55 ` [PATCH v5 2/5] drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link") Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:25 ` Stephen Boyd 2022-03-03 22:25 ` Stephen Boyd 2022-02-17 5:55 ` [PATCH v5 3/5] drm/msm/dp: set stream_pixel rate directly Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:32 ` Stephen Boyd [this message] 2022-03-03 22:32 ` Stephen Boyd 2022-03-04 4:23 ` Dmitry Baryshkov 2022-03-04 4:23 ` Dmitry Baryshkov 2022-03-04 4:31 ` Stephen Boyd 2022-03-04 4:31 ` Stephen Boyd 2022-03-04 7:58 ` Dmitry Baryshkov 2022-03-04 7:58 ` Dmitry Baryshkov 2022-03-08 20:46 ` Stephen Boyd 2022-03-08 20:46 ` Stephen Boyd 2022-04-19 16:34 ` Dmitry Baryshkov 2022-04-19 16:34 ` Dmitry Baryshkov 2022-04-28 21:49 ` Stephen Boyd 2022-04-28 21:49 ` Stephen Boyd 2022-04-28 21:51 ` Dmitry Baryshkov 2022-04-28 21:51 ` Dmitry Baryshkov 2022-04-29 1:20 ` Stephen Boyd 2022-04-29 1:20 ` Stephen Boyd 2022-04-29 9:44 ` Dmitry Baryshkov 2022-04-29 9:44 ` Dmitry Baryshkov 2022-02-17 5:55 ` [PATCH v5 4/5] drm/msm/dp: inline dp_power_clk_set_rate() Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:32 ` Stephen Boyd 2022-03-03 22:32 ` Stephen Boyd 2022-02-17 5:55 ` [PATCH v5 5/5] drm/msm/dp: rewrite dss_module_power to use bulk clock functions Dmitry Baryshkov 2022-02-17 5:55 ` Dmitry Baryshkov 2022-03-03 22:33 ` Stephen Boyd 2022-03-03 22:33 ` Stephen Boyd
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