From: Atish Patra <atishp@rivosinc.com> To: qemu-devel@nongnu.org Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Atish Patra <atishp@rivosinc.com>, Palmer Dabbelt <palmer@dabbelt.com>, qemu-riscv@nongnu.org Subject: [PATCH v5 10/12] target/riscv: Add few cache related PMU events Date: Fri, 18 Feb 2022 16:25:16 -0800 [thread overview] Message-ID: <20220219002518.1936806-11-atishp@rivosinc.com> (raw) In-Reply-To: <20220219002518.1936806-1-atishp@rivosinc.com> From: Atish Patra <atish.patra@wdc.com> Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 746335bfd6b9..094d41ba07f7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,10 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu.h" +#include "cpu_bits.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -1174,6 +1177,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_raise_exception(env, cs->exception_index, retaddr); } + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -1270,6 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret = get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, false); -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: qemu-devel@nongnu.org Cc: Atish Patra <atishp@rivosinc.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>, qemu-riscv@nongnu.org Subject: [PATCH v5 10/12] target/riscv: Add few cache related PMU events Date: Fri, 18 Feb 2022 16:25:16 -0800 [thread overview] Message-ID: <20220219002518.1936806-11-atishp@rivosinc.com> (raw) In-Reply-To: <20220219002518.1936806-1-atishp@rivosinc.com> From: Atish Patra <atish.patra@wdc.com> Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 746335bfd6b9..094d41ba07f7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,10 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu.h" +#include "cpu_bits.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -1174,6 +1177,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_raise_exception(env, cs->exception_index, retaddr); } + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -1270,6 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret = get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, false); -- 2.30.2
next prev parent reply other threads:[~2022-02-19 0:35 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-19 0:25 [PATCH v5 00/12] Improve PMU support Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-19 0:25 ` [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-03-03 5:22 ` Alistair Francis 2022-03-03 5:22 ` Alistair Francis 2022-03-03 10:03 ` Atish Kumar Patra 2022-03-03 10:03 ` Atish Kumar Patra 2022-02-19 0:25 ` [PATCH v5 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-19 0:25 ` [PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-19 0:25 ` [PATCH v5 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-19 0:25 ` [PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-19 0:25 ` [PATCH v5 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-28 4:17 ` Alistair Francis 2022-02-28 4:17 ` Alistair Francis 2022-02-19 0:25 ` [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-03-01 6:14 ` Alistair Francis 2022-03-01 6:14 ` Alistair Francis 2022-03-03 20:04 ` Atish Kumar Patra 2022-03-03 20:04 ` Atish Kumar Patra 2022-02-19 0:25 ` [PATCH v5 08/12] target/riscv: Add sscofpmf extension support Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-03-02 22:36 ` Alistair Francis 2022-03-02 22:36 ` Alistair Francis 2022-03-03 20:16 ` Atish Kumar Patra 2022-03-03 20:16 ` Atish Kumar Patra 2022-02-19 0:25 ` [PATCH v5 09/12] target/riscv: Simplify counter predicate function Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-03-02 22:45 ` Alistair Francis 2022-03-02 22:45 ` Alistair Francis 2022-02-19 0:25 ` Atish Patra [this message] 2022-02-19 0:25 ` [PATCH v5 10/12] target/riscv: Add few cache related PMU events Atish Patra 2022-03-02 23:35 ` Alistair Francis 2022-03-02 23:35 ` Alistair Francis 2022-02-19 0:25 ` [PATCH v5 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-02-19 0:25 ` [PATCH v5 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra 2022-02-19 0:25 ` Atish Patra 2022-03-03 3:20 ` [PATCH v5 00/12] Improve PMU support Alistair Francis 2022-03-03 3:20 ` Alistair Francis
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