From: Atish Kumar Patra <atishp@rivosinc.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function
Date: Thu, 3 Mar 2022 02:03:02 -0800 [thread overview]
Message-ID: <CAHBxVyGd4GP-4Vig8An55ck4UVUiBwzMwkBGfAYTxC0G1HWsuQ@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNEy=Kwg3DXmF0C8f+rYGkf0dw2HKLftgf2ejRFROg6nA@mail.gmail.com>
On Wed, Mar 2, 2022 at 9:22 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sat, Feb 19, 2022 at 10:34 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > From: Atish Patra <atish.patra@wdc.com>
> >
> > The predicate function calculates the counter index incorrectly for
> > hpmcounterx. Fix the counter index to reflect correct CSR number.
> >
> > Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
> >
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> > target/riscv/csr.c | 10 ++++++----
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index b16881615997..3799ee850087 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -94,8 +94,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > }
> > break;
> > case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> > - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
> > - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
> > + ctr_index = csrno - CSR_CYCLE;
> > + if (!get_field(env->hcounteren, 1 << ctr_index) &&
> > + get_field(env->mcounteren, 1 << ctr_index)) {
>
> This fails to build:
>
> ../target/riscv/csr.c: In function ‘ctr’:
> ../target/riscv/csr.c:99:13: error: ‘ctr_index’ undeclared (first use
> in this function); did you mean ‘tlb_index’?
> 99 | ctr_index = csrno - CSR_CYCLE;
> | ^~~~~~~~~
> | tlb_index
>
My bad. The ctr_index is defined in PATCH 2. I think I forgot to move
it when I split this one
from PATCH 2. I will send a v6 after addressing your comments on other
patches in this series.
> Alistair
>
> > return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > }
> > break;
> > @@ -121,8 +122,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > }
> > break;
> > case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> > - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
> > - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
> > + ctr_index = csrno - CSR_CYCLEH;
> > + if (!get_field(env->hcounteren, 1 << ctr_index) &&
> > + get_field(env->mcounteren, 1 << ctr_index)) {
> > return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > }
> > break;
> > --
> > 2.30.2
> >
> >
WARNING: multiple messages have this Message-ID (diff)
From: Atish Kumar Patra <atishp@rivosinc.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function
Date: Thu, 3 Mar 2022 02:03:02 -0800 [thread overview]
Message-ID: <CAHBxVyGd4GP-4Vig8An55ck4UVUiBwzMwkBGfAYTxC0G1HWsuQ@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKNEy=Kwg3DXmF0C8f+rYGkf0dw2HKLftgf2ejRFROg6nA@mail.gmail.com>
On Wed, Mar 2, 2022 at 9:22 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sat, Feb 19, 2022 at 10:34 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > From: Atish Patra <atish.patra@wdc.com>
> >
> > The predicate function calculates the counter index incorrectly for
> > hpmcounterx. Fix the counter index to reflect correct CSR number.
> >
> > Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
> >
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> > target/riscv/csr.c | 10 ++++++----
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index b16881615997..3799ee850087 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -94,8 +94,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > }
> > break;
> > case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> > - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
> > - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
> > + ctr_index = csrno - CSR_CYCLE;
> > + if (!get_field(env->hcounteren, 1 << ctr_index) &&
> > + get_field(env->mcounteren, 1 << ctr_index)) {
>
> This fails to build:
>
> ../target/riscv/csr.c: In function ‘ctr’:
> ../target/riscv/csr.c:99:13: error: ‘ctr_index’ undeclared (first use
> in this function); did you mean ‘tlb_index’?
> 99 | ctr_index = csrno - CSR_CYCLE;
> | ^~~~~~~~~
> | tlb_index
>
My bad. The ctr_index is defined in PATCH 2. I think I forgot to move
it when I split this one
from PATCH 2. I will send a v6 after addressing your comments on other
patches in this series.
> Alistair
>
> > return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > }
> > break;
> > @@ -121,8 +122,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> > }
> > break;
> > case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> > - if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
> > - get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
> > + ctr_index = csrno - CSR_CYCLEH;
> > + if (!get_field(env->hcounteren, 1 << ctr_index) &&
> > + get_field(env->mcounteren, 1 << ctr_index)) {
> > return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > }
> > break;
> > --
> > 2.30.2
> >
> >
next prev parent reply other threads:[~2022-03-03 10:06 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-19 0:25 [PATCH v5 00/12] Improve PMU support Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-19 0:25 ` [PATCH v5 01/12] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-03-03 5:22 ` Alistair Francis
2022-03-03 5:22 ` Alistair Francis
2022-03-03 10:03 ` Atish Kumar Patra [this message]
2022-03-03 10:03 ` Atish Kumar Patra
2022-02-19 0:25 ` [PATCH v5 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-19 0:25 ` [PATCH v5 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-19 0:25 ` [PATCH v5 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-19 0:25 ` [PATCH v5 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-19 0:25 ` [PATCH v5 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-28 4:17 ` Alistair Francis
2022-02-28 4:17 ` Alistair Francis
2022-02-19 0:25 ` [PATCH v5 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-03-01 6:14 ` Alistair Francis
2022-03-01 6:14 ` Alistair Francis
2022-03-03 20:04 ` Atish Kumar Patra
2022-03-03 20:04 ` Atish Kumar Patra
2022-02-19 0:25 ` [PATCH v5 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-03-02 22:36 ` Alistair Francis
2022-03-02 22:36 ` Alistair Francis
2022-03-03 20:16 ` Atish Kumar Patra
2022-03-03 20:16 ` Atish Kumar Patra
2022-02-19 0:25 ` [PATCH v5 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-03-02 22:45 ` Alistair Francis
2022-03-02 22:45 ` Alistair Francis
2022-02-19 0:25 ` [PATCH v5 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-03-02 23:35 ` Alistair Francis
2022-03-02 23:35 ` Alistair Francis
2022-02-19 0:25 ` [PATCH v5 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-02-19 0:25 ` [PATCH v5 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-02-19 0:25 ` Atish Patra
2022-03-03 3:20 ` [PATCH v5 00/12] Improve PMU support Alistair Francis
2022-03-03 3:20 ` Alistair Francis
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