* [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc
@ 2022-02-24 13:04 Kamil Konieczny
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs Kamil Konieczny
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: Kamil Konieczny @ 2022-02-24 13:04 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Cc: "Zbigniew Kempczyński" <zbigniew.kempczynski@intel.com>
Kamil Konieczny (2):
lib/intel_batchbuffer: add create without relocs
tests/i915/gem_concurrent_all: Add no-reloc capability
lib/intel_batchbuffer.c | 9 +-
lib/intel_batchbuffer.h | 1 +
tests/i915/gem_concurrent_all.c | 162 +++++++++++++++++++++++++++-----
3 files changed, 148 insertions(+), 24 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs
2022-02-24 13:04 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
@ 2022-02-24 13:04 ` Kamil Konieczny
2022-03-22 19:09 ` Zbigniew Kempczyński
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
` (2 subsequent siblings)
3 siblings, 1 reply; 16+ messages in thread
From: Kamil Konieczny @ 2022-02-24 13:04 UTC (permalink / raw)
To: igt-dev
There is create function with relocations, so add its
counterpart without it.
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/intel_batchbuffer.c | 9 ++++++++-
lib/intel_batchbuffer.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index e5666cd4..159813dd 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1484,7 +1484,14 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
return __intel_bb_create(i915, 0, size,
relocs && !aux_needs_softpin(i915), 0, 0,
INTEL_ALLOCATOR_SIMPLE,
- ALLOC_STRATEGY_HIGH_TO_LOW);
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+}
+
+struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
+{
+ return __intel_bb_create(i915, 0, size, false, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
}
/**
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index a488f9cf..793c16aa 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -523,6 +523,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size);
struct intel_bb *
intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
+struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size);
struct intel_bb *
intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
void intel_bb_destroy(struct intel_bb *ibb);
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-02-24 13:04 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs Kamil Konieczny
@ 2022-02-24 13:04 ` Kamil Konieczny
2022-03-22 19:34 ` Zbigniew Kempczyński
2022-02-24 14:15 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_concurrent_all: Add no-reloc Patchwork
2022-02-25 3:42 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 16+ messages in thread
From: Kamil Konieczny @ 2022-02-24 13:04 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_concurrent_all.c | 162 +++++++++++++++++++++++++++-----
1 file changed, 139 insertions(+), 23 deletions(-)
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index d0f9b62e..24009da4 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -60,6 +60,7 @@ int fd, devid, gen;
int vgem_drv = -1;
int all;
int pass;
+uint64_t ahnd;
struct create {
const char *name;
@@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
+ static bool check_llc = true;
+ static bool has_snoop;
+
create_cpu_require(create, count);
- igt_require(!gem_has_llc(fd));
+ if (check_llc) {
+ has_snoop = !gem_has_llc(fd);
+ check_llc = false;
+ igt_require(!gem_has_llc(fd));
+ } else
+ igt_require(has_snoop);
}
static struct intel_buf *
@@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
struct intel_buf *buf;
buf = unmapped_create_bo(b);
- gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
+ __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
return buf;
}
@@ -578,16 +587,27 @@ static void bit17_require(void)
uint32_t swizzle_mode;
uint32_t phys_swizzle_mode;
} arg;
+ bool has_tiling2;
+ int has_tiling;
#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
if (arg.handle == 0) {
+ has_tiling2 = false;
arg.handle = gem_create(fd, 4096);
- gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ has_tiling = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ if (!has_tiling) {
+ igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ if (!errno)
+ has_tiling2 = true;
+
+ errno = 0;
+ }
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
gem_close(fd, arg.handle);
+ igt_require(has_tiling);
}
igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+ igt_require(has_tiling2);
}
static void wc_require(void)
@@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf;
uint32_t tmp[10], *b;
+ uint64_t addr = 0;
memset(reloc, 0, sizeof(reloc));
memset(gem_exec, 0, sizeof(gem_exec));
memset(&execbuf, 0, sizeof(execbuf));
+ if (ahnd) {
+ addr = buf->addr.offset;
+ if (INVALID_ADDR(addr)) {
+ addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
+ buf->handle, buf->size, 0);
+ buf->addr.offset = addr;
+ }
+ }
+
b = tmp;
*b++ = XY_COLOR_BLT_CMD_NOLEN |
((gen >= 8) ? 5 : 4) |
@@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
reloc[0].target_handle = buf->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
- *b++ = 0;
+ *b++ = addr;
if (gen >= 8)
- *b++ = 0;
+ *b++ = addr >> 32;
*b++ = val;
*b++ = MI_BATCH_BUFFER_END;
if ((b - tmp) & 1)
@@ -703,8 +733,17 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
gem_exec[1].handle = gem_create(fd, 4096);
- gem_exec[1].relocation_count = 1;
- gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (!ahnd) {
+ gem_exec[1].relocation_count = 1;
+ gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ gem_exec[1].offset = intel_allocator_alloc(ahnd,
+ gem_exec[1].handle, 4096, 4096);
+ gem_exec[1].flags |= EXEC_OBJECT_PINNED;
+
+ gem_exec[0].offset = buf->addr.offset;
+ gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ }
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 2;
@@ -716,6 +755,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_execbuf(fd, &execbuf);
gem_close(fd, gem_exec[1].handle);
+ put_offset(ahnd, gem_exec[1].handle);
}
static void
@@ -766,6 +806,18 @@ static bool set_max_map_count(int num_buffers)
return max > num_buffers;
}
+static uint64_t alloc_open(void)
+{
+ return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH) : 0;
+}
+
+static struct intel_bb *bb_create(int i915, uint32_t size)
+{
+ return ahnd ? intel_bb_create_no_relocs(i915, size) :
+ intel_bb_create_with_relocs(i915, size);
+}
+
static void buffers_init(struct buffers *b,
const char *name,
const struct create *create,
@@ -796,7 +848,7 @@ static void buffers_init(struct buffers *b,
igt_assert(b->src);
b->dst = b->src + num_buffers;
- b->ibb = intel_bb_create(_fd, 4096);
+ b->ibb = bb_create(_fd, 4096);
}
static void buffers_destroy(struct buffers *b)
@@ -829,6 +881,27 @@ static void buffers_destroy(struct buffers *b)
}
}
+static void bb_destroy(struct buffers *b)
+{
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+}
+
+static void __bufs_destroy(struct buffers *b)
+{
+ buffers_destroy(b);
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+ if (b->bops) {
+ buf_ops_destroy(b->bops);
+ b->bops = NULL;
+ }
+}
+
static void buffers_create(struct buffers *b)
{
int count = b->num_buffers;
@@ -838,32 +911,57 @@ static void buffers_create(struct buffers *b)
igt_assert(b->count == 0);
b->count = count;
+ ahnd = alloc_open();
for (int i = 0; i < count; i++) {
b->src[i] = b->mode->create_bo(b);
b->dst[i] = b->mode->create_bo(b);
}
b->spare = b->mode->create_bo(b);
b->snoop = snoop_create_bo(b);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_reset(struct buffers *b)
{
b->bops = buf_ops_create(fd);
- b->ibb = intel_bb_create(fd, 4096);
+ b->ibb = bb_create(fd, 4096);
+}
+
+static void __buffers_create(struct buffers *b)
+{
+ b->bops = buf_ops_create(fd);
+ igt_assert(b->bops);
+ igt_assert(b->num_buffers > 0);
+ igt_assert(b->mode);
+ igt_assert(b->mode->create_bo);
+
+ b->count = 0;
+ for (int i = 0; i < b->num_buffers; i++) {
+ b->src[i] = b->mode->create_bo(b);
+ b->dst[i] = b->mode->create_bo(b);
+ }
+ b->count = b->num_buffers;
+ b->spare = b->mode->create_bo(b);
+ b->snoop = snoop_create_bo(b);
+ ahnd = alloc_open();
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_fini(struct buffers *b)
{
if (b->bops == NULL)
return;
-
buffers_destroy(b);
free(b->tmp);
free(b->src);
-
- intel_bb_destroy(b->ibb);
- buf_ops_destroy(b->bops);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+ if (b->bops)
+ buf_ops_destroy(b->bops);
memset(b, 0, sizeof(*b));
}
@@ -1306,6 +1404,8 @@ static void run_single(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
@@ -1316,6 +1416,8 @@ static void run_interruptible(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
igt_while_interruptible(true)
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1332,10 +1434,20 @@ static void run_child(struct buffers *buffers,
* leading to the child closing an object without the parent knowing.
*/
pass = 0;
- igt_fork(child, 1)
+ __bufs_destroy(buffers);
+ intel_allocator_multiprocess_start();
+
+ igt_fork(child, 1) {
+ /* recreate process local variables */
+ intel_allocator_init();
+ __buffers_create(buffers);
do_test_func(buffers, do_copy_func, do_hang_func);
+ }
igt_waitchildren();
+ intel_allocator_multiprocess_stop();
+
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ buffers_reset(buffers);
}
static void __run_forked(struct buffers *buffers,
@@ -1346,24 +1458,21 @@ static void __run_forked(struct buffers *buffers,
{
/* purge the caches before cloing the process */
- buffers_destroy(buffers);
- intel_bb_destroy(buffers->ibb);
- buf_ops_destroy(buffers->bops);
+ __bufs_destroy(buffers);
+ intel_allocator_multiprocess_start();
igt_fork(child, num_children) {
int num_buffers;
/* recreate process local variables */
fd = gem_reopen_driver(fd);
-
+ intel_allocator_init(); //detach from thread
num_buffers = buffers->num_buffers / num_children;
num_buffers += MIN_BUFFERS;
if (num_buffers < buffers->num_buffers)
buffers->num_buffers = num_buffers;
- buffers_reset(buffers);
- buffers_create(buffers);
-
+ __buffers_create(buffers);
igt_while_interruptible(interrupt) {
for (pass = 0; pass < loops; pass++)
do_test_func(buffers,
@@ -1372,6 +1481,7 @@ static void __run_forked(struct buffers *buffers,
}
}
igt_waitchildren();
+ intel_allocator_multiprocess_stop();
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
buffers_reset(buffers);
@@ -1773,6 +1883,7 @@ igt_main
{ "16MiB", 2048, 2048 },
{ NULL}
};
+
uint64_t pin_sz = 0;
void *pinned = NULL;
char name[80];
@@ -1792,6 +1903,12 @@ igt_main
rendercopy = igt_get_render_copyfunc(devid);
vgem_drv = __drm_open_driver(DRIVER_VGEM);
+
+ ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH);
+ put_ahnd(ahnd);
+ if (ahnd)
+ intel_bb_track(true);
}
for (const struct create *c = create; c->name; c++) {
@@ -1864,7 +1981,6 @@ igt_main
igt_fixture
igt_stop_shrink_helper();
}
-
/* Use the entire mappable aperture, force swapping */
snprintf(name, sizeof(name), "%s%s-%s",
c->name, s->name, "swap");
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_concurrent_all: Add no-reloc
2022-02-24 13:04 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs Kamil Konieczny
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
@ 2022-02-24 14:15 ` Patchwork
2022-02-25 3:42 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2022-02-24 14:15 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4742 bytes --]
== Series Details ==
Series: i915/gem_concurrent_all: Add no-reloc
URL : https://patchwork.freedesktop.org/series/100688/
State : success
== Summary ==
CI Bug Log - changes from IGT_6356 -> IGTPW_6700
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/index.html
Participating hosts (45 -> 42)
------------------------------
Missing (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus
Known issues
------------
Here are the changes found in IGTPW_6700 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-blb-e6850/igt@amdgpu/amd_basic@cs-multi-fence.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271]) +21 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-skl-6600u/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [FAIL][9] ([i915#4547]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][11] ([i915#5026]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/fi-blb-e6850/igt@i915_selftest@live@requests.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][13] ([i915#3576]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/bat-adlp-6/igt@kms_busy@basic@flip.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/bat-adlp-6/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6356 -> IGTPW_6700
CI-20190529: 20190529
CI_DRM_11277: a9d1ffee8dbe2c5506cccf9077eab8fe439eea46 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6700: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/index.html
IGT_6356: b403d8e73c6888561eaec97835688313b0763ce9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/index.html
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915/gem_concurrent_all: Add no-reloc
2022-02-24 13:04 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
` (2 preceding siblings ...)
2022-02-24 14:15 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_concurrent_all: Add no-reloc Patchwork
@ 2022-02-25 3:42 ` Patchwork
3 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2022-02-25 3:42 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
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== Series Details ==
Series: i915/gem_concurrent_all: Add no-reloc
URL : https://patchwork.freedesktop.org/series/100688/
State : success
== Summary ==
CI Bug Log - changes from IGT_6356_full -> IGTPW_6700_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/index.html
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in IGTPW_6700_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-tglb: NOTRUN -> [SKIP][1] ([fdo#111827])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@feature_discovery@chamelium.html
- shard-iclb: NOTRUN -> [SKIP][2] ([fdo#111827])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb2/igt@feature_discovery@chamelium.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: NOTRUN -> [FAIL][3] ([i915#232])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@gem_eio@unwedge-stress.html
- shard-iclb: NOTRUN -> [TIMEOUT][4] ([i915#2481] / [i915#3070])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][5] ([i915#3354])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-snb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-tglb: NOTRUN -> [DMESG-WARN][6] ([i915#5076])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@gem_exec_balancer@parallel-bb-first.html
- shard-iclb: NOTRUN -> [SKIP][7] ([i915#4525])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_capture@pi@vcs0:
- shard-iclb: [PASS][8] -> [INCOMPLETE][9] ([i915#3371])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-iclb5/igt@gem_exec_capture@pi@vcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb6/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
- shard-tglb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#112283])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb6/igt@gem_exec_params@secure-non-root.html
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#112283])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@gem_exec_params@secure-non-root.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl7/igt@gem_lmem_swapping@heavy-multi.html
- shard-glk: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk7/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl4/igt@gem_lmem_swapping@parallel-random-verify.html
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#4613]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#4270])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@gem_pxp@fail-invalid-protected-context.html
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#4270])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb5/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][26] ([i915#768])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#110542])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#3297])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][29] ([i915#3318])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl4/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_linear_blits:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#109289]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@gen3_render_linear_blits.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109289]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb7/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][32] ([fdo#109271]) +135 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-snb6/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-oversize:
- shard-tglb: NOTRUN -> [SKIP][33] ([i915#2527] / [i915#2856]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb7/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-iclb: NOTRUN -> [SKIP][34] ([i915#2856]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb8/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [PASS][35] -> [INCOMPLETE][36] ([i915#456])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-tglb6/igt@i915_pm_backlight@fade_with_suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][37] ([i915#454])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: NOTRUN -> [FAIL][38] ([i915#454]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#4281])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#1937])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#1937])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#109289] / [fdo#111719])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109293] / [fdo#109506])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb4/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#110892])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@i915_pm_rpm@modeset-non-lpsp.html
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111644] / [i915#1397] / [i915#2411])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb6/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109506] / [i915#2411]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-kbl: [PASS][47] -> [INCOMPLETE][48] ([i915#151])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-kbl1/igt@i915_pm_rpm@system-suspend-modeset.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl4/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][49] ([i915#2373])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][50] ([i915#1759])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#111614]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][52] -> [DMESG-WARN][53] ([i915#118]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#3777]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111615]) +7 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#110723])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#3777]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
- shard-glk: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#3777]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#3689] / [i915#3886]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
- shard-glk: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3886])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][61] ([i915#3689]) +9 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109278] / [i915#3886]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb5/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3886]) +16 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#3886]) +12 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][65] ([fdo#111615] / [i915#3689]) +10 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271]) +211 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl1/igt@kms_cdclk@mode-transition.html
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#3742])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb7/igt@kms_cdclk@mode-transition.html
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#3742])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-hpd-after-suspend:
- shard-snb: NOTRUN -> [SKIP][69] ([fdo#109271] / [fdo#111827]) +5 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-snb6/igt@kms_chamelium@dp-hpd-after-suspend.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [fdo#111827]) +13 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl3/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@hdmi-hpd-after-suspend:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109284] / [fdo#111827]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb6/igt@kms_chamelium@hdmi-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [fdo#111827]) +22 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl7/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [fdo#111827]) +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk5/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
- shard-tglb: NOTRUN -> [SKIP][74] ([fdo#109284] / [fdo#111827]) +13 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-gamma:
- shard-iclb: NOTRUN -> [SKIP][75] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb7/igt@kms_color_chamelium@pipe-d-gamma.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#3116] / [i915#3299])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][77] ([i915#1319]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl1/igt@kms_content_protection@legacy.html
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#1063]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][79] ([i915#1319]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl2/igt@kms_content_protection@lic.html
* igt@kms_content_protection@type1:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109300] / [fdo#111066])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb4/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109278] / [fdo#109279]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3319]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#3359]) +6 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109279] / [i915#3359]) +8 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271]) +260 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#109274] / [fdo#109278]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#533]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl4/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-tglb: NOTRUN -> [SKIP][88] ([fdo#109274] / [fdo#111825]) +12 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109274]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb1/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][90] ([i915#180]) +4 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][91] -> [DMESG-WARN][92] ([i915#180]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][93] -> [DMESG-WARN][94] ([i915#180]) +3 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglb: NOTRUN -> [SKIP][95] ([i915#2587])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][96] -> [SKIP][97] ([i915#3701])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling:
- shard-iclb: NOTRUN -> [SKIP][98] ([i915#2587])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109280]) +18 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][100] ([fdo#109271]) +70 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][101] ([fdo#109280] / [fdo#111825]) +37 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#1187]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@kms_hdr@static-toggle-dpms.html
- shard-iclb: NOTRUN -> [SKIP][103] ([i915#1187])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb1/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_invalid_mode@clock-too-high:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#4278])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb7/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][106] ([i915#265])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-kbl: NOTRUN -> [FAIL][107] ([i915#265]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][108] ([fdo#108145] / [i915#265]) +2 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109278]) +19 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb6/igt@kms_plane_lowres@pipe-d-tiling-x.html
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#3536]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb7/igt@kms_plane_lowres@pipe-d-tiling-x.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-glk: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2733])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk5/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#111068] / [i915#658])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@kms_psr2_sf@cursor-plane-update-sf.html
- shard-glk: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk9/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#658]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-tglb: NOTRUN -> [SKIP][115] ([i915#2920])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#658]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][117] -> [SKIP][118] ([fdo#109441]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][119] ([i915#132] / [i915#3467]) +2 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb1/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][120] ([fdo#109441])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][121] ([IGT#2])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][122] ([i915#180] / [i915#295])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
- shard-apl: [PASS][123] -> [DMESG-WARN][124] ([i915#180] / [i915#295])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6356/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][125] ([fdo#109271] / [i915#533]) +3 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl4/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_vrr@flip-suspend:
- shard-tglb: NOTRUN -> [SKIP][126] ([fdo#109502])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@kms_vrr@flip-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#2437]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-apl3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglb: NOTRUN -> [SKIP][128] ([i915#2437]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-tglb3/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#2437])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-glk2/igt@kms_writeback@writeback-pixel-formats.html
- shard-kbl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#2437]) +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/shard-kbl1/igt@kms_writeback@writeback-pixel-form
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6700/index.html
[-- Attachment #2: Type: text/html, Size: 34025 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs Kamil Konieczny
@ 2022-03-22 19:09 ` Zbigniew Kempczyński
0 siblings, 0 replies; 16+ messages in thread
From: Zbigniew Kempczyński @ 2022-03-22 19:09 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
On Thu, Feb 24, 2022 at 02:04:43PM +0100, Kamil Konieczny wrote:
> There is create function with relocations, so add its
> counterpart without it.
>
> Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> lib/intel_batchbuffer.c | 9 ++++++++-
> lib/intel_batchbuffer.h | 1 +
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index e5666cd4..159813dd 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -1484,7 +1484,14 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size)
> return __intel_bb_create(i915, 0, size,
> relocs && !aux_needs_softpin(i915), 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> - ALLOC_STRATEGY_HIGH_TO_LOW);
> + ALLOC_STRATEGY_LOW_TO_HIGH);
Please keep HIGH_TO_LOW strategy. Only thing you need to do is
to use CANONICAL() + EXEC_OBJECT_SUPPORTS_48B_ADDRESS. Works fine
for me.
> +}
> +
> +struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size)
> +{
> + return __intel_bb_create(i915, 0, size, false, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
> }
Same here.
--
Zbigniew
>
> /**
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index a488f9cf..793c16aa 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -523,6 +523,7 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size);
> struct intel_bb *
> intel_bb_create_with_context(int i915, uint32_t ctx, uint32_t size);
> struct intel_bb *intel_bb_create_with_relocs(int i915, uint32_t size);
> +struct intel_bb *intel_bb_create_no_relocs(int i915, uint32_t size);
> struct intel_bb *
> intel_bb_create_with_relocs_and_context(int i915, uint32_t ctx, uint32_t size);
> void intel_bb_destroy(struct intel_bb *ibb);
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
@ 2022-03-22 19:34 ` Zbigniew Kempczyński
0 siblings, 0 replies; 16+ messages in thread
From: Zbigniew Kempczyński @ 2022-03-22 19:34 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
On Thu, Feb 24, 2022 at 02:04:44PM +0100, Kamil Konieczny wrote:
> Add noreloc mode for GPU gens without relocations. Also
> while at this, add some caching for required properties.
> Change also snoop function so it will work on DG1.
>
> v4: corrected alloc_open and first ahnd setting
>
> Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> tests/i915/gem_concurrent_all.c | 162 +++++++++++++++++++++++++++-----
> 1 file changed, 139 insertions(+), 23 deletions(-)
>
> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> index d0f9b62e..24009da4 100644
> --- a/tests/i915/gem_concurrent_all.c
> +++ b/tests/i915/gem_concurrent_all.c
> @@ -60,6 +60,7 @@ int fd, devid, gen;
> int vgem_drv = -1;
> int all;
> int pass;
> +uint64_t ahnd;
>
> struct create {
> const char *name;
> @@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
>
> static void create_snoop_require(const struct create *create, unsigned count)
> {
> + static bool check_llc = true;
> + static bool has_snoop;
> +
> create_cpu_require(create, count);
> - igt_require(!gem_has_llc(fd));
> + if (check_llc) {
> + has_snoop = !gem_has_llc(fd);
> + check_llc = false;
> + igt_require(!gem_has_llc(fd));
> + } else
> + igt_require(has_snoop);
> }
For this case (gem_concurrent_blit) you may cache - there's no reopening
of another device. But be careful for other tests.
I think above can be simplified to:
if (check_llc) {
has_snoop = !gem_has_llc(fd);
check_llc = false;
}
igt_require(has_snoop);
>
> static struct intel_buf *
> @@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
> struct intel_buf *buf;
>
> buf = unmapped_create_bo(b);
> - gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
> + __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
>
> return buf;
> }
> @@ -578,16 +587,27 @@ static void bit17_require(void)
> uint32_t swizzle_mode;
> uint32_t phys_swizzle_mode;
> } arg;
> + bool has_tiling2;
> + int has_tiling;
> #define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
>
> if (arg.handle == 0) {
> + has_tiling2 = false;
> arg.handle = gem_create(fd, 4096);
> - gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + has_tiling = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + if (!has_tiling) {
> + igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> + if (!errno)
> + has_tiling2 = true;
> +
> + errno = 0;
> + }
>
> - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> gem_close(fd, arg.handle);
> + igt_require(has_tiling);
> }
> igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
> + igt_require(has_tiling2);
> }
>
> static void wc_require(void)
> @@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> struct drm_i915_gem_exec_object2 gem_exec[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> uint32_t tmp[10], *b;
> + uint64_t addr = 0;
>
> memset(reloc, 0, sizeof(reloc));
> memset(gem_exec, 0, sizeof(gem_exec));
> memset(&execbuf, 0, sizeof(execbuf));
>
> + if (ahnd) {
> + addr = buf->addr.offset;
> + if (INVALID_ADDR(addr)) {
> + addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
> + buf->handle, buf->size, 0);
> + buf->addr.offset = addr;
> + }
> + }
> +
> b = tmp;
> *b++ = XY_COLOR_BLT_CMD_NOLEN |
> ((gen >= 8) ? 5 : 4) |
> @@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> reloc[0].target_handle = buf->handle;
> reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
> reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
> - *b++ = 0;
> + *b++ = addr;
> if (gen >= 8)
> - *b++ = 0;
> + *b++ = addr >> 32;
> *b++ = val;
> *b++ = MI_BATCH_BUFFER_END;
> if ((b - tmp) & 1)
> @@ -703,8 +733,17 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
>
> gem_exec[1].handle = gem_create(fd, 4096);
It is tempting place to use gem_create_from_pool() call.
> - gem_exec[1].relocation_count = 1;
> - gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + if (!ahnd) {
> + gem_exec[1].relocation_count = 1;
> + gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + } else {
> + gem_exec[1].offset = intel_allocator_alloc(ahnd,
> + gem_exec[1].handle, 4096, 4096);
Use 0 as last argument - allocator will use safe alignment and we won't get
surprises.
> + gem_exec[1].flags |= EXEC_OBJECT_PINNED;
> +
> + gem_exec[0].offset = buf->addr.offset;
> + gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> + }
Use CANONICAL() + EXEC_OBJECT_SUPPORTS_48B_ADDRESS and it is HIGH_TO_LOW ready.
>
> execbuf.buffers_ptr = to_user_pointer(gem_exec);
> execbuf.buffer_count = 2;
> @@ -716,6 +755,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_execbuf(fd, &execbuf);
>
> gem_close(fd, gem_exec[1].handle);
> + put_offset(ahnd, gem_exec[1].handle);
> }
>
> static void
> @@ -766,6 +806,18 @@ static bool set_max_map_count(int num_buffers)
> return max > num_buffers;
> }
>
> +static uint64_t alloc_open(void)
> +{
> + return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH) : 0;
HIGH_TO_LOW.
> +}
> +
> +static struct intel_bb *bb_create(int i915, uint32_t size)
> +{
> + return ahnd ? intel_bb_create_no_relocs(i915, size) :
> + intel_bb_create_with_relocs(i915, size);
> +}
> +
> static void buffers_init(struct buffers *b,
> const char *name,
> const struct create *create,
> @@ -796,7 +848,7 @@ static void buffers_init(struct buffers *b,
> igt_assert(b->src);
> b->dst = b->src + num_buffers;
>
> - b->ibb = intel_bb_create(_fd, 4096);
> + b->ibb = bb_create(_fd, 4096);
> }
>
> static void buffers_destroy(struct buffers *b)
> @@ -829,6 +881,27 @@ static void buffers_destroy(struct buffers *b)
> }
> }
>
> +static void bb_destroy(struct buffers *b)
> +{
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> +}
> +
> +static void __bufs_destroy(struct buffers *b)
> +{
> + buffers_destroy(b);
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> + if (b->bops) {
> + buf_ops_destroy(b->bops);
> + b->bops = NULL;
> + }
> +}
> +
> static void buffers_create(struct buffers *b)
> {
> int count = b->num_buffers;
> @@ -838,32 +911,57 @@ static void buffers_create(struct buffers *b)
> igt_assert(b->count == 0);
> b->count = count;
>
> + ahnd = alloc_open();
> for (int i = 0; i < count; i++) {
> b->src[i] = b->mode->create_bo(b);
> b->dst[i] = b->mode->create_bo(b);
> }
> b->spare = b->mode->create_bo(b);
> b->snoop = snoop_create_bo(b);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> +
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_reset(struct buffers *b)
> {
> b->bops = buf_ops_create(fd);
> - b->ibb = intel_bb_create(fd, 4096);
> + b->ibb = bb_create(fd, 4096);
> +}
> +
> +static void __buffers_create(struct buffers *b)
> +{
> + b->bops = buf_ops_create(fd);
> + igt_assert(b->bops);
> + igt_assert(b->num_buffers > 0);
> + igt_assert(b->mode);
> + igt_assert(b->mode->create_bo);
> +
> + b->count = 0;
> + for (int i = 0; i < b->num_buffers; i++) {
> + b->src[i] = b->mode->create_bo(b);
> + b->dst[i] = b->mode->create_bo(b);
> + }
> + b->count = b->num_buffers;
> + b->spare = b->mode->create_bo(b);
> + b->snoop = snoop_create_bo(b);
> + ahnd = alloc_open();
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_fini(struct buffers *b)
> {
> if (b->bops == NULL)
> return;
> -
> buffers_destroy(b);
>
> free(b->tmp);
> free(b->src);
> -
> - intel_bb_destroy(b->ibb);
> - buf_ops_destroy(b->bops);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> + if (b->bops)
> + buf_ops_destroy(b->bops);
>
> memset(b, 0, sizeof(*b));
> }
> @@ -1306,6 +1404,8 @@ static void run_single(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> }
> @@ -1316,6 +1416,8 @@ static void run_interruptible(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> igt_while_interruptible(true)
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> @@ -1332,10 +1434,20 @@ static void run_child(struct buffers *buffers,
> * leading to the child closing an object without the parent knowing.
> */
> pass = 0;
> - igt_fork(child, 1)
> + __bufs_destroy(buffers);
> + intel_allocator_multiprocess_start();
Imo you don't need to create multiprocess infra as you're initializing
standalone allocator within child.
> +
> + igt_fork(child, 1) {
> + /* recreate process local variables */
> + intel_allocator_init();
> + __buffers_create(buffers);
> do_test_func(buffers, do_copy_func, do_hang_func);
> + }
> igt_waitchildren();
> + intel_allocator_multiprocess_stop();
Same here.
> +
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> + buffers_reset(buffers);
> }
>
> static void __run_forked(struct buffers *buffers,
> @@ -1346,24 +1458,21 @@ static void __run_forked(struct buffers *buffers,
>
> {
> /* purge the caches before cloing the process */
> - buffers_destroy(buffers);
> - intel_bb_destroy(buffers->ibb);
> - buf_ops_destroy(buffers->bops);
> + __bufs_destroy(buffers);
> + intel_allocator_multiprocess_start();
Same here.
>
> igt_fork(child, num_children) {
> int num_buffers;
>
> /* recreate process local variables */
> fd = gem_reopen_driver(fd);
> -
> + intel_allocator_init(); //detach from thread
> num_buffers = buffers->num_buffers / num_children;
> num_buffers += MIN_BUFFERS;
> if (num_buffers < buffers->num_buffers)
> buffers->num_buffers = num_buffers;
>
> - buffers_reset(buffers);
> - buffers_create(buffers);
> -
> + __buffers_create(buffers);
> igt_while_interruptible(interrupt) {
> for (pass = 0; pass < loops; pass++)
> do_test_func(buffers,
> @@ -1372,6 +1481,7 @@ static void __run_forked(struct buffers *buffers,
> }
> }
> igt_waitchildren();
> + intel_allocator_multiprocess_stop();
And here.
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
>
> buffers_reset(buffers);
> @@ -1773,6 +1883,7 @@ igt_main
> { "16MiB", 2048, 2048 },
> { NULL}
> };
> +
> uint64_t pin_sz = 0;
> void *pinned = NULL;
> char name[80];
> @@ -1792,6 +1903,12 @@ igt_main
> rendercopy = igt_get_render_copyfunc(devid);
>
> vgem_drv = __drm_open_driver(DRIVER_VGEM);
> +
> + ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH);
Keep HIGH_TO_LOW.
Anyway - changes you did work for me, but I would like to keep
intel-bb intact (high-to-low strategy).
--
Zbigniew
> + put_ahnd(ahnd);
> + if (ahnd)
> + intel_bb_track(true);
> }
>
> for (const struct create *c = create; c->name; c++) {
> @@ -1864,7 +1981,6 @@ igt_main
> igt_fixture
> igt_stop_shrink_helper();
> }
> -
> /* Use the entire mappable aperture, force swapping */
> snprintf(name, sizeof(name), "%s%s-%s",
> c->name, s->name, "swap");
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-29 14:17 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
@ 2022-03-29 14:17 ` Kamil Konieczny
0 siblings, 0 replies; 16+ messages in thread
From: Kamil Konieczny @ 2022-03-29 14:17 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
and 256KiB with modified drm-tip to allow softpinning and
second run with relocs.
v8: In main fixture, first try to open allocator should be done
with get_simple_h2l_ahnd so only on no-relocs gens we will
later use intel_allocator_open_full function (Zbigniew).
v7: rebase, cleanup bit17 caching (Zbigniew comments)
v6: correct comment, rewrite bit17 caching (Zbigniew)
v5: rebase, fix caching in bit17_require, changes according
to Zbigniew review: simplify cache of !gem_has_llc, drop
multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
correct offset and flags
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_concurrent_all.c | 175 ++++++++++++++++++++++++++------
1 file changed, 144 insertions(+), 31 deletions(-)
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index d0f9b62e..92c13f33 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -60,6 +60,7 @@ int fd, devid, gen;
int vgem_drv = -1;
int all;
int pass;
+uint64_t ahnd;
struct create {
const char *name;
@@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
+ static bool check_llc = true;
+ static bool has_snoop;
+
create_cpu_require(create, count);
- igt_require(!gem_has_llc(fd));
+ if (check_llc) {
+ has_snoop = !gem_has_llc(fd);
+ check_llc = false;
+ }
+
+ igt_require(has_snoop);
}
static struct intel_buf *
@@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
struct intel_buf *buf;
buf = unmapped_create_bo(b);
- gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
+ __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
return buf;
}
@@ -572,22 +581,33 @@ gttX_create_bo(const struct buffers *b)
static void bit17_require(void)
{
- static struct drm_i915_gem_get_tiling2 {
- uint32_t handle;
- uint32_t tiling_mode;
- uint32_t swizzle_mode;
- uint32_t phys_swizzle_mode;
- } arg;
+ static bool has_tiling2, checked;
+
#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
- if (arg.handle == 0) {
+ if (!checked) {
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg = {};
+ int err;
+
+ checked = true;
arg.handle = gem_create(fd, 4096);
- gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ if (!err) {
+ igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ if (!errno && arg.phys_swizzle_mode == arg.swizzle_mode)
+ has_tiling2 = true;
+ }
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ errno = 0;
gem_close(fd, arg.handle);
}
- igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ igt_require(has_tiling2);
}
static void wc_require(void)
@@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf;
uint32_t tmp[10], *b;
+ uint64_t addr = 0;
memset(reloc, 0, sizeof(reloc));
memset(gem_exec, 0, sizeof(gem_exec));
memset(&execbuf, 0, sizeof(execbuf));
+ if (ahnd) {
+ addr = buf->addr.offset;
+ if (INVALID_ADDR(addr)) {
+ addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
+ buf->handle, buf->size, 0);
+ buf->addr.offset = addr;
+ }
+ }
+
b = tmp;
*b++ = XY_COLOR_BLT_CMD_NOLEN |
((gen >= 8) ? 5 : 4) |
@@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
reloc[0].target_handle = buf->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
- *b++ = 0;
+ *b++ = addr;
if (gen >= 8)
- *b++ = 0;
+ *b++ = addr >> 32;
*b++ = val;
*b++ = MI_BATCH_BUFFER_END;
if ((b - tmp) & 1)
@@ -703,8 +733,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
gem_exec[1].handle = gem_create(fd, 4096);
- gem_exec[1].relocation_count = 1;
- gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (!ahnd) {
+ gem_exec[1].relocation_count = 1;
+ gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
+ gem_exec[1].handle,
+ 4096, 0));
+ gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ gem_exec[0].offset = CANONICAL(buf->addr.offset);
+ gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ }
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 2;
@@ -716,6 +757,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_execbuf(fd, &execbuf);
gem_close(fd, gem_exec[1].handle);
+ put_offset(ahnd, gem_exec[1].handle);
}
static void
@@ -766,6 +808,18 @@ static bool set_max_map_count(int num_buffers)
return max > num_buffers;
}
+static uint64_t alloc_open(void)
+{
+ return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
+}
+
+static struct intel_bb *bb_create(int i915, uint32_t size)
+{
+ return ahnd ? intel_bb_create_no_relocs(i915, size) :
+ intel_bb_create_with_relocs(i915, size);
+}
+
static void buffers_init(struct buffers *b,
const char *name,
const struct create *create,
@@ -796,7 +850,7 @@ static void buffers_init(struct buffers *b,
igt_assert(b->src);
b->dst = b->src + num_buffers;
- b->ibb = intel_bb_create(_fd, 4096);
+ b->ibb = bb_create(_fd, 4096);
}
static void buffers_destroy(struct buffers *b)
@@ -829,6 +883,27 @@ static void buffers_destroy(struct buffers *b)
}
}
+static void bb_destroy(struct buffers *b)
+{
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+}
+
+static void __bufs_destroy(struct buffers *b)
+{
+ buffers_destroy(b);
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+ if (b->bops) {
+ buf_ops_destroy(b->bops);
+ b->bops = NULL;
+ }
+}
+
static void buffers_create(struct buffers *b)
{
int count = b->num_buffers;
@@ -838,32 +913,57 @@ static void buffers_create(struct buffers *b)
igt_assert(b->count == 0);
b->count = count;
+ ahnd = alloc_open();
for (int i = 0; i < count; i++) {
b->src[i] = b->mode->create_bo(b);
b->dst[i] = b->mode->create_bo(b);
}
b->spare = b->mode->create_bo(b);
b->snoop = snoop_create_bo(b);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_reset(struct buffers *b)
{
b->bops = buf_ops_create(fd);
- b->ibb = intel_bb_create(fd, 4096);
+ b->ibb = bb_create(fd, 4096);
+}
+
+static void __buffers_create(struct buffers *b)
+{
+ b->bops = buf_ops_create(fd);
+ igt_assert(b->bops);
+ igt_assert(b->num_buffers > 0);
+ igt_assert(b->mode);
+ igt_assert(b->mode->create_bo);
+
+ b->count = 0;
+ for (int i = 0; i < b->num_buffers; i++) {
+ b->src[i] = b->mode->create_bo(b);
+ b->dst[i] = b->mode->create_bo(b);
+ }
+ b->count = b->num_buffers;
+ b->spare = b->mode->create_bo(b);
+ b->snoop = snoop_create_bo(b);
+ ahnd = alloc_open();
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_fini(struct buffers *b)
{
if (b->bops == NULL)
return;
-
buffers_destroy(b);
free(b->tmp);
free(b->src);
-
- intel_bb_destroy(b->ibb);
- buf_ops_destroy(b->bops);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+ if (b->bops)
+ buf_ops_destroy(b->bops);
memset(b, 0, sizeof(*b));
}
@@ -1306,6 +1406,8 @@ static void run_single(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
@@ -1316,6 +1418,8 @@ static void run_interruptible(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
igt_while_interruptible(true)
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1332,10 +1436,18 @@ static void run_child(struct buffers *buffers,
* leading to the child closing an object without the parent knowing.
*/
pass = 0;
- igt_fork(child, 1)
+ __bufs_destroy(buffers);
+
+ igt_fork(child, 1) {
+ /* recreate process local variables */
+ intel_allocator_init();
+ __buffers_create(buffers);
do_test_func(buffers, do_copy_func, do_hang_func);
+ }
igt_waitchildren();
+
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ buffers_reset(buffers);
}
static void __run_forked(struct buffers *buffers,
@@ -1346,24 +1458,20 @@ static void __run_forked(struct buffers *buffers,
{
/* purge the caches before cloing the process */
- buffers_destroy(buffers);
- intel_bb_destroy(buffers->ibb);
- buf_ops_destroy(buffers->bops);
+ __bufs_destroy(buffers);
igt_fork(child, num_children) {
int num_buffers;
/* recreate process local variables */
fd = gem_reopen_driver(fd);
-
+ intel_allocator_init(); /* detach from thread */
num_buffers = buffers->num_buffers / num_children;
num_buffers += MIN_BUFFERS;
if (num_buffers < buffers->num_buffers)
buffers->num_buffers = num_buffers;
- buffers_reset(buffers);
- buffers_create(buffers);
-
+ __buffers_create(buffers);
igt_while_interruptible(interrupt) {
for (pass = 0; pass < loops; pass++)
do_test_func(buffers,
@@ -1773,6 +1881,7 @@ igt_main
{ "16MiB", 2048, 2048 },
{ NULL}
};
+
uint64_t pin_sz = 0;
void *pinned = NULL;
char name[80];
@@ -1792,6 +1901,11 @@ igt_main
rendercopy = igt_get_render_copyfunc(devid);
vgem_drv = __drm_open_driver(DRIVER_VGEM);
+
+ ahnd = get_simple_h2l_ahnd(fd, 0);
+ put_ahnd(ahnd);
+ if (ahnd)
+ intel_bb_track(true);
}
for (const struct create *c = create; c->name; c++) {
@@ -1864,7 +1978,6 @@ igt_main
igt_fixture
igt_stop_shrink_helper();
}
-
/* Use the entire mappable aperture, force swapping */
snprintf(name, sizeof(name), "%s%s-%s",
c->name, s->name, "swap");
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-29 13:49 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
@ 2022-03-29 13:49 ` Kamil Konieczny
0 siblings, 0 replies; 16+ messages in thread
From: Kamil Konieczny @ 2022-03-29 13:49 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
and 256KiB with modified drm-tip to allow softpinning and
second run with relocs.
v8: In main first call to allocator only checks if there are no
relocs so it can use simpler function.
v7: rebase, cleanup bit17 caching (Zbigniew comments)
v6: correct comment, rewrite bit17 caching (Zbigniew)
v5: rebase, fix caching in bit17_require, changes according
to Zbigniew review: simplify cache of !gem_has_llc, drop
multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
correct offset and flags
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_concurrent_all.c | 175 ++++++++++++++++++++++++++------
1 file changed, 144 insertions(+), 31 deletions(-)
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index d0f9b62e..92c13f33 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -60,6 +60,7 @@ int fd, devid, gen;
int vgem_drv = -1;
int all;
int pass;
+uint64_t ahnd;
struct create {
const char *name;
@@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
+ static bool check_llc = true;
+ static bool has_snoop;
+
create_cpu_require(create, count);
- igt_require(!gem_has_llc(fd));
+ if (check_llc) {
+ has_snoop = !gem_has_llc(fd);
+ check_llc = false;
+ }
+
+ igt_require(has_snoop);
}
static struct intel_buf *
@@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
struct intel_buf *buf;
buf = unmapped_create_bo(b);
- gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
+ __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
return buf;
}
@@ -572,22 +581,33 @@ gttX_create_bo(const struct buffers *b)
static void bit17_require(void)
{
- static struct drm_i915_gem_get_tiling2 {
- uint32_t handle;
- uint32_t tiling_mode;
- uint32_t swizzle_mode;
- uint32_t phys_swizzle_mode;
- } arg;
+ static bool has_tiling2, checked;
+
#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
- if (arg.handle == 0) {
+ if (!checked) {
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg = {};
+ int err;
+
+ checked = true;
arg.handle = gem_create(fd, 4096);
- gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ if (!err) {
+ igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ if (!errno && arg.phys_swizzle_mode == arg.swizzle_mode)
+ has_tiling2 = true;
+ }
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ errno = 0;
gem_close(fd, arg.handle);
}
- igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ igt_require(has_tiling2);
}
static void wc_require(void)
@@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf;
uint32_t tmp[10], *b;
+ uint64_t addr = 0;
memset(reloc, 0, sizeof(reloc));
memset(gem_exec, 0, sizeof(gem_exec));
memset(&execbuf, 0, sizeof(execbuf));
+ if (ahnd) {
+ addr = buf->addr.offset;
+ if (INVALID_ADDR(addr)) {
+ addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
+ buf->handle, buf->size, 0);
+ buf->addr.offset = addr;
+ }
+ }
+
b = tmp;
*b++ = XY_COLOR_BLT_CMD_NOLEN |
((gen >= 8) ? 5 : 4) |
@@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
reloc[0].target_handle = buf->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
- *b++ = 0;
+ *b++ = addr;
if (gen >= 8)
- *b++ = 0;
+ *b++ = addr >> 32;
*b++ = val;
*b++ = MI_BATCH_BUFFER_END;
if ((b - tmp) & 1)
@@ -703,8 +733,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
gem_exec[1].handle = gem_create(fd, 4096);
- gem_exec[1].relocation_count = 1;
- gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (!ahnd) {
+ gem_exec[1].relocation_count = 1;
+ gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
+ gem_exec[1].handle,
+ 4096, 0));
+ gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ gem_exec[0].offset = CANONICAL(buf->addr.offset);
+ gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ }
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 2;
@@ -716,6 +757,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_execbuf(fd, &execbuf);
gem_close(fd, gem_exec[1].handle);
+ put_offset(ahnd, gem_exec[1].handle);
}
static void
@@ -766,6 +808,18 @@ static bool set_max_map_count(int num_buffers)
return max > num_buffers;
}
+static uint64_t alloc_open(void)
+{
+ return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
+}
+
+static struct intel_bb *bb_create(int i915, uint32_t size)
+{
+ return ahnd ? intel_bb_create_no_relocs(i915, size) :
+ intel_bb_create_with_relocs(i915, size);
+}
+
static void buffers_init(struct buffers *b,
const char *name,
const struct create *create,
@@ -796,7 +850,7 @@ static void buffers_init(struct buffers *b,
igt_assert(b->src);
b->dst = b->src + num_buffers;
- b->ibb = intel_bb_create(_fd, 4096);
+ b->ibb = bb_create(_fd, 4096);
}
static void buffers_destroy(struct buffers *b)
@@ -829,6 +883,27 @@ static void buffers_destroy(struct buffers *b)
}
}
+static void bb_destroy(struct buffers *b)
+{
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+}
+
+static void __bufs_destroy(struct buffers *b)
+{
+ buffers_destroy(b);
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+ if (b->bops) {
+ buf_ops_destroy(b->bops);
+ b->bops = NULL;
+ }
+}
+
static void buffers_create(struct buffers *b)
{
int count = b->num_buffers;
@@ -838,32 +913,57 @@ static void buffers_create(struct buffers *b)
igt_assert(b->count == 0);
b->count = count;
+ ahnd = alloc_open();
for (int i = 0; i < count; i++) {
b->src[i] = b->mode->create_bo(b);
b->dst[i] = b->mode->create_bo(b);
}
b->spare = b->mode->create_bo(b);
b->snoop = snoop_create_bo(b);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_reset(struct buffers *b)
{
b->bops = buf_ops_create(fd);
- b->ibb = intel_bb_create(fd, 4096);
+ b->ibb = bb_create(fd, 4096);
+}
+
+static void __buffers_create(struct buffers *b)
+{
+ b->bops = buf_ops_create(fd);
+ igt_assert(b->bops);
+ igt_assert(b->num_buffers > 0);
+ igt_assert(b->mode);
+ igt_assert(b->mode->create_bo);
+
+ b->count = 0;
+ for (int i = 0; i < b->num_buffers; i++) {
+ b->src[i] = b->mode->create_bo(b);
+ b->dst[i] = b->mode->create_bo(b);
+ }
+ b->count = b->num_buffers;
+ b->spare = b->mode->create_bo(b);
+ b->snoop = snoop_create_bo(b);
+ ahnd = alloc_open();
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_fini(struct buffers *b)
{
if (b->bops == NULL)
return;
-
buffers_destroy(b);
free(b->tmp);
free(b->src);
-
- intel_bb_destroy(b->ibb);
- buf_ops_destroy(b->bops);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+ if (b->bops)
+ buf_ops_destroy(b->bops);
memset(b, 0, sizeof(*b));
}
@@ -1306,6 +1406,8 @@ static void run_single(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
@@ -1316,6 +1418,8 @@ static void run_interruptible(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
igt_while_interruptible(true)
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1332,10 +1436,18 @@ static void run_child(struct buffers *buffers,
* leading to the child closing an object without the parent knowing.
*/
pass = 0;
- igt_fork(child, 1)
+ __bufs_destroy(buffers);
+
+ igt_fork(child, 1) {
+ /* recreate process local variables */
+ intel_allocator_init();
+ __buffers_create(buffers);
do_test_func(buffers, do_copy_func, do_hang_func);
+ }
igt_waitchildren();
+
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ buffers_reset(buffers);
}
static void __run_forked(struct buffers *buffers,
@@ -1346,24 +1458,20 @@ static void __run_forked(struct buffers *buffers,
{
/* purge the caches before cloing the process */
- buffers_destroy(buffers);
- intel_bb_destroy(buffers->ibb);
- buf_ops_destroy(buffers->bops);
+ __bufs_destroy(buffers);
igt_fork(child, num_children) {
int num_buffers;
/* recreate process local variables */
fd = gem_reopen_driver(fd);
-
+ intel_allocator_init(); /* detach from thread */
num_buffers = buffers->num_buffers / num_children;
num_buffers += MIN_BUFFERS;
if (num_buffers < buffers->num_buffers)
buffers->num_buffers = num_buffers;
- buffers_reset(buffers);
- buffers_create(buffers);
-
+ __buffers_create(buffers);
igt_while_interruptible(interrupt) {
for (pass = 0; pass < loops; pass++)
do_test_func(buffers,
@@ -1773,6 +1881,7 @@ igt_main
{ "16MiB", 2048, 2048 },
{ NULL}
};
+
uint64_t pin_sz = 0;
void *pinned = NULL;
char name[80];
@@ -1792,6 +1901,11 @@ igt_main
rendercopy = igt_get_render_copyfunc(devid);
vgem_drv = __drm_open_driver(DRIVER_VGEM);
+
+ ahnd = get_simple_h2l_ahnd(fd, 0);
+ put_ahnd(ahnd);
+ if (ahnd)
+ intel_bb_track(true);
}
for (const struct create *c = create; c->name; c++) {
@@ -1864,7 +1978,6 @@ igt_main
igt_fixture
igt_stop_shrink_helper();
}
-
/* Use the entire mappable aperture, force swapping */
snprintf(name, sizeof(name), "%s%s-%s",
c->name, s->name, "swap");
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-29 8:10 ` Zbigniew Kempczyński
@ 2022-03-29 12:56 ` Kamil Konieczny
0 siblings, 0 replies; 16+ messages in thread
From: Kamil Konieczny @ 2022-03-29 12:56 UTC (permalink / raw)
To: igt-dev
Hi Zbigniew,
Dnia 2022-03-29 at 10:10:14 +0200, Zbigniew Kempczyński napisał(a):
> On Mon, Mar 28, 2022 at 06:55:45PM +0200, Kamil Konieczny wrote:
> > Add noreloc mode for GPU gens without relocations. Also
> > while at this, add some caching for required properties.
> > Change also snoop function so it will work on DG1.
> >
> > Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
> > and 256KiB with modified drm-tip to allow softpinning.
> >
> > v7: rebase, cleanup bit17 caching (Zbigniew comments)
> > v6: correct comment, rewrite bit17 caching (Zbigniew)
> > v5: rebase, fix caching in bit17_require, changes according
> > to Zbigniew review: simplify cache of !gem_has_llc, drop
> > multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
> > correct offset and flags
> > v4: corrected alloc_open and first ahnd setting
> >
> > Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> > tests/i915/gem_concurrent_all.c | 176 ++++++++++++++++++++++++++------
> > 1 file changed, 145 insertions(+), 31 deletions(-)
> >
> > diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> > index d0f9b62e..7a91434c 100644
> > --- a/tests/i915/gem_concurrent_all.c
> > +++ b/tests/i915/gem_concurrent_all.c
> > @@ -60,6 +60,7 @@ int fd, devid, gen;
> > int vgem_drv = -1;
> > int all;
> > int pass;
> > +uint64_t ahnd;
> >
> > struct create {
> > const char *name;
> > @@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
> >
> > static void create_snoop_require(const struct create *create, unsigned count)
> > {
> > + static bool check_llc = true;
> > + static bool has_snoop;
> > +
> > create_cpu_require(create, count);
> > - igt_require(!gem_has_llc(fd));
> > + if (check_llc) {
> > + has_snoop = !gem_has_llc(fd);
> > + check_llc = false;
> > + }
> > +
> > + igt_require(has_snoop);
> > }
> >
> > static struct intel_buf *
> > @@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
> > struct intel_buf *buf;
> >
> > buf = unmapped_create_bo(b);
> > - gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
> > + __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
> >
> > return buf;
> > }
> > @@ -572,22 +581,33 @@ gttX_create_bo(const struct buffers *b)
> >
> > static void bit17_require(void)
> > {
> > - static struct drm_i915_gem_get_tiling2 {
> > - uint32_t handle;
> > - uint32_t tiling_mode;
> > - uint32_t swizzle_mode;
> > - uint32_t phys_swizzle_mode;
> > - } arg;
> > + static bool has_tiling2, checked;
> > +
> > #define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
> >
> > - if (arg.handle == 0) {
> > + if (!checked) {
> > + struct drm_i915_gem_get_tiling2 {
> > + uint32_t handle;
> > + uint32_t tiling_mode;
> > + uint32_t swizzle_mode;
> > + uint32_t phys_swizzle_mode;
> > + } arg = {};
> > + int err;
> > +
> > + checked = true;
> > arg.handle = gem_create(fd, 4096);
> > - gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> > + err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> > + if (!err) {
> > + igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> > + if (!errno && arg.phys_swizzle_mode == arg.swizzle_mode)
> > + has_tiling2 = true;
> > + }
> >
> > - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> > + errno = 0;
> > gem_close(fd, arg.handle);
> > }
> > - igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
> > +
> > + igt_require(has_tiling2);
> > }
>
> This looks much better.
>
> >
> > static void wc_require(void)
> > @@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> > struct drm_i915_gem_exec_object2 gem_exec[2];
> > struct drm_i915_gem_execbuffer2 execbuf;
> > uint32_t tmp[10], *b;
> > + uint64_t addr = 0;
> >
> > memset(reloc, 0, sizeof(reloc));
> > memset(gem_exec, 0, sizeof(gem_exec));
> > memset(&execbuf, 0, sizeof(execbuf));
> >
> > + if (ahnd) {
> > + addr = buf->addr.offset;
> > + if (INVALID_ADDR(addr)) {
> > + addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
> > + buf->handle, buf->size, 0);
> > + buf->addr.offset = addr;
> > + }
> > + }
> > +
> > b = tmp;
> > *b++ = XY_COLOR_BLT_CMD_NOLEN |
> > ((gen >= 8) ? 5 : 4) |
> > @@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> > reloc[0].target_handle = buf->handle;
> > reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
> > reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
> > - *b++ = 0;
> > + *b++ = addr;
> > if (gen >= 8)
> > - *b++ = 0;
> > + *b++ = addr >> 32;
> > *b++ = val;
> > *b++ = MI_BATCH_BUFFER_END;
> > if ((b - tmp) & 1)
> > @@ -703,8 +733,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> > gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
> >
> > gem_exec[1].handle = gem_create(fd, 4096);
> > - gem_exec[1].relocation_count = 1;
> > - gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> > + if (!ahnd) {
> > + gem_exec[1].relocation_count = 1;
> > + gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> > + } else {
> > + gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
> > + gem_exec[1].handle,
> > + 4096, 0));
> > + gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > +
> > + gem_exec[0].offset = CANONICAL(buf->addr.offset);
> > + gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > + }
> >
> > execbuf.buffers_ptr = to_user_pointer(gem_exec);
> > execbuf.buffer_count = 2;
> > @@ -716,6 +757,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> > gem_execbuf(fd, &execbuf);
> >
> > gem_close(fd, gem_exec[1].handle);
> > + put_offset(ahnd, gem_exec[1].handle);
> > }
> >
> > static void
> > @@ -766,6 +808,18 @@ static bool set_max_map_count(int num_buffers)
> > return max > num_buffers;
> > }
> >
> > +static uint64_t alloc_open(void)
> > +{
> > + return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> > + ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
>
> Should be:
>
> return ahnd ? get_simple_h2l_ahnd(fd, 0) : 0;
>
> Explanation below.
I would like to keep it here, get_simple checks for relocs
before actually doing anything and that runs execbuf. I like to
avoid any syscall here, if possible.
> > +}
> > +
> > +static struct intel_bb *bb_create(int i915, uint32_t size)
> > +{
> > + return ahnd ? intel_bb_create_no_relocs(i915, size) :
> > + intel_bb_create_with_relocs(i915, size);
> > +}
> > +
> > static void buffers_init(struct buffers *b,
> > const char *name,
> > const struct create *create,
> > @@ -796,7 +850,7 @@ static void buffers_init(struct buffers *b,
> > igt_assert(b->src);
> > b->dst = b->src + num_buffers;
> >
> > - b->ibb = intel_bb_create(_fd, 4096);
> > + b->ibb = bb_create(_fd, 4096);
> > }
> >
> > static void buffers_destroy(struct buffers *b)
> > @@ -829,6 +883,27 @@ static void buffers_destroy(struct buffers *b)
> > }
> > }
> >
> > +static void bb_destroy(struct buffers *b)
> > +{
> > + if (b->ibb) {
> > + intel_bb_destroy(b->ibb);
> > + b->ibb = NULL;
> > + }
> > +}
> > +
> > +static void __bufs_destroy(struct buffers *b)
> > +{
> > + buffers_destroy(b);
> > + if (b->ibb) {
> > + intel_bb_destroy(b->ibb);
> > + b->ibb = NULL;
> > + }
> > + if (b->bops) {
> > + buf_ops_destroy(b->bops);
> > + b->bops = NULL;
> > + }
> > +}
> > +
> > static void buffers_create(struct buffers *b)
> > {
> > int count = b->num_buffers;
> > @@ -838,32 +913,57 @@ static void buffers_create(struct buffers *b)
> > igt_assert(b->count == 0);
> > b->count = count;
> >
> > + ahnd = alloc_open();
> > for (int i = 0; i < count; i++) {
> > b->src[i] = b->mode->create_bo(b);
> > b->dst[i] = b->mode->create_bo(b);
> > }
> > b->spare = b->mode->create_bo(b);
> > b->snoop = snoop_create_bo(b);
> > + if (b->ibb)
> > + intel_bb_destroy(b->ibb);
> > +
> > + b->ibb = bb_create(fd, 4096);
> > }
> >
> > static void buffers_reset(struct buffers *b)
> > {
> > b->bops = buf_ops_create(fd);
> > - b->ibb = intel_bb_create(fd, 4096);
> > + b->ibb = bb_create(fd, 4096);
> > +}
> > +
> > +static void __buffers_create(struct buffers *b)
> > +{
> > + b->bops = buf_ops_create(fd);
> > + igt_assert(b->bops);
> > + igt_assert(b->num_buffers > 0);
> > + igt_assert(b->mode);
> > + igt_assert(b->mode->create_bo);
> > +
> > + b->count = 0;
> > + for (int i = 0; i < b->num_buffers; i++) {
> > + b->src[i] = b->mode->create_bo(b);
> > + b->dst[i] = b->mode->create_bo(b);
> > + }
> > + b->count = b->num_buffers;
> > + b->spare = b->mode->create_bo(b);
> > + b->snoop = snoop_create_bo(b);
> > + ahnd = alloc_open();
> > + b->ibb = bb_create(fd, 4096);
> > }
> >
> > static void buffers_fini(struct buffers *b)
> > {
> > if (b->bops == NULL)
> > return;
> > -
> > buffers_destroy(b);
> >
> > free(b->tmp);
> > free(b->src);
> > -
> > - intel_bb_destroy(b->ibb);
> > - buf_ops_destroy(b->bops);
> > + if (b->ibb)
> > + intel_bb_destroy(b->ibb);
> > + if (b->bops)
> > + buf_ops_destroy(b->bops);
> >
> > memset(b, 0, sizeof(*b));
> > }
> > @@ -1306,6 +1406,8 @@ static void run_single(struct buffers *buffers,
> > do_hang do_hang_func)
> > {
> > pass = 0;
> > + bb_destroy(buffers);
> > + buffers->ibb = bb_create(fd, 4096);
> > do_test_func(buffers, do_copy_func, do_hang_func);
> > igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> > }
> > @@ -1316,6 +1418,8 @@ static void run_interruptible(struct buffers *buffers,
> > do_hang do_hang_func)
> > {
> > pass = 0;
> > + bb_destroy(buffers);
> > + buffers->ibb = bb_create(fd, 4096);
> > igt_while_interruptible(true)
> > do_test_func(buffers, do_copy_func, do_hang_func);
> > igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> > @@ -1332,10 +1436,18 @@ static void run_child(struct buffers *buffers,
> > * leading to the child closing an object without the parent knowing.
> > */
> > pass = 0;
> > - igt_fork(child, 1)
> > + __bufs_destroy(buffers);
> > +
> > + igt_fork(child, 1) {
> > + /* recreate process local variables */
> > + intel_allocator_init();
> > + __buffers_create(buffers);
> > do_test_func(buffers, do_copy_func, do_hang_func);
> > + }
> > igt_waitchildren();
> > +
> > igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> > + buffers_reset(buffers);
> > }
> >
> > static void __run_forked(struct buffers *buffers,
> > @@ -1346,24 +1458,20 @@ static void __run_forked(struct buffers *buffers,
> >
> > {
> > /* purge the caches before cloing the process */
> > - buffers_destroy(buffers);
> > - intel_bb_destroy(buffers->ibb);
> > - buf_ops_destroy(buffers->bops);
> > + __bufs_destroy(buffers);
> >
> > igt_fork(child, num_children) {
> > int num_buffers;
> >
> > /* recreate process local variables */
> > fd = gem_reopen_driver(fd);
> > -
> > + intel_allocator_init(); /* detach from thread */
> > num_buffers = buffers->num_buffers / num_children;
> > num_buffers += MIN_BUFFERS;
> > if (num_buffers < buffers->num_buffers)
> > buffers->num_buffers = num_buffers;
> >
> > - buffers_reset(buffers);
> > - buffers_create(buffers);
> > -
> > + __buffers_create(buffers);
> > igt_while_interruptible(interrupt) {
> > for (pass = 0; pass < loops; pass++)
> > do_test_func(buffers,
> > @@ -1773,6 +1881,7 @@ igt_main
> > { "16MiB", 2048, 2048 },
> > { NULL}
> > };
> > +
> > uint64_t pin_sz = 0;
> > void *pinned = NULL;
> > char name[80];
> > @@ -1792,6 +1901,12 @@ igt_main
> > rendercopy = igt_get_render_copyfunc(devid);
> >
> > vgem_drv = __drm_open_driver(DRIVER_VGEM);
> > +
> > + ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> > + ALLOC_STRATEGY_HIGH_TO_LOW, 0);
>
> You will use allocator always, even on gens < 8 where offsets could be
> altered by relocations. This should look:
>
> ahnd = get_simple_h2l_ahnd(fd, 0);
I agree that here it can be used once.
--
Kamil
> > + put_ahnd(ahnd);
> > + if (ahnd)
> > + intel_bb_track(true);
> > }
> >
> > for (const struct create *c = create; c->name; c++) {
> > @@ -1864,7 +1979,6 @@ igt_main
> > igt_fixture
> > igt_stop_shrink_helper();
> > }
> > -
> > /* Use the entire mappable aperture, force swapping */
> > snprintf(name, sizeof(name), "%s%s-%s",
> > c->name, s->name, "swap");
> > --
> > 2.32.0
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-28 16:55 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
@ 2022-03-29 8:10 ` Zbigniew Kempczyński
2022-03-29 12:56 ` Kamil Konieczny
0 siblings, 1 reply; 16+ messages in thread
From: Zbigniew Kempczyński @ 2022-03-29 8:10 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
On Mon, Mar 28, 2022 at 06:55:45PM +0200, Kamil Konieczny wrote:
> Add noreloc mode for GPU gens without relocations. Also
> while at this, add some caching for required properties.
> Change also snoop function so it will work on DG1.
>
> Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
> and 256KiB with modified drm-tip to allow softpinning.
>
> v7: rebase, cleanup bit17 caching (Zbigniew comments)
> v6: correct comment, rewrite bit17 caching (Zbigniew)
> v5: rebase, fix caching in bit17_require, changes according
> to Zbigniew review: simplify cache of !gem_has_llc, drop
> multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
> correct offset and flags
> v4: corrected alloc_open and first ahnd setting
>
> Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> tests/i915/gem_concurrent_all.c | 176 ++++++++++++++++++++++++++------
> 1 file changed, 145 insertions(+), 31 deletions(-)
>
> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> index d0f9b62e..7a91434c 100644
> --- a/tests/i915/gem_concurrent_all.c
> +++ b/tests/i915/gem_concurrent_all.c
> @@ -60,6 +60,7 @@ int fd, devid, gen;
> int vgem_drv = -1;
> int all;
> int pass;
> +uint64_t ahnd;
>
> struct create {
> const char *name;
> @@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
>
> static void create_snoop_require(const struct create *create, unsigned count)
> {
> + static bool check_llc = true;
> + static bool has_snoop;
> +
> create_cpu_require(create, count);
> - igt_require(!gem_has_llc(fd));
> + if (check_llc) {
> + has_snoop = !gem_has_llc(fd);
> + check_llc = false;
> + }
> +
> + igt_require(has_snoop);
> }
>
> static struct intel_buf *
> @@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
> struct intel_buf *buf;
>
> buf = unmapped_create_bo(b);
> - gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
> + __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
>
> return buf;
> }
> @@ -572,22 +581,33 @@ gttX_create_bo(const struct buffers *b)
>
> static void bit17_require(void)
> {
> - static struct drm_i915_gem_get_tiling2 {
> - uint32_t handle;
> - uint32_t tiling_mode;
> - uint32_t swizzle_mode;
> - uint32_t phys_swizzle_mode;
> - } arg;
> + static bool has_tiling2, checked;
> +
> #define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
>
> - if (arg.handle == 0) {
> + if (!checked) {
> + struct drm_i915_gem_get_tiling2 {
> + uint32_t handle;
> + uint32_t tiling_mode;
> + uint32_t swizzle_mode;
> + uint32_t phys_swizzle_mode;
> + } arg = {};
> + int err;
> +
> + checked = true;
> arg.handle = gem_create(fd, 4096);
> - gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + if (!err) {
> + igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> + if (!errno && arg.phys_swizzle_mode == arg.swizzle_mode)
> + has_tiling2 = true;
> + }
>
> - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> + errno = 0;
> gem_close(fd, arg.handle);
> }
> - igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
> +
> + igt_require(has_tiling2);
> }
This looks much better.
>
> static void wc_require(void)
> @@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> struct drm_i915_gem_exec_object2 gem_exec[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> uint32_t tmp[10], *b;
> + uint64_t addr = 0;
>
> memset(reloc, 0, sizeof(reloc));
> memset(gem_exec, 0, sizeof(gem_exec));
> memset(&execbuf, 0, sizeof(execbuf));
>
> + if (ahnd) {
> + addr = buf->addr.offset;
> + if (INVALID_ADDR(addr)) {
> + addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
> + buf->handle, buf->size, 0);
> + buf->addr.offset = addr;
> + }
> + }
> +
> b = tmp;
> *b++ = XY_COLOR_BLT_CMD_NOLEN |
> ((gen >= 8) ? 5 : 4) |
> @@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> reloc[0].target_handle = buf->handle;
> reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
> reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
> - *b++ = 0;
> + *b++ = addr;
> if (gen >= 8)
> - *b++ = 0;
> + *b++ = addr >> 32;
> *b++ = val;
> *b++ = MI_BATCH_BUFFER_END;
> if ((b - tmp) & 1)
> @@ -703,8 +733,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
>
> gem_exec[1].handle = gem_create(fd, 4096);
> - gem_exec[1].relocation_count = 1;
> - gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + if (!ahnd) {
> + gem_exec[1].relocation_count = 1;
> + gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + } else {
> + gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
> + gem_exec[1].handle,
> + 4096, 0));
> + gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +
> + gem_exec[0].offset = CANONICAL(buf->addr.offset);
> + gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + }
>
> execbuf.buffers_ptr = to_user_pointer(gem_exec);
> execbuf.buffer_count = 2;
> @@ -716,6 +757,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_execbuf(fd, &execbuf);
>
> gem_close(fd, gem_exec[1].handle);
> + put_offset(ahnd, gem_exec[1].handle);
> }
>
> static void
> @@ -766,6 +808,18 @@ static bool set_max_map_count(int num_buffers)
> return max > num_buffers;
> }
>
> +static uint64_t alloc_open(void)
> +{
> + return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
Should be:
return ahnd ? get_simple_h2l_ahnd(fd, 0) : 0;
Explanation below.
> +}
> +
> +static struct intel_bb *bb_create(int i915, uint32_t size)
> +{
> + return ahnd ? intel_bb_create_no_relocs(i915, size) :
> + intel_bb_create_with_relocs(i915, size);
> +}
> +
> static void buffers_init(struct buffers *b,
> const char *name,
> const struct create *create,
> @@ -796,7 +850,7 @@ static void buffers_init(struct buffers *b,
> igt_assert(b->src);
> b->dst = b->src + num_buffers;
>
> - b->ibb = intel_bb_create(_fd, 4096);
> + b->ibb = bb_create(_fd, 4096);
> }
>
> static void buffers_destroy(struct buffers *b)
> @@ -829,6 +883,27 @@ static void buffers_destroy(struct buffers *b)
> }
> }
>
> +static void bb_destroy(struct buffers *b)
> +{
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> +}
> +
> +static void __bufs_destroy(struct buffers *b)
> +{
> + buffers_destroy(b);
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> + if (b->bops) {
> + buf_ops_destroy(b->bops);
> + b->bops = NULL;
> + }
> +}
> +
> static void buffers_create(struct buffers *b)
> {
> int count = b->num_buffers;
> @@ -838,32 +913,57 @@ static void buffers_create(struct buffers *b)
> igt_assert(b->count == 0);
> b->count = count;
>
> + ahnd = alloc_open();
> for (int i = 0; i < count; i++) {
> b->src[i] = b->mode->create_bo(b);
> b->dst[i] = b->mode->create_bo(b);
> }
> b->spare = b->mode->create_bo(b);
> b->snoop = snoop_create_bo(b);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> +
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_reset(struct buffers *b)
> {
> b->bops = buf_ops_create(fd);
> - b->ibb = intel_bb_create(fd, 4096);
> + b->ibb = bb_create(fd, 4096);
> +}
> +
> +static void __buffers_create(struct buffers *b)
> +{
> + b->bops = buf_ops_create(fd);
> + igt_assert(b->bops);
> + igt_assert(b->num_buffers > 0);
> + igt_assert(b->mode);
> + igt_assert(b->mode->create_bo);
> +
> + b->count = 0;
> + for (int i = 0; i < b->num_buffers; i++) {
> + b->src[i] = b->mode->create_bo(b);
> + b->dst[i] = b->mode->create_bo(b);
> + }
> + b->count = b->num_buffers;
> + b->spare = b->mode->create_bo(b);
> + b->snoop = snoop_create_bo(b);
> + ahnd = alloc_open();
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_fini(struct buffers *b)
> {
> if (b->bops == NULL)
> return;
> -
> buffers_destroy(b);
>
> free(b->tmp);
> free(b->src);
> -
> - intel_bb_destroy(b->ibb);
> - buf_ops_destroy(b->bops);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> + if (b->bops)
> + buf_ops_destroy(b->bops);
>
> memset(b, 0, sizeof(*b));
> }
> @@ -1306,6 +1406,8 @@ static void run_single(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> }
> @@ -1316,6 +1418,8 @@ static void run_interruptible(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> igt_while_interruptible(true)
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> @@ -1332,10 +1436,18 @@ static void run_child(struct buffers *buffers,
> * leading to the child closing an object without the parent knowing.
> */
> pass = 0;
> - igt_fork(child, 1)
> + __bufs_destroy(buffers);
> +
> + igt_fork(child, 1) {
> + /* recreate process local variables */
> + intel_allocator_init();
> + __buffers_create(buffers);
> do_test_func(buffers, do_copy_func, do_hang_func);
> + }
> igt_waitchildren();
> +
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> + buffers_reset(buffers);
> }
>
> static void __run_forked(struct buffers *buffers,
> @@ -1346,24 +1458,20 @@ static void __run_forked(struct buffers *buffers,
>
> {
> /* purge the caches before cloing the process */
> - buffers_destroy(buffers);
> - intel_bb_destroy(buffers->ibb);
> - buf_ops_destroy(buffers->bops);
> + __bufs_destroy(buffers);
>
> igt_fork(child, num_children) {
> int num_buffers;
>
> /* recreate process local variables */
> fd = gem_reopen_driver(fd);
> -
> + intel_allocator_init(); /* detach from thread */
> num_buffers = buffers->num_buffers / num_children;
> num_buffers += MIN_BUFFERS;
> if (num_buffers < buffers->num_buffers)
> buffers->num_buffers = num_buffers;
>
> - buffers_reset(buffers);
> - buffers_create(buffers);
> -
> + __buffers_create(buffers);
> igt_while_interruptible(interrupt) {
> for (pass = 0; pass < loops; pass++)
> do_test_func(buffers,
> @@ -1773,6 +1881,7 @@ igt_main
> { "16MiB", 2048, 2048 },
> { NULL}
> };
> +
> uint64_t pin_sz = 0;
> void *pinned = NULL;
> char name[80];
> @@ -1792,6 +1901,12 @@ igt_main
> rendercopy = igt_get_render_copyfunc(devid);
>
> vgem_drv = __drm_open_driver(DRIVER_VGEM);
> +
> + ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_HIGH_TO_LOW, 0);
You will use allocator always, even on gens < 8 where offsets could be
altered by relocations. This should look:
ahnd = get_simple_h2l_ahnd(fd, 0);
--
Zbigniew
> + put_ahnd(ahnd);
> + if (ahnd)
> + intel_bb_track(true);
> }
>
> for (const struct create *c = create; c->name; c++) {
> @@ -1864,7 +1979,6 @@ igt_main
> igt_fixture
> igt_stop_shrink_helper();
> }
> -
> /* Use the entire mappable aperture, force swapping */
> snprintf(name, sizeof(name), "%s%s-%s",
> c->name, s->name, "swap");
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-28 16:55 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
@ 2022-03-28 16:55 ` Kamil Konieczny
2022-03-29 8:10 ` Zbigniew Kempczyński
0 siblings, 1 reply; 16+ messages in thread
From: Kamil Konieczny @ 2022-03-28 16:55 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
and 256KiB with modified drm-tip to allow softpinning.
v7: rebase, cleanup bit17 caching (Zbigniew comments)
v6: correct comment, rewrite bit17 caching (Zbigniew)
v5: rebase, fix caching in bit17_require, changes according
to Zbigniew review: simplify cache of !gem_has_llc, drop
multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
correct offset and flags
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_concurrent_all.c | 176 ++++++++++++++++++++++++++------
1 file changed, 145 insertions(+), 31 deletions(-)
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index d0f9b62e..7a91434c 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -60,6 +60,7 @@ int fd, devid, gen;
int vgem_drv = -1;
int all;
int pass;
+uint64_t ahnd;
struct create {
const char *name;
@@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
+ static bool check_llc = true;
+ static bool has_snoop;
+
create_cpu_require(create, count);
- igt_require(!gem_has_llc(fd));
+ if (check_llc) {
+ has_snoop = !gem_has_llc(fd);
+ check_llc = false;
+ }
+
+ igt_require(has_snoop);
}
static struct intel_buf *
@@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
struct intel_buf *buf;
buf = unmapped_create_bo(b);
- gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
+ __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
return buf;
}
@@ -572,22 +581,33 @@ gttX_create_bo(const struct buffers *b)
static void bit17_require(void)
{
- static struct drm_i915_gem_get_tiling2 {
- uint32_t handle;
- uint32_t tiling_mode;
- uint32_t swizzle_mode;
- uint32_t phys_swizzle_mode;
- } arg;
+ static bool has_tiling2, checked;
+
#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
- if (arg.handle == 0) {
+ if (!checked) {
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg = {};
+ int err;
+
+ checked = true;
arg.handle = gem_create(fd, 4096);
- gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ if (!err) {
+ igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ if (!errno && arg.phys_swizzle_mode == arg.swizzle_mode)
+ has_tiling2 = true;
+ }
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ errno = 0;
gem_close(fd, arg.handle);
}
- igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+
+ igt_require(has_tiling2);
}
static void wc_require(void)
@@ -670,11 +690,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf;
uint32_t tmp[10], *b;
+ uint64_t addr = 0;
memset(reloc, 0, sizeof(reloc));
memset(gem_exec, 0, sizeof(gem_exec));
memset(&execbuf, 0, sizeof(execbuf));
+ if (ahnd) {
+ addr = buf->addr.offset;
+ if (INVALID_ADDR(addr)) {
+ addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
+ buf->handle, buf->size, 0);
+ buf->addr.offset = addr;
+ }
+ }
+
b = tmp;
*b++ = XY_COLOR_BLT_CMD_NOLEN |
((gen >= 8) ? 5 : 4) |
@@ -691,9 +721,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
reloc[0].target_handle = buf->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
- *b++ = 0;
+ *b++ = addr;
if (gen >= 8)
- *b++ = 0;
+ *b++ = addr >> 32;
*b++ = val;
*b++ = MI_BATCH_BUFFER_END;
if ((b - tmp) & 1)
@@ -703,8 +733,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
gem_exec[1].handle = gem_create(fd, 4096);
- gem_exec[1].relocation_count = 1;
- gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (!ahnd) {
+ gem_exec[1].relocation_count = 1;
+ gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
+ gem_exec[1].handle,
+ 4096, 0));
+ gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ gem_exec[0].offset = CANONICAL(buf->addr.offset);
+ gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ }
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 2;
@@ -716,6 +757,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_execbuf(fd, &execbuf);
gem_close(fd, gem_exec[1].handle);
+ put_offset(ahnd, gem_exec[1].handle);
}
static void
@@ -766,6 +808,18 @@ static bool set_max_map_count(int num_buffers)
return max > num_buffers;
}
+static uint64_t alloc_open(void)
+{
+ return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
+}
+
+static struct intel_bb *bb_create(int i915, uint32_t size)
+{
+ return ahnd ? intel_bb_create_no_relocs(i915, size) :
+ intel_bb_create_with_relocs(i915, size);
+}
+
static void buffers_init(struct buffers *b,
const char *name,
const struct create *create,
@@ -796,7 +850,7 @@ static void buffers_init(struct buffers *b,
igt_assert(b->src);
b->dst = b->src + num_buffers;
- b->ibb = intel_bb_create(_fd, 4096);
+ b->ibb = bb_create(_fd, 4096);
}
static void buffers_destroy(struct buffers *b)
@@ -829,6 +883,27 @@ static void buffers_destroy(struct buffers *b)
}
}
+static void bb_destroy(struct buffers *b)
+{
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+}
+
+static void __bufs_destroy(struct buffers *b)
+{
+ buffers_destroy(b);
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+ if (b->bops) {
+ buf_ops_destroy(b->bops);
+ b->bops = NULL;
+ }
+}
+
static void buffers_create(struct buffers *b)
{
int count = b->num_buffers;
@@ -838,32 +913,57 @@ static void buffers_create(struct buffers *b)
igt_assert(b->count == 0);
b->count = count;
+ ahnd = alloc_open();
for (int i = 0; i < count; i++) {
b->src[i] = b->mode->create_bo(b);
b->dst[i] = b->mode->create_bo(b);
}
b->spare = b->mode->create_bo(b);
b->snoop = snoop_create_bo(b);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_reset(struct buffers *b)
{
b->bops = buf_ops_create(fd);
- b->ibb = intel_bb_create(fd, 4096);
+ b->ibb = bb_create(fd, 4096);
+}
+
+static void __buffers_create(struct buffers *b)
+{
+ b->bops = buf_ops_create(fd);
+ igt_assert(b->bops);
+ igt_assert(b->num_buffers > 0);
+ igt_assert(b->mode);
+ igt_assert(b->mode->create_bo);
+
+ b->count = 0;
+ for (int i = 0; i < b->num_buffers; i++) {
+ b->src[i] = b->mode->create_bo(b);
+ b->dst[i] = b->mode->create_bo(b);
+ }
+ b->count = b->num_buffers;
+ b->spare = b->mode->create_bo(b);
+ b->snoop = snoop_create_bo(b);
+ ahnd = alloc_open();
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_fini(struct buffers *b)
{
if (b->bops == NULL)
return;
-
buffers_destroy(b);
free(b->tmp);
free(b->src);
-
- intel_bb_destroy(b->ibb);
- buf_ops_destroy(b->bops);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+ if (b->bops)
+ buf_ops_destroy(b->bops);
memset(b, 0, sizeof(*b));
}
@@ -1306,6 +1406,8 @@ static void run_single(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
@@ -1316,6 +1418,8 @@ static void run_interruptible(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
igt_while_interruptible(true)
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1332,10 +1436,18 @@ static void run_child(struct buffers *buffers,
* leading to the child closing an object without the parent knowing.
*/
pass = 0;
- igt_fork(child, 1)
+ __bufs_destroy(buffers);
+
+ igt_fork(child, 1) {
+ /* recreate process local variables */
+ intel_allocator_init();
+ __buffers_create(buffers);
do_test_func(buffers, do_copy_func, do_hang_func);
+ }
igt_waitchildren();
+
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ buffers_reset(buffers);
}
static void __run_forked(struct buffers *buffers,
@@ -1346,24 +1458,20 @@ static void __run_forked(struct buffers *buffers,
{
/* purge the caches before cloing the process */
- buffers_destroy(buffers);
- intel_bb_destroy(buffers->ibb);
- buf_ops_destroy(buffers->bops);
+ __bufs_destroy(buffers);
igt_fork(child, num_children) {
int num_buffers;
/* recreate process local variables */
fd = gem_reopen_driver(fd);
-
+ intel_allocator_init(); /* detach from thread */
num_buffers = buffers->num_buffers / num_children;
num_buffers += MIN_BUFFERS;
if (num_buffers < buffers->num_buffers)
buffers->num_buffers = num_buffers;
- buffers_reset(buffers);
- buffers_create(buffers);
-
+ __buffers_create(buffers);
igt_while_interruptible(interrupt) {
for (pass = 0; pass < loops; pass++)
do_test_func(buffers,
@@ -1773,6 +1881,7 @@ igt_main
{ "16MiB", 2048, 2048 },
{ NULL}
};
+
uint64_t pin_sz = 0;
void *pinned = NULL;
char name[80];
@@ -1792,6 +1901,12 @@ igt_main
rendercopy = igt_get_render_copyfunc(devid);
vgem_drv = __drm_open_driver(DRIVER_VGEM);
+
+ ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0);
+ put_ahnd(ahnd);
+ if (ahnd)
+ intel_bb_track(true);
}
for (const struct create *c = create; c->name; c++) {
@@ -1864,7 +1979,6 @@ igt_main
igt_fixture
igt_stop_shrink_helper();
}
-
/* Use the entire mappable aperture, force swapping */
snprintf(name, sizeof(name), "%s%s-%s",
c->name, s->name, "swap");
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-28 8:31 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
@ 2022-03-28 12:33 ` Zbigniew Kempczyński
0 siblings, 0 replies; 16+ messages in thread
From: Zbigniew Kempczyński @ 2022-03-28 12:33 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
On Mon, Mar 28, 2022 at 10:31:40AM +0200, Kamil Konieczny wrote:
> Add noreloc mode for GPU gens without relocations. Also
> while at this, add some caching for required properties.
> Change also snoop function so it will work on DG1.
>
> Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
> and 256KiB with modified drm-tip to allow softpinning.
>
> v6: correct comment, rewrite bit17 caching (Zbigniew)
> v5: rebase, fix caching in bit17_require, changes according
> to Zbigniew review: simplify cache of !gem_has_llc, drop
> multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
> correct offset and flags
> v4: corrected alloc_open and first ahnd setting
>
> Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> tests/i915/gem_concurrent_all.c | 167 +++++++++++++++++++++++++++-----
> 1 file changed, 144 insertions(+), 23 deletions(-)
>
> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> index d0f9b62e..3e650233 100644
> --- a/tests/i915/gem_concurrent_all.c
> +++ b/tests/i915/gem_concurrent_all.c
> @@ -60,6 +60,7 @@ int fd, devid, gen;
> int vgem_drv = -1;
> int all;
> int pass;
> +uint64_t ahnd;
>
> struct create {
> const char *name;
> @@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
>
> static void create_snoop_require(const struct create *create, unsigned count)
> {
> + static bool check_llc = true;
> + static bool has_snoop;
> +
> create_cpu_require(create, count);
> - igt_require(!gem_has_llc(fd));
> + if (check_llc) {
> + has_snoop = !gem_has_llc(fd);
> + check_llc = false;
> + }
> +
> + igt_require(has_snoop);
> }
>
> static struct intel_buf *
> @@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
> struct intel_buf *buf;
>
> buf = unmapped_create_bo(b);
> - gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
> + __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
>
> return buf;
> }
> @@ -581,11 +590,29 @@ static void bit17_require(void)
> #define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
>
> if (arg.handle == 0) {
> + bool has_tiling2;
> + int err_tiling;
> +
> + has_tiling2 = false;
> arg.handle = gem_create(fd, 4096);
> - gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + err_tiling = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + if (!err_tiling) {
> + igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> + if (!errno)
> + has_tiling2 = true;
> +
> + errno = 0;
> + }
>
> - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> gem_close(fd, arg.handle);
> + if (err_tiling || !has_tiling2)
> + if (arg.phys_swizzle_mode == arg.swizzle_mode) {
> + arg.phys_swizzle_mode = 0;
> + arg.swizzle_mode = -1;
> + }
> +
> + igt_require(!err_tiling);
> + igt_require(has_tiling2);
Still little bit overengineered. set/get were provided in pairs, so
trying to set on gen which doesn't support can immediately go out
with require (apart of gem_close() which should be done to avoid
fd leakage). So calling get-tiling and gathering / faking information
is a little bit confusing.
--
Zbigniew
> }
> igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
> }
> @@ -670,11 +697,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> struct drm_i915_gem_exec_object2 gem_exec[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> uint32_t tmp[10], *b;
> + uint64_t addr = 0;
>
> memset(reloc, 0, sizeof(reloc));
> memset(gem_exec, 0, sizeof(gem_exec));
> memset(&execbuf, 0, sizeof(execbuf));
>
> + if (ahnd) {
> + addr = buf->addr.offset;
> + if (INVALID_ADDR(addr)) {
> + addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
> + buf->handle, buf->size, 0);
> + buf->addr.offset = addr;
> + }
> + }
> +
> b = tmp;
> *b++ = XY_COLOR_BLT_CMD_NOLEN |
> ((gen >= 8) ? 5 : 4) |
> @@ -691,9 +728,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> reloc[0].target_handle = buf->handle;
> reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
> reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
> - *b++ = 0;
> + *b++ = addr;
> if (gen >= 8)
> - *b++ = 0;
> + *b++ = addr >> 32;
> *b++ = val;
> *b++ = MI_BATCH_BUFFER_END;
> if ((b - tmp) & 1)
> @@ -703,8 +740,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
>
> gem_exec[1].handle = gem_create(fd, 4096);
> - gem_exec[1].relocation_count = 1;
> - gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + if (!ahnd) {
> + gem_exec[1].relocation_count = 1;
> + gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + } else {
> + gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
> + gem_exec[1].handle,
> + 4096, 0));
> + gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +
> + gem_exec[0].offset = CANONICAL(buf->addr.offset);
> + gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + }
>
> execbuf.buffers_ptr = to_user_pointer(gem_exec);
> execbuf.buffer_count = 2;
> @@ -716,6 +764,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_execbuf(fd, &execbuf);
>
> gem_close(fd, gem_exec[1].handle);
> + put_offset(ahnd, gem_exec[1].handle);
> }
>
> static void
> @@ -766,6 +815,18 @@ static bool set_max_map_count(int num_buffers)
> return max > num_buffers;
> }
>
> +static uint64_t alloc_open(void)
> +{
> + return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
> +}
> +
> +static struct intel_bb *bb_create(int i915, uint32_t size)
> +{
> + return ahnd ? intel_bb_create_no_relocs(i915, size) :
> + intel_bb_create_with_relocs(i915, size);
> +}
> +
> static void buffers_init(struct buffers *b,
> const char *name,
> const struct create *create,
> @@ -796,7 +857,7 @@ static void buffers_init(struct buffers *b,
> igt_assert(b->src);
> b->dst = b->src + num_buffers;
>
> - b->ibb = intel_bb_create(_fd, 4096);
> + b->ibb = bb_create(_fd, 4096);
> }
>
> static void buffers_destroy(struct buffers *b)
> @@ -829,6 +890,27 @@ static void buffers_destroy(struct buffers *b)
> }
> }
>
> +static void bb_destroy(struct buffers *b)
> +{
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> +}
> +
> +static void __bufs_destroy(struct buffers *b)
> +{
> + buffers_destroy(b);
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> + if (b->bops) {
> + buf_ops_destroy(b->bops);
> + b->bops = NULL;
> + }
> +}
> +
> static void buffers_create(struct buffers *b)
> {
> int count = b->num_buffers;
> @@ -838,32 +920,57 @@ static void buffers_create(struct buffers *b)
> igt_assert(b->count == 0);
> b->count = count;
>
> + ahnd = alloc_open();
> for (int i = 0; i < count; i++) {
> b->src[i] = b->mode->create_bo(b);
> b->dst[i] = b->mode->create_bo(b);
> }
> b->spare = b->mode->create_bo(b);
> b->snoop = snoop_create_bo(b);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> +
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_reset(struct buffers *b)
> {
> b->bops = buf_ops_create(fd);
> - b->ibb = intel_bb_create(fd, 4096);
> + b->ibb = bb_create(fd, 4096);
> +}
> +
> +static void __buffers_create(struct buffers *b)
> +{
> + b->bops = buf_ops_create(fd);
> + igt_assert(b->bops);
> + igt_assert(b->num_buffers > 0);
> + igt_assert(b->mode);
> + igt_assert(b->mode->create_bo);
> +
> + b->count = 0;
> + for (int i = 0; i < b->num_buffers; i++) {
> + b->src[i] = b->mode->create_bo(b);
> + b->dst[i] = b->mode->create_bo(b);
> + }
> + b->count = b->num_buffers;
> + b->spare = b->mode->create_bo(b);
> + b->snoop = snoop_create_bo(b);
> + ahnd = alloc_open();
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_fini(struct buffers *b)
> {
> if (b->bops == NULL)
> return;
> -
> buffers_destroy(b);
>
> free(b->tmp);
> free(b->src);
> -
> - intel_bb_destroy(b->ibb);
> - buf_ops_destroy(b->bops);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> + if (b->bops)
> + buf_ops_destroy(b->bops);
>
> memset(b, 0, sizeof(*b));
> }
> @@ -1306,6 +1413,8 @@ static void run_single(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> }
> @@ -1316,6 +1425,8 @@ static void run_interruptible(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> igt_while_interruptible(true)
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> @@ -1332,10 +1443,18 @@ static void run_child(struct buffers *buffers,
> * leading to the child closing an object without the parent knowing.
> */
> pass = 0;
> - igt_fork(child, 1)
> + __bufs_destroy(buffers);
> +
> + igt_fork(child, 1) {
> + /* recreate process local variables */
> + intel_allocator_init();
> + __buffers_create(buffers);
> do_test_func(buffers, do_copy_func, do_hang_func);
> + }
> igt_waitchildren();
> +
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> + buffers_reset(buffers);
> }
>
> static void __run_forked(struct buffers *buffers,
> @@ -1346,24 +1465,20 @@ static void __run_forked(struct buffers *buffers,
>
> {
> /* purge the caches before cloing the process */
> - buffers_destroy(buffers);
> - intel_bb_destroy(buffers->ibb);
> - buf_ops_destroy(buffers->bops);
> + __bufs_destroy(buffers);
>
> igt_fork(child, num_children) {
> int num_buffers;
>
> /* recreate process local variables */
> fd = gem_reopen_driver(fd);
> -
> + intel_allocator_init(); /* detach from thread */
> num_buffers = buffers->num_buffers / num_children;
> num_buffers += MIN_BUFFERS;
> if (num_buffers < buffers->num_buffers)
> buffers->num_buffers = num_buffers;
>
> - buffers_reset(buffers);
> - buffers_create(buffers);
> -
> + __buffers_create(buffers);
> igt_while_interruptible(interrupt) {
> for (pass = 0; pass < loops; pass++)
> do_test_func(buffers,
> @@ -1773,6 +1888,7 @@ igt_main
> { "16MiB", 2048, 2048 },
> { NULL}
> };
> +
> uint64_t pin_sz = 0;
> void *pinned = NULL;
> char name[80];
> @@ -1792,6 +1908,12 @@ igt_main
> rendercopy = igt_get_render_copyfunc(devid);
>
> vgem_drv = __drm_open_driver(DRIVER_VGEM);
> +
> + ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_HIGH_TO_LOW, 0);
> + put_ahnd(ahnd);
> + if (ahnd)
> + intel_bb_track(true);
> }
>
> for (const struct create *c = create; c->name; c++) {
> @@ -1864,7 +1986,6 @@ igt_main
> igt_fixture
> igt_stop_shrink_helper();
> }
> -
> /* Use the entire mappable aperture, force swapping */
> snprintf(name, sizeof(name), "%s%s-%s",
> c->name, s->name, "swap");
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-28 8:31 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
@ 2022-03-28 8:31 ` Kamil Konieczny
2022-03-28 12:33 ` Zbigniew Kempczyński
0 siblings, 1 reply; 16+ messages in thread
From: Kamil Konieczny @ 2022-03-28 8:31 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
and 256KiB with modified drm-tip to allow softpinning.
v6: correct comment, rewrite bit17 caching (Zbigniew)
v5: rebase, fix caching in bit17_require, changes according
to Zbigniew review: simplify cache of !gem_has_llc, drop
multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
correct offset and flags
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_concurrent_all.c | 167 +++++++++++++++++++++++++++-----
1 file changed, 144 insertions(+), 23 deletions(-)
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index d0f9b62e..3e650233 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -60,6 +60,7 @@ int fd, devid, gen;
int vgem_drv = -1;
int all;
int pass;
+uint64_t ahnd;
struct create {
const char *name;
@@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
+ static bool check_llc = true;
+ static bool has_snoop;
+
create_cpu_require(create, count);
- igt_require(!gem_has_llc(fd));
+ if (check_llc) {
+ has_snoop = !gem_has_llc(fd);
+ check_llc = false;
+ }
+
+ igt_require(has_snoop);
}
static struct intel_buf *
@@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
struct intel_buf *buf;
buf = unmapped_create_bo(b);
- gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
+ __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
return buf;
}
@@ -581,11 +590,29 @@ static void bit17_require(void)
#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
if (arg.handle == 0) {
+ bool has_tiling2;
+ int err_tiling;
+
+ has_tiling2 = false;
arg.handle = gem_create(fd, 4096);
- gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ err_tiling = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ if (!err_tiling) {
+ igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ if (!errno)
+ has_tiling2 = true;
+
+ errno = 0;
+ }
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
gem_close(fd, arg.handle);
+ if (err_tiling || !has_tiling2)
+ if (arg.phys_swizzle_mode == arg.swizzle_mode) {
+ arg.phys_swizzle_mode = 0;
+ arg.swizzle_mode = -1;
+ }
+
+ igt_require(!err_tiling);
+ igt_require(has_tiling2);
}
igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
}
@@ -670,11 +697,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf;
uint32_t tmp[10], *b;
+ uint64_t addr = 0;
memset(reloc, 0, sizeof(reloc));
memset(gem_exec, 0, sizeof(gem_exec));
memset(&execbuf, 0, sizeof(execbuf));
+ if (ahnd) {
+ addr = buf->addr.offset;
+ if (INVALID_ADDR(addr)) {
+ addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
+ buf->handle, buf->size, 0);
+ buf->addr.offset = addr;
+ }
+ }
+
b = tmp;
*b++ = XY_COLOR_BLT_CMD_NOLEN |
((gen >= 8) ? 5 : 4) |
@@ -691,9 +728,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
reloc[0].target_handle = buf->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
- *b++ = 0;
+ *b++ = addr;
if (gen >= 8)
- *b++ = 0;
+ *b++ = addr >> 32;
*b++ = val;
*b++ = MI_BATCH_BUFFER_END;
if ((b - tmp) & 1)
@@ -703,8 +740,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
gem_exec[1].handle = gem_create(fd, 4096);
- gem_exec[1].relocation_count = 1;
- gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (!ahnd) {
+ gem_exec[1].relocation_count = 1;
+ gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
+ gem_exec[1].handle,
+ 4096, 0));
+ gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ gem_exec[0].offset = CANONICAL(buf->addr.offset);
+ gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ }
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 2;
@@ -716,6 +764,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_execbuf(fd, &execbuf);
gem_close(fd, gem_exec[1].handle);
+ put_offset(ahnd, gem_exec[1].handle);
}
static void
@@ -766,6 +815,18 @@ static bool set_max_map_count(int num_buffers)
return max > num_buffers;
}
+static uint64_t alloc_open(void)
+{
+ return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
+}
+
+static struct intel_bb *bb_create(int i915, uint32_t size)
+{
+ return ahnd ? intel_bb_create_no_relocs(i915, size) :
+ intel_bb_create_with_relocs(i915, size);
+}
+
static void buffers_init(struct buffers *b,
const char *name,
const struct create *create,
@@ -796,7 +857,7 @@ static void buffers_init(struct buffers *b,
igt_assert(b->src);
b->dst = b->src + num_buffers;
- b->ibb = intel_bb_create(_fd, 4096);
+ b->ibb = bb_create(_fd, 4096);
}
static void buffers_destroy(struct buffers *b)
@@ -829,6 +890,27 @@ static void buffers_destroy(struct buffers *b)
}
}
+static void bb_destroy(struct buffers *b)
+{
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+}
+
+static void __bufs_destroy(struct buffers *b)
+{
+ buffers_destroy(b);
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+ if (b->bops) {
+ buf_ops_destroy(b->bops);
+ b->bops = NULL;
+ }
+}
+
static void buffers_create(struct buffers *b)
{
int count = b->num_buffers;
@@ -838,32 +920,57 @@ static void buffers_create(struct buffers *b)
igt_assert(b->count == 0);
b->count = count;
+ ahnd = alloc_open();
for (int i = 0; i < count; i++) {
b->src[i] = b->mode->create_bo(b);
b->dst[i] = b->mode->create_bo(b);
}
b->spare = b->mode->create_bo(b);
b->snoop = snoop_create_bo(b);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_reset(struct buffers *b)
{
b->bops = buf_ops_create(fd);
- b->ibb = intel_bb_create(fd, 4096);
+ b->ibb = bb_create(fd, 4096);
+}
+
+static void __buffers_create(struct buffers *b)
+{
+ b->bops = buf_ops_create(fd);
+ igt_assert(b->bops);
+ igt_assert(b->num_buffers > 0);
+ igt_assert(b->mode);
+ igt_assert(b->mode->create_bo);
+
+ b->count = 0;
+ for (int i = 0; i < b->num_buffers; i++) {
+ b->src[i] = b->mode->create_bo(b);
+ b->dst[i] = b->mode->create_bo(b);
+ }
+ b->count = b->num_buffers;
+ b->spare = b->mode->create_bo(b);
+ b->snoop = snoop_create_bo(b);
+ ahnd = alloc_open();
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_fini(struct buffers *b)
{
if (b->bops == NULL)
return;
-
buffers_destroy(b);
free(b->tmp);
free(b->src);
-
- intel_bb_destroy(b->ibb);
- buf_ops_destroy(b->bops);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+ if (b->bops)
+ buf_ops_destroy(b->bops);
memset(b, 0, sizeof(*b));
}
@@ -1306,6 +1413,8 @@ static void run_single(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
@@ -1316,6 +1425,8 @@ static void run_interruptible(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
igt_while_interruptible(true)
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1332,10 +1443,18 @@ static void run_child(struct buffers *buffers,
* leading to the child closing an object without the parent knowing.
*/
pass = 0;
- igt_fork(child, 1)
+ __bufs_destroy(buffers);
+
+ igt_fork(child, 1) {
+ /* recreate process local variables */
+ intel_allocator_init();
+ __buffers_create(buffers);
do_test_func(buffers, do_copy_func, do_hang_func);
+ }
igt_waitchildren();
+
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ buffers_reset(buffers);
}
static void __run_forked(struct buffers *buffers,
@@ -1346,24 +1465,20 @@ static void __run_forked(struct buffers *buffers,
{
/* purge the caches before cloing the process */
- buffers_destroy(buffers);
- intel_bb_destroy(buffers->ibb);
- buf_ops_destroy(buffers->bops);
+ __bufs_destroy(buffers);
igt_fork(child, num_children) {
int num_buffers;
/* recreate process local variables */
fd = gem_reopen_driver(fd);
-
+ intel_allocator_init(); /* detach from thread */
num_buffers = buffers->num_buffers / num_children;
num_buffers += MIN_BUFFERS;
if (num_buffers < buffers->num_buffers)
buffers->num_buffers = num_buffers;
- buffers_reset(buffers);
- buffers_create(buffers);
-
+ __buffers_create(buffers);
igt_while_interruptible(interrupt) {
for (pass = 0; pass < loops; pass++)
do_test_func(buffers,
@@ -1773,6 +1888,7 @@ igt_main
{ "16MiB", 2048, 2048 },
{ NULL}
};
+
uint64_t pin_sz = 0;
void *pinned = NULL;
char name[80];
@@ -1792,6 +1908,12 @@ igt_main
rendercopy = igt_get_render_copyfunc(devid);
vgem_drv = __drm_open_driver(DRIVER_VGEM);
+
+ ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0);
+ put_ahnd(ahnd);
+ if (ahnd)
+ intel_bb_track(true);
}
for (const struct create *c = create; c->name; c++) {
@@ -1864,7 +1986,6 @@ igt_main
igt_fixture
igt_stop_shrink_helper();
}
-
/* Use the entire mappable aperture, force swapping */
snprintf(name, sizeof(name), "%s%s-%s",
c->name, s->name, "swap");
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-24 14:19 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
@ 2022-03-28 6:41 ` Zbigniew Kempczyński
0 siblings, 0 replies; 16+ messages in thread
From: Zbigniew Kempczyński @ 2022-03-28 6:41 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
On Thu, Mar 24, 2022 at 03:19:17PM +0100, Kamil Konieczny wrote:
> Add noreloc mode for GPU gens without relocations. Also
> while at this, add some caching for required properties.
> Change also snoop function so it will work on DG1.
>
> Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
> and 256KiB with modified drm-tip to allow softpinning.
>
> v5: rebase, fix caching in bit17_require, changes according
> to Zbigniew review: simplify cache of !gem_has_llc, drop
> multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
> correct offset and flags
> v4: corrected alloc_open and first ahnd setting
>
> Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> tests/i915/gem_concurrent_all.c | 165 +++++++++++++++++++++++++++-----
> 1 file changed, 142 insertions(+), 23 deletions(-)
>
> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> index d0f9b62e..d17c19fc 100644
> --- a/tests/i915/gem_concurrent_all.c
> +++ b/tests/i915/gem_concurrent_all.c
> @@ -60,6 +60,7 @@ int fd, devid, gen;
> int vgem_drv = -1;
> int all;
> int pass;
> +uint64_t ahnd;
>
> struct create {
> const char *name;
> @@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
>
> static void create_snoop_require(const struct create *create, unsigned count)
> {
> + static bool check_llc = true;
> + static bool has_snoop;
> +
> create_cpu_require(create, count);
> - igt_require(!gem_has_llc(fd));
> + if (check_llc) {
> + has_snoop = !gem_has_llc(fd);
> + check_llc = false;
> + }
> +
> + igt_require(has_snoop);
> }
>
> static struct intel_buf *
> @@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
> struct intel_buf *buf;
>
> buf = unmapped_create_bo(b);
> - gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
> + __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
>
> return buf;
> }
> @@ -578,16 +587,32 @@ static void bit17_require(void)
> uint32_t swizzle_mode;
> uint32_t phys_swizzle_mode;
> } arg;
> + static bool has_tiling2;
> #define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
>
> if (arg.handle == 0) {
> + bool has_tiling;
> + int err;
> +
> + has_tiling2 = false;
> arg.handle = gem_create(fd, 4096);
> - gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
> + if (!err) {
> + has_tiling = true;
> + igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> + if (!errno)
> + has_tiling2 = true;
> +
> + errno = 0;
> + } else {
> + has_tiling = false;
> + }
>
> - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
> gem_close(fd, arg.handle);
> + igt_require(has_tiling);
> }
> igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
> + igt_require(has_tiling2);
I think you can simplify this to:
if (arg.handle == 0) {
int err;
arg.handle = gem_create(fd, 4096);
err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
igt_require(!err);
igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
gem_close(fd, arg.handle);
}
igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
If first set_tiling() is failing we can immediate skip. But if we can
set-tiling on bo then after get-tiling2 swizzle mode must be same.
Maybe someone will complain on igt_require(!err), but imo looking at
set-tiling it is clear - we need to support this, if not test can
be skipped.
> }
>
> static void wc_require(void)
> @@ -670,11 +695,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> struct drm_i915_gem_exec_object2 gem_exec[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> uint32_t tmp[10], *b;
> + uint64_t addr = 0;
>
> memset(reloc, 0, sizeof(reloc));
> memset(gem_exec, 0, sizeof(gem_exec));
> memset(&execbuf, 0, sizeof(execbuf));
>
> + if (ahnd) {
> + addr = buf->addr.offset;
> + if (INVALID_ADDR(addr)) {
> + addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
> + buf->handle, buf->size, 0);
> + buf->addr.offset = addr;
> + }
> + }
> +
> b = tmp;
> *b++ = XY_COLOR_BLT_CMD_NOLEN |
> ((gen >= 8) ? 5 : 4) |
> @@ -691,9 +726,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> reloc[0].target_handle = buf->handle;
> reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
> reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
> - *b++ = 0;
> + *b++ = addr;
> if (gen >= 8)
> - *b++ = 0;
> + *b++ = addr >> 32;
> *b++ = val;
> *b++ = MI_BATCH_BUFFER_END;
> if ((b - tmp) & 1)
> @@ -703,8 +738,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
>
> gem_exec[1].handle = gem_create(fd, 4096);
> - gem_exec[1].relocation_count = 1;
> - gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + if (!ahnd) {
> + gem_exec[1].relocation_count = 1;
> + gem_exec[1].relocs_ptr = to_user_pointer(reloc);
> + } else {
> + gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
> + gem_exec[1].handle,
> + 4096, 0));
> + gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +
> + gem_exec[0].offset = CANONICAL(buf->addr.offset);
> + gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> + }
>
> execbuf.buffers_ptr = to_user_pointer(gem_exec);
> execbuf.buffer_count = 2;
> @@ -716,6 +762,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
> gem_execbuf(fd, &execbuf);
>
> gem_close(fd, gem_exec[1].handle);
> + put_offset(ahnd, gem_exec[1].handle);
> }
>
> static void
> @@ -766,6 +813,18 @@ static bool set_max_map_count(int num_buffers)
> return max > num_buffers;
> }
>
> +static uint64_t alloc_open(void)
> +{
> + return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
> +}
> +
> +static struct intel_bb *bb_create(int i915, uint32_t size)
> +{
> + return ahnd ? intel_bb_create_no_relocs(i915, size) :
> + intel_bb_create_with_relocs(i915, size);
> +}
> +
> static void buffers_init(struct buffers *b,
> const char *name,
> const struct create *create,
> @@ -796,7 +855,7 @@ static void buffers_init(struct buffers *b,
> igt_assert(b->src);
> b->dst = b->src + num_buffers;
>
> - b->ibb = intel_bb_create(_fd, 4096);
> + b->ibb = bb_create(_fd, 4096);
> }
>
> static void buffers_destroy(struct buffers *b)
> @@ -829,6 +888,27 @@ static void buffers_destroy(struct buffers *b)
> }
> }
>
> +static void bb_destroy(struct buffers *b)
> +{
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> +}
> +
> +static void __bufs_destroy(struct buffers *b)
> +{
> + buffers_destroy(b);
> + if (b->ibb) {
> + intel_bb_destroy(b->ibb);
> + b->ibb = NULL;
> + }
> + if (b->bops) {
> + buf_ops_destroy(b->bops);
> + b->bops = NULL;
> + }
> +}
> +
> static void buffers_create(struct buffers *b)
> {
> int count = b->num_buffers;
> @@ -838,32 +918,57 @@ static void buffers_create(struct buffers *b)
> igt_assert(b->count == 0);
> b->count = count;
>
> + ahnd = alloc_open();
> for (int i = 0; i < count; i++) {
> b->src[i] = b->mode->create_bo(b);
> b->dst[i] = b->mode->create_bo(b);
> }
> b->spare = b->mode->create_bo(b);
> b->snoop = snoop_create_bo(b);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> +
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_reset(struct buffers *b)
> {
> b->bops = buf_ops_create(fd);
> - b->ibb = intel_bb_create(fd, 4096);
> + b->ibb = bb_create(fd, 4096);
> +}
> +
> +static void __buffers_create(struct buffers *b)
> +{
> + b->bops = buf_ops_create(fd);
> + igt_assert(b->bops);
> + igt_assert(b->num_buffers > 0);
> + igt_assert(b->mode);
> + igt_assert(b->mode->create_bo);
> +
> + b->count = 0;
> + for (int i = 0; i < b->num_buffers; i++) {
> + b->src[i] = b->mode->create_bo(b);
> + b->dst[i] = b->mode->create_bo(b);
> + }
> + b->count = b->num_buffers;
> + b->spare = b->mode->create_bo(b);
> + b->snoop = snoop_create_bo(b);
> + ahnd = alloc_open();
> + b->ibb = bb_create(fd, 4096);
> }
>
> static void buffers_fini(struct buffers *b)
> {
> if (b->bops == NULL)
> return;
> -
> buffers_destroy(b);
>
> free(b->tmp);
> free(b->src);
> -
> - intel_bb_destroy(b->ibb);
> - buf_ops_destroy(b->bops);
> + if (b->ibb)
> + intel_bb_destroy(b->ibb);
> + if (b->bops)
> + buf_ops_destroy(b->bops);
>
> memset(b, 0, sizeof(*b));
> }
> @@ -1306,6 +1411,8 @@ static void run_single(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> }
> @@ -1316,6 +1423,8 @@ static void run_interruptible(struct buffers *buffers,
> do_hang do_hang_func)
> {
> pass = 0;
> + bb_destroy(buffers);
> + buffers->ibb = bb_create(fd, 4096);
> igt_while_interruptible(true)
> do_test_func(buffers, do_copy_func, do_hang_func);
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> @@ -1332,10 +1441,18 @@ static void run_child(struct buffers *buffers,
> * leading to the child closing an object without the parent knowing.
> */
> pass = 0;
> - igt_fork(child, 1)
> + __bufs_destroy(buffers);
> +
> + igt_fork(child, 1) {
> + /* recreate process local variables */
> + intel_allocator_init();
> + __buffers_create(buffers);
> do_test_func(buffers, do_copy_func, do_hang_func);
> + }
> igt_waitchildren();
> +
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> + buffers_reset(buffers);
> }
>
> static void __run_forked(struct buffers *buffers,
> @@ -1346,24 +1463,20 @@ static void __run_forked(struct buffers *buffers,
>
> {
> /* purge the caches before cloing the process */
> - buffers_destroy(buffers);
> - intel_bb_destroy(buffers->ibb);
> - buf_ops_destroy(buffers->bops);
> + __bufs_destroy(buffers);
>
> igt_fork(child, num_children) {
> int num_buffers;
>
> /* recreate process local variables */
> fd = gem_reopen_driver(fd);
> -
> + intel_allocator_init(); //detach from thread
We agreed to use C-style comments, so change to /* */ or remove.
> num_buffers = buffers->num_buffers / num_children;
> num_buffers += MIN_BUFFERS;
> if (num_buffers < buffers->num_buffers)
> buffers->num_buffers = num_buffers;
>
> - buffers_reset(buffers);
> - buffers_create(buffers);
> -
> + __buffers_create(buffers);
> igt_while_interruptible(interrupt) {
> for (pass = 0; pass < loops; pass++)
> do_test_func(buffers,
> @@ -1773,6 +1886,7 @@ igt_main
> { "16MiB", 2048, 2048 },
> { NULL}
> };
> +
> uint64_t pin_sz = 0;
> void *pinned = NULL;
> char name[80];
> @@ -1792,6 +1906,12 @@ igt_main
> rendercopy = igt_get_render_copyfunc(devid);
>
> vgem_drv = __drm_open_driver(DRIVER_VGEM);
> +
> + ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_HIGH_TO_LOW, 0);
> + put_ahnd(ahnd);
> + if (ahnd)
> + intel_bb_track(true);
> }
>
> for (const struct create *c = create; c->name; c++) {
> @@ -1864,7 +1984,6 @@ igt_main
> igt_fixture
> igt_stop_shrink_helper();
> }
> -
> /* Use the entire mappable aperture, force swapping */
> snprintf(name, sizeof(name), "%s%s-%s",
> c->name, s->name, "swap");
> --
> 2.32.0
>
Other things looks fine for me. Please change above and I'm going
to merge this.
--
Zbigniew
^ permalink raw reply [flat|nested] 16+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability
2022-03-24 14:19 [igt-dev] [PATCH i-g-t 0/2] " Kamil Konieczny
@ 2022-03-24 14:19 ` Kamil Konieczny
2022-03-28 6:41 ` Zbigniew Kempczyński
0 siblings, 1 reply; 16+ messages in thread
From: Kamil Konieczny @ 2022-03-24 14:19 UTC (permalink / raw)
To: igt-dev
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
and 256KiB with modified drm-tip to allow softpinning.
v5: rebase, fix caching in bit17_require, changes according
to Zbigniew review: simplify cache of !gem_has_llc, drop
multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
correct offset and flags
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/gem_concurrent_all.c | 165 +++++++++++++++++++++++++++-----
1 file changed, 142 insertions(+), 23 deletions(-)
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index d0f9b62e..d17c19fc 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -60,6 +60,7 @@ int fd, devid, gen;
int vgem_drv = -1;
int all;
int pass;
+uint64_t ahnd;
struct create {
const char *name;
@@ -239,8 +240,16 @@ unmapped_create_bo(const struct buffers *b)
static void create_snoop_require(const struct create *create, unsigned count)
{
+ static bool check_llc = true;
+ static bool has_snoop;
+
create_cpu_require(create, count);
- igt_require(!gem_has_llc(fd));
+ if (check_llc) {
+ has_snoop = !gem_has_llc(fd);
+ check_llc = false;
+ }
+
+ igt_require(has_snoop);
}
static struct intel_buf *
@@ -249,7 +258,7 @@ snoop_create_bo(const struct buffers *b)
struct intel_buf *buf;
buf = unmapped_create_bo(b);
- gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
+ __gem_set_caching(fd, buf->handle, I915_CACHING_CACHED);
return buf;
}
@@ -578,16 +587,32 @@ static void bit17_require(void)
uint32_t swizzle_mode;
uint32_t phys_swizzle_mode;
} arg;
+ static bool has_tiling2;
#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
if (arg.handle == 0) {
+ bool has_tiling;
+ int err;
+
+ has_tiling2 = false;
arg.handle = gem_create(fd, 4096);
- gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ err = __gem_set_tiling(fd, arg.handle, I915_TILING_X, 512);
+ if (!err) {
+ has_tiling = true;
+ igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
+ if (!errno)
+ has_tiling2 = true;
+
+ errno = 0;
+ } else {
+ has_tiling = false;
+ }
- do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg);
gem_close(fd, arg.handle);
+ igt_require(has_tiling);
}
igt_require(arg.phys_swizzle_mode == arg.swizzle_mode);
+ igt_require(has_tiling2);
}
static void wc_require(void)
@@ -670,11 +695,21 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
struct drm_i915_gem_exec_object2 gem_exec[2];
struct drm_i915_gem_execbuffer2 execbuf;
uint32_t tmp[10], *b;
+ uint64_t addr = 0;
memset(reloc, 0, sizeof(reloc));
memset(gem_exec, 0, sizeof(gem_exec));
memset(&execbuf, 0, sizeof(execbuf));
+ if (ahnd) {
+ addr = buf->addr.offset;
+ if (INVALID_ADDR(addr)) {
+ addr = intel_allocator_alloc(buffers->ibb->allocator_handle,
+ buf->handle, buf->size, 0);
+ buf->addr.offset = addr;
+ }
+ }
+
b = tmp;
*b++ = XY_COLOR_BLT_CMD_NOLEN |
((gen >= 8) ? 5 : 4) |
@@ -691,9 +726,9 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
reloc[0].target_handle = buf->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
- *b++ = 0;
+ *b++ = addr;
if (gen >= 8)
- *b++ = 0;
+ *b++ = addr >> 32;
*b++ = val;
*b++ = MI_BATCH_BUFFER_END;
if ((b - tmp) & 1)
@@ -703,8 +738,19 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_exec[0].flags = EXEC_OBJECT_NEEDS_FENCE;
gem_exec[1].handle = gem_create(fd, 4096);
- gem_exec[1].relocation_count = 1;
- gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ if (!ahnd) {
+ gem_exec[1].relocation_count = 1;
+ gem_exec[1].relocs_ptr = to_user_pointer(reloc);
+ } else {
+ gem_exec[1].offset = CANONICAL(intel_allocator_alloc(ahnd,
+ gem_exec[1].handle,
+ 4096, 0));
+ gem_exec[1].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ gem_exec[0].offset = CANONICAL(buf->addr.offset);
+ gem_exec[0].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ }
execbuf.buffers_ptr = to_user_pointer(gem_exec);
execbuf.buffer_count = 2;
@@ -716,6 +762,7 @@ gpu_set_bo(struct buffers *buffers, struct intel_buf *buf, uint32_t val)
gem_execbuf(fd, &execbuf);
gem_close(fd, gem_exec[1].handle);
+ put_offset(ahnd, gem_exec[1].handle);
}
static void
@@ -766,6 +813,18 @@ static bool set_max_map_count(int num_buffers)
return max > num_buffers;
}
+static uint64_t alloc_open(void)
+{
+ return ahnd ? intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0) : 0;
+}
+
+static struct intel_bb *bb_create(int i915, uint32_t size)
+{
+ return ahnd ? intel_bb_create_no_relocs(i915, size) :
+ intel_bb_create_with_relocs(i915, size);
+}
+
static void buffers_init(struct buffers *b,
const char *name,
const struct create *create,
@@ -796,7 +855,7 @@ static void buffers_init(struct buffers *b,
igt_assert(b->src);
b->dst = b->src + num_buffers;
- b->ibb = intel_bb_create(_fd, 4096);
+ b->ibb = bb_create(_fd, 4096);
}
static void buffers_destroy(struct buffers *b)
@@ -829,6 +888,27 @@ static void buffers_destroy(struct buffers *b)
}
}
+static void bb_destroy(struct buffers *b)
+{
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+}
+
+static void __bufs_destroy(struct buffers *b)
+{
+ buffers_destroy(b);
+ if (b->ibb) {
+ intel_bb_destroy(b->ibb);
+ b->ibb = NULL;
+ }
+ if (b->bops) {
+ buf_ops_destroy(b->bops);
+ b->bops = NULL;
+ }
+}
+
static void buffers_create(struct buffers *b)
{
int count = b->num_buffers;
@@ -838,32 +918,57 @@ static void buffers_create(struct buffers *b)
igt_assert(b->count == 0);
b->count = count;
+ ahnd = alloc_open();
for (int i = 0; i < count; i++) {
b->src[i] = b->mode->create_bo(b);
b->dst[i] = b->mode->create_bo(b);
}
b->spare = b->mode->create_bo(b);
b->snoop = snoop_create_bo(b);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_reset(struct buffers *b)
{
b->bops = buf_ops_create(fd);
- b->ibb = intel_bb_create(fd, 4096);
+ b->ibb = bb_create(fd, 4096);
+}
+
+static void __buffers_create(struct buffers *b)
+{
+ b->bops = buf_ops_create(fd);
+ igt_assert(b->bops);
+ igt_assert(b->num_buffers > 0);
+ igt_assert(b->mode);
+ igt_assert(b->mode->create_bo);
+
+ b->count = 0;
+ for (int i = 0; i < b->num_buffers; i++) {
+ b->src[i] = b->mode->create_bo(b);
+ b->dst[i] = b->mode->create_bo(b);
+ }
+ b->count = b->num_buffers;
+ b->spare = b->mode->create_bo(b);
+ b->snoop = snoop_create_bo(b);
+ ahnd = alloc_open();
+ b->ibb = bb_create(fd, 4096);
}
static void buffers_fini(struct buffers *b)
{
if (b->bops == NULL)
return;
-
buffers_destroy(b);
free(b->tmp);
free(b->src);
-
- intel_bb_destroy(b->ibb);
- buf_ops_destroy(b->bops);
+ if (b->ibb)
+ intel_bb_destroy(b->ibb);
+ if (b->bops)
+ buf_ops_destroy(b->bops);
memset(b, 0, sizeof(*b));
}
@@ -1306,6 +1411,8 @@ static void run_single(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
@@ -1316,6 +1423,8 @@ static void run_interruptible(struct buffers *buffers,
do_hang do_hang_func)
{
pass = 0;
+ bb_destroy(buffers);
+ buffers->ibb = bb_create(fd, 4096);
igt_while_interruptible(true)
do_test_func(buffers, do_copy_func, do_hang_func);
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
@@ -1332,10 +1441,18 @@ static void run_child(struct buffers *buffers,
* leading to the child closing an object without the parent knowing.
*/
pass = 0;
- igt_fork(child, 1)
+ __bufs_destroy(buffers);
+
+ igt_fork(child, 1) {
+ /* recreate process local variables */
+ intel_allocator_init();
+ __buffers_create(buffers);
do_test_func(buffers, do_copy_func, do_hang_func);
+ }
igt_waitchildren();
+
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+ buffers_reset(buffers);
}
static void __run_forked(struct buffers *buffers,
@@ -1346,24 +1463,20 @@ static void __run_forked(struct buffers *buffers,
{
/* purge the caches before cloing the process */
- buffers_destroy(buffers);
- intel_bb_destroy(buffers->ibb);
- buf_ops_destroy(buffers->bops);
+ __bufs_destroy(buffers);
igt_fork(child, num_children) {
int num_buffers;
/* recreate process local variables */
fd = gem_reopen_driver(fd);
-
+ intel_allocator_init(); //detach from thread
num_buffers = buffers->num_buffers / num_children;
num_buffers += MIN_BUFFERS;
if (num_buffers < buffers->num_buffers)
buffers->num_buffers = num_buffers;
- buffers_reset(buffers);
- buffers_create(buffers);
-
+ __buffers_create(buffers);
igt_while_interruptible(interrupt) {
for (pass = 0; pass < loops; pass++)
do_test_func(buffers,
@@ -1773,6 +1886,7 @@ igt_main
{ "16MiB", 2048, 2048 },
{ NULL}
};
+
uint64_t pin_sz = 0;
void *pinned = NULL;
char name[80];
@@ -1792,6 +1906,12 @@ igt_main
rendercopy = igt_get_render_copyfunc(devid);
vgem_drv = __drm_open_driver(DRIVER_VGEM);
+
+ ahnd = intel_allocator_open_full(fd, 0, 0, 0, INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_HIGH_TO_LOW, 0);
+ put_ahnd(ahnd);
+ if (ahnd)
+ intel_bb_track(true);
}
for (const struct create *c = create; c->name; c++) {
@@ -1864,7 +1984,6 @@ igt_main
igt_fixture
igt_stop_shrink_helper();
}
-
/* Use the entire mappable aperture, force swapping */
snprintf(name, sizeof(name), "%s%s-%s",
c->name, s->name, "swap");
--
2.32.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-03-29 14:17 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-24 13:04 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 1/2] lib/intel_batchbuffer: add create without relocs Kamil Konieczny
2022-03-22 19:09 ` Zbigniew Kempczyński
2022-02-24 13:04 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
2022-03-22 19:34 ` Zbigniew Kempczyński
2022-02-24 14:15 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_concurrent_all: Add no-reloc Patchwork
2022-02-25 3:42 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2022-03-24 14:19 [igt-dev] [PATCH i-g-t 0/2] " Kamil Konieczny
2022-03-24 14:19 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
2022-03-28 6:41 ` Zbigniew Kempczyński
2022-03-28 8:31 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-03-28 8:31 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
2022-03-28 12:33 ` Zbigniew Kempczyński
2022-03-28 16:55 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-03-28 16:55 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
2022-03-29 8:10 ` Zbigniew Kempczyński
2022-03-29 12:56 ` Kamil Konieczny
2022-03-29 13:49 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-03-29 13:49 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
2022-03-29 14:17 [igt-dev] [PATCH i-g-t 0/2] i915/gem_concurrent_all: Add no-reloc Kamil Konieczny
2022-03-29 14:17 ` [igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_concurrent_all: Add no-reloc capability Kamil Konieczny
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