From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>, lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com Subject: [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Date: Mon, 28 Feb 2022 22:48:04 +0800 [thread overview] Message-ID: <20220228144810.7284-9-liweiwei@iscas.ac.cn> (raw) In-Reply-To: <20220228144810.7284-1-liweiwei@iscas.ac.cn> - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/insn32.decode | 5 ++++ target/riscv/insn_trans/trans_rvk.c.inc | 37 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0b800b4093..db28ecdd2b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -857,3 +857,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r # *** RV64 Zkne/zknd Standard Extension *** aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes +# *** RV32 Zknh Standard Extension *** +sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 +sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 +sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 +sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index e315462e5a..02a3261675 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -29,6 +29,12 @@ } \ } while (0) +#define REQUIRE_ZKNH(ctx) do { \ + if (!ctx->cfg_ptr->ext_zknh) { \ + return false; \ + } \ +} while (0) + static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a, void (*func)(TCGv, TCGv, TCGv, TCGv)) { @@ -112,3 +118,34 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a) REQUIRE_ZKND(ctx); return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im); } + +#define GEN_SHA256(NAME, OP, NUM1, NUM2, NUM3) \ +static void gen_##NAME(TCGv dest, TCGv src1) \ +{ \ + TCGv_i32 t0 = tcg_temp_new_i32(); \ + TCGv_i32 t1 = tcg_temp_new_i32(); \ + TCGv_i32 t2 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, src1); \ + tcg_gen_rotri_i32(t1, t0, NUM1); \ + tcg_gen_rotri_i32(t2, t0, NUM2); \ + tcg_gen_xor_i32(t1, t1, t2); \ + tcg_gen_##OP##_i32(t2, t0, NUM3); \ + tcg_gen_xor_i32(t1, t1, t2); \ + tcg_gen_ext_i32_tl(dest, t1); \ + \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_i32(t1); \ + tcg_temp_free_i32(t2); \ +} \ +\ +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ +{ \ + REQUIRE_ZKNH(ctx); \ + return gen_unary(ctx, a, EXT_NONE, gen_##NAME); \ +} + +GEN_SHA256(sha256sig0, shri, 7, 18, 3) +GEN_SHA256(sha256sig1, shri, 17, 19, 10) +GEN_SHA256(sha256sum0, rotri, 2, 13, 22) +GEN_SHA256(sha256sum1, rotri, 6, 11, 25) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, lustrew@foxmail.com, luruibo2000@163.com, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Date: Mon, 28 Feb 2022 22:48:04 +0800 [thread overview] Message-ID: <20220228144810.7284-9-liweiwei@iscas.ac.cn> (raw) In-Reply-To: <20220228144810.7284-1-liweiwei@iscas.ac.cn> - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/insn32.decode | 5 ++++ target/riscv/insn_trans/trans_rvk.c.inc | 37 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0b800b4093..db28ecdd2b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -857,3 +857,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r # *** RV64 Zkne/zknd Standard Extension *** aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes +# *** RV32 Zknh Standard Extension *** +sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 +sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 +sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 +sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index e315462e5a..02a3261675 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -29,6 +29,12 @@ } \ } while (0) +#define REQUIRE_ZKNH(ctx) do { \ + if (!ctx->cfg_ptr->ext_zknh) { \ + return false; \ + } \ +} while (0) + static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a, void (*func)(TCGv, TCGv, TCGv, TCGv)) { @@ -112,3 +118,34 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a) REQUIRE_ZKND(ctx); return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im); } + +#define GEN_SHA256(NAME, OP, NUM1, NUM2, NUM3) \ +static void gen_##NAME(TCGv dest, TCGv src1) \ +{ \ + TCGv_i32 t0 = tcg_temp_new_i32(); \ + TCGv_i32 t1 = tcg_temp_new_i32(); \ + TCGv_i32 t2 = tcg_temp_new_i32(); \ + \ + tcg_gen_trunc_tl_i32(t0, src1); \ + tcg_gen_rotri_i32(t1, t0, NUM1); \ + tcg_gen_rotri_i32(t2, t0, NUM2); \ + tcg_gen_xor_i32(t1, t1, t2); \ + tcg_gen_##OP##_i32(t2, t0, NUM3); \ + tcg_gen_xor_i32(t1, t1, t2); \ + tcg_gen_ext_i32_tl(dest, t1); \ + \ + tcg_temp_free_i32(t0); \ + tcg_temp_free_i32(t1); \ + tcg_temp_free_i32(t2); \ +} \ +\ +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ +{ \ + REQUIRE_ZKNH(ctx); \ + return gen_unary(ctx, a, EXT_NONE, gen_##NAME); \ +} + +GEN_SHA256(sha256sig0, shri, 7, 18, 3) +GEN_SHA256(sha256sig1, shri, 17, 19, 10) +GEN_SHA256(sha256sum0, rotri, 2, 13, 22) +GEN_SHA256(sha256sum1, rotri, 6, 11, 25) -- 2.17.1
next prev parent reply other threads:[~2022-02-28 14:51 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-28 14:47 [PATCH v7 00/14] support subsets of scalar crypto extension Weiwei Li 2022-02-28 14:47 ` Weiwei Li 2022-02-28 14:47 ` [PATCH v7 01/14] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li 2022-02-28 14:47 ` Weiwei Li 2022-02-28 14:47 ` [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension Weiwei Li 2022-02-28 14:47 ` Weiwei Li 2022-02-28 18:54 ` Richard Henderson 2022-02-28 18:54 ` Richard Henderson 2022-02-28 14:47 ` [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension Weiwei Li 2022-02-28 14:47 ` Weiwei Li 2022-02-28 18:55 ` Richard Henderson 2022-02-28 18:55 ` Richard Henderson 2022-02-28 14:48 ` [PATCH v7 04/14] target/riscv: rvk: add support for zbkx extension Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 14:48 ` [PATCH v7 05/14] crypto: move sm4_sbox from target/arm Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 14:48 ` [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32 Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 18:57 ` Richard Henderson 2022-02-28 18:57 ` Richard Henderson 2022-02-28 14:48 ` [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64 Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 19:01 ` Richard Henderson 2022-02-28 19:01 ` Richard Henderson 2022-02-28 14:48 ` Weiwei Li [this message] 2022-02-28 14:48 ` [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Weiwei Li 2022-02-28 19:03 ` Richard Henderson 2022-02-28 19:03 ` Richard Henderson 2022-02-28 14:48 ` [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 " Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 19:38 ` Richard Henderson 2022-02-28 19:38 ` Richard Henderson 2022-03-01 1:28 ` Weiwei Li 2022-03-01 1:28 ` Weiwei Li 2022-02-28 14:48 ` [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 " Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 19:40 ` Richard Henderson 2022-02-28 19:40 ` Richard Henderson 2022-02-28 14:48 ` [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 19:44 ` Richard Henderson 2022-02-28 19:44 ` Richard Henderson 2022-02-28 14:48 ` [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 20:11 ` Richard Henderson 2022-02-28 20:11 ` Richard Henderson 2022-03-01 1:44 ` Weiwei Li 2022-03-01 1:44 ` Weiwei Li 2022-03-01 2:27 ` Weiwei Li 2022-03-01 2:27 ` Weiwei Li 2022-03-01 15:59 ` Richard Henderson 2022-03-01 15:59 ` Richard Henderson 2022-03-02 0:57 ` Weiwei Li 2022-03-02 0:57 ` Weiwei Li 2022-02-28 14:48 ` [PATCH v7 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li 2022-02-28 14:48 ` Weiwei Li 2022-02-28 14:48 ` [PATCH v7 14/14] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li 2022-02-28 14:48 ` Weiwei Li
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