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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Richard Henderson <richard.henderson@linaro.org>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	luruibo2000@163.com, lustrew@foxmail.com
Subject: Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
Date: Wed, 2 Mar 2022 08:57:05 +0800	[thread overview]
Message-ID: <13cb8412-c237-bd1b-29c3-a1a35397c8ab@iscas.ac.cn> (raw)
In-Reply-To: <8b6ff05f-7246-940e-be90-44ede1a6a3ba@linaro.org>


在 2022/3/1 下午11:59, Richard Henderson 写道:
> On 2/28/22 16:27, Weiwei Li wrote:
>>
>> 在 2022/3/1 上午9:44, Weiwei Li 写道:
>>>
>>> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>>>> On 2/28/22 04:48, Weiwei Li wrote:
>>>>> +/* Crypto Extension */
>>>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>>>> +                              target_ulong *ret_value,
>>>>> +                              target_ulong new_value, 
>>>>> target_ulong write_mask)
>>>>> +{
>>>>> +    if (!write_mask) {
>>>>> +        return RISCV_EXCP_ILLEGAL_INST;
>>>>> +    }
>>>>
>>>> This is incorrect.  The error should only be with a write-mask of 
>>>> the actual x0 register, not another register which happens to 
>>>> contain 0.  There is in fact no way to diagnose exactly what you 
>>>> want here, which IIRC has an existing fixme comment somewhere.
>>> Yeah. write_mask is also used in riscv_csrrw_check to check whether 
>>> the read-only csr is written. We cannot distinguish x0 and reg which 
>>> contains 0  here without changing total progress of csr read/write.
>>>>
>> I seems misunderstand the code for csr read/write:  write_mask will 
>> be set zero only for read-only operation (CSRRS/CSRRC with rs1=x0 or 
>> CSRRSI/CSRRCI with uimm=0) via do_csrr --> helper_csrr -> riscv_csrrw 
>> call-chain.
>>
>> The write_mask for do_csrw and do_csrrw will not be zero.
>>
>> As said in the spec :
>>
>> "TheseedCSR must be accessed with a read-write instruction. A 
>> read-only instruction such asCSRRS/CSRRC
>> withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction 
>> exception. "
>>
>> So it's suitable to check write_mask here.
>
> Consider CSRRS with rs1=x31.  In that case mask will be the value in 
> x31.  Even if the value is 0, this is still considered a read-write 
> instruction.
Yeah. I lost this kind of case . So this is a bug. Maybe we can add a 
new parameter like  'write' to helper_csrrw to indicate that write 
operation should be done.
>
>
> r~



WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Richard Henderson <richard.henderson@linaro.org>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	lustrew@foxmail.com, luruibo2000@163.com
Subject: Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
Date: Wed, 2 Mar 2022 08:57:05 +0800	[thread overview]
Message-ID: <13cb8412-c237-bd1b-29c3-a1a35397c8ab@iscas.ac.cn> (raw)
In-Reply-To: <8b6ff05f-7246-940e-be90-44ede1a6a3ba@linaro.org>


在 2022/3/1 下午11:59, Richard Henderson 写道:
> On 2/28/22 16:27, Weiwei Li wrote:
>>
>> 在 2022/3/1 上午9:44, Weiwei Li 写道:
>>>
>>> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>>>> On 2/28/22 04:48, Weiwei Li wrote:
>>>>> +/* Crypto Extension */
>>>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>>>> +                              target_ulong *ret_value,
>>>>> +                              target_ulong new_value, 
>>>>> target_ulong write_mask)
>>>>> +{
>>>>> +    if (!write_mask) {
>>>>> +        return RISCV_EXCP_ILLEGAL_INST;
>>>>> +    }
>>>>
>>>> This is incorrect.  The error should only be with a write-mask of 
>>>> the actual x0 register, not another register which happens to 
>>>> contain 0.  There is in fact no way to diagnose exactly what you 
>>>> want here, which IIRC has an existing fixme comment somewhere.
>>> Yeah. write_mask is also used in riscv_csrrw_check to check whether 
>>> the read-only csr is written. We cannot distinguish x0 and reg which 
>>> contains 0  here without changing total progress of csr read/write.
>>>>
>> I seems misunderstand the code for csr read/write:  write_mask will 
>> be set zero only for read-only operation (CSRRS/CSRRC with rs1=x0 or 
>> CSRRSI/CSRRCI with uimm=0) via do_csrr --> helper_csrr -> riscv_csrrw 
>> call-chain.
>>
>> The write_mask for do_csrw and do_csrrw will not be zero.
>>
>> As said in the spec :
>>
>> "TheseedCSR must be accessed with a read-write instruction. A 
>> read-only instruction such asCSRRS/CSRRC
>> withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction 
>> exception. "
>>
>> So it's suitable to check write_mask here.
>
> Consider CSRRS with rs1=x31.  In that case mask will be the value in 
> x31.  Even if the value is 0, this is still considered a read-write 
> instruction.
Yeah. I lost this kind of case . So this is a bug. Maybe we can add a 
new parameter like  'write' to helper_csrrw to indicate that write 
operation should be done.
>
>
> r~



  reply	other threads:[~2022-03-02  1:02 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-28 14:47 [PATCH v7 00/14] support subsets of scalar crypto extension Weiwei Li
2022-02-28 14:47 ` Weiwei Li
2022-02-28 14:47 ` [PATCH v7 01/14] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li
2022-02-28 14:47   ` Weiwei Li
2022-02-28 14:47 ` [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension Weiwei Li
2022-02-28 14:47   ` Weiwei Li
2022-02-28 18:54   ` Richard Henderson
2022-02-28 18:54     ` Richard Henderson
2022-02-28 14:47 ` [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension Weiwei Li
2022-02-28 14:47   ` Weiwei Li
2022-02-28 18:55   ` Richard Henderson
2022-02-28 18:55     ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 04/14] target/riscv: rvk: add support for zbkx extension Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 05/14] crypto: move sm4_sbox from target/arm Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32 Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 18:57   ` Richard Henderson
2022-02-28 18:57     ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64 Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 19:01   ` Richard Henderson
2022-02-28 19:01     ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 19:03   ` Richard Henderson
2022-02-28 19:03     ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 " Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 19:38   ` Richard Henderson
2022-02-28 19:38     ` Richard Henderson
2022-03-01  1:28     ` Weiwei Li
2022-03-01  1:28       ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 " Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 19:40   ` Richard Henderson
2022-02-28 19:40     ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 19:44   ` Richard Henderson
2022-02-28 19:44     ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 20:11   ` Richard Henderson
2022-02-28 20:11     ` Richard Henderson
2022-03-01  1:44     ` Weiwei Li
2022-03-01  1:44       ` Weiwei Li
2022-03-01  2:27       ` Weiwei Li
2022-03-01  2:27         ` Weiwei Li
2022-03-01 15:59         ` Richard Henderson
2022-03-01 15:59           ` Richard Henderson
2022-03-02  0:57           ` Weiwei Li [this message]
2022-03-02  0:57             ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li
2022-02-28 14:48   ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 14/14] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li
2022-02-28 14:48   ` Weiwei Li

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