From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>, Tvrtko Ursulin <tvrtko.ursulin@intel.com>, dri-devel@lists.freedesktop.org, Prasad Nallani <prasad.nallani@intel.com>, Aravind Iddamsetty <aravind.iddamsetty@intel.com> Subject: [PATCH v3 07/13] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Date: Tue, 1 Mar 2022 15:15:43 -0800 [thread overview] Message-ID: <20220301231549.1817978-8-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220301231549.1817978-1-matthew.d.roper@intel.com> In Dual Context mode the EUs are shared between render and compute command streamers. The hardware provides a field in the lrc descriptor to indicate the prioritization of the thread dispatch associated to the corresponding context. The context priority is set to 'low' at creation time and relies on the existing context priority to set it to low/normal/high. Bspec: 46145, 46260 Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by: Prasad Nallani <prasad.nallani@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + .../drm/i915/gt/intel_execlists_submission.c | 6 +++++- drivers/gpu/drm/i915/gt/intel_lrc.h | 17 +++++++++++++++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index b0982a9e4476..2136c56d3abc 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -435,8 +435,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, engine->props.preempt_timeout_ms = 0; /* features common between engines sharing EUs */ - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; + } engine->defaults = engine->props; /* never to change again */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 5fa5f21bbf2d..19ff8758e34d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -525,6 +525,7 @@ struct intel_engine_cs { #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8) #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9) +#define I915_ENGINE_HAS_EU_PRIORITY BIT(10) unsigned int flags; /* diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 47fca5ebfa76..c8407cc96c42 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -665,9 +665,13 @@ static inline void execlists_schedule_out(struct i915_request *rq) static u64 execlists_update_context(struct i915_request *rq) { struct intel_context *ce = rq->context; - u64 desc = ce->lrc.desc; + u64 desc; u32 tail, prev; + desc = ce->lrc.desc; + if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY) + desc |= lrc_desc_priority(rq_prio(rq)); + /* * WaIdleLiteRestore:bdw,skl * diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h index bb0e6c5b9922..6e4f9f58fca5 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h @@ -6,6 +6,9 @@ #ifndef __INTEL_LRC_H__ #define __INTEL_LRC_H__ +#include "i915_priolist_types.h" + +#include <linux/bitfield.h> #include <linux/types.h> struct drm_i915_gem_object; @@ -90,6 +93,10 @@ enum { #define GEN8_CTX_L3LLC_COHERENT (1 << 5) #define GEN8_CTX_PRIVILEGE (1 << 8) #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 +#define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9) +#define GEN12_CTX_PRIORITY_HIGH FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2) +#define GEN12_CTX_PRIORITY_NORMAL FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1) +#define GEN12_CTX_PRIORITY_LOW FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0) #define GEN8_CTX_ID_SHIFT 32 #define GEN8_CTX_ID_WIDTH 21 #define GEN11_SW_CTX_ID_SHIFT 37 @@ -103,4 +110,14 @@ enum { #define XEHP_SW_COUNTER_SHIFT 58 #define XEHP_SW_COUNTER_WIDTH 6 +static inline u32 lrc_desc_priority(int prio) +{ + if (prio > I915_PRIORITY_NORMAL) + return GEN12_CTX_PRIORITY_HIGH; + else if (prio < I915_PRIORITY_NORMAL) + return GEN12_CTX_PRIORITY_LOW; + else + return GEN12_CTX_PRIORITY_NORMAL; +} + #endif /* __INTEL_LRC_H__ */ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v3 07/13] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Date: Tue, 1 Mar 2022 15:15:43 -0800 [thread overview] Message-ID: <20220301231549.1817978-8-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220301231549.1817978-1-matthew.d.roper@intel.com> In Dual Context mode the EUs are shared between render and compute command streamers. The hardware provides a field in the lrc descriptor to indicate the prioritization of the thread dispatch associated to the corresponding context. The context priority is set to 'low' at creation time and relies on the existing context priority to set it to low/normal/high. Bspec: 46145, 46260 Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by: Prasad Nallani <prasad.nallani@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + .../drm/i915/gt/intel_execlists_submission.c | 6 +++++- drivers/gpu/drm/i915/gt/intel_lrc.h | 17 +++++++++++++++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index b0982a9e4476..2136c56d3abc 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -435,8 +435,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, engine->props.preempt_timeout_ms = 0; /* features common between engines sharing EUs */ - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; + } engine->defaults = engine->props; /* never to change again */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 5fa5f21bbf2d..19ff8758e34d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -525,6 +525,7 @@ struct intel_engine_cs { #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7) #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8) #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9) +#define I915_ENGINE_HAS_EU_PRIORITY BIT(10) unsigned int flags; /* diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 47fca5ebfa76..c8407cc96c42 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -665,9 +665,13 @@ static inline void execlists_schedule_out(struct i915_request *rq) static u64 execlists_update_context(struct i915_request *rq) { struct intel_context *ce = rq->context; - u64 desc = ce->lrc.desc; + u64 desc; u32 tail, prev; + desc = ce->lrc.desc; + if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY) + desc |= lrc_desc_priority(rq_prio(rq)); + /* * WaIdleLiteRestore:bdw,skl * diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h index bb0e6c5b9922..6e4f9f58fca5 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h @@ -6,6 +6,9 @@ #ifndef __INTEL_LRC_H__ #define __INTEL_LRC_H__ +#include "i915_priolist_types.h" + +#include <linux/bitfield.h> #include <linux/types.h> struct drm_i915_gem_object; @@ -90,6 +93,10 @@ enum { #define GEN8_CTX_L3LLC_COHERENT (1 << 5) #define GEN8_CTX_PRIVILEGE (1 << 8) #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 +#define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9) +#define GEN12_CTX_PRIORITY_HIGH FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2) +#define GEN12_CTX_PRIORITY_NORMAL FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1) +#define GEN12_CTX_PRIORITY_LOW FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0) #define GEN8_CTX_ID_SHIFT 32 #define GEN8_CTX_ID_WIDTH 21 #define GEN11_SW_CTX_ID_SHIFT 37 @@ -103,4 +110,14 @@ enum { #define XEHP_SW_COUNTER_SHIFT 58 #define XEHP_SW_COUNTER_WIDTH 6 +static inline u32 lrc_desc_priority(int prio) +{ + if (prio > I915_PRIORITY_NORMAL) + return GEN12_CTX_PRIORITY_HIGH; + else if (prio < I915_PRIORITY_NORMAL) + return GEN12_CTX_PRIORITY_LOW; + else + return GEN12_CTX_PRIORITY_NORMAL; +} + #endif /* __INTEL_LRC_H__ */ -- 2.34.1
next prev parent reply other threads:[~2022-03-01 23:17 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-01 23:15 [PATCH v3 00/13] i915: Prepare for Xe_HP compute engines Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 01/13] drm/i915/xehp: Define compute class and engine Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 02/13] drm/i915/xehp: CCS shares the render reset domain Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 03/13] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 04/13] drm/i915/xehp: compute engine pipe_control Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 05/13] drm/i915/xehp: CCS should use RCS setup functions Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 06/13] drm/i915: Move context descriptor fields to intel_lrc.h Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` Matt Roper [this message] 2022-03-01 23:15 ` [Intel-gfx] [PATCH v3 07/13] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper 2022-03-01 23:15 ` [PATCH v3 08/13] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:51 ` Umesh Nerlige Ramappa 2022-03-02 0:04 ` Matt Roper 2022-03-02 0:15 ` [PATCH v4 " Matt Roper 2022-03-02 0:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 09/13] drm/i915/xehp/guc: enable compute engine inside GuC Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:38 ` Ceraolo Spurio, Daniele 2022-03-01 23:38 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-03-02 0:18 ` Matt Roper 2022-03-02 0:18 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 10/13] drm/i915/xehp: Don't support parallel submission on compute / render Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 11/13] drm/i915/xehp: handle fused off CCS engines Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:47 ` Matt Roper 2022-03-01 23:47 ` [Intel-gfx] " Matt Roper 2022-03-02 5:20 ` [PATCH v5 " Matt Roper 2022-03-02 5:20 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 12/13] drm/i915/xehp: Add compute workarounds Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-01 23:15 ` [PATCH v3 13/13] drm/i915/xehpsdv: Move render/compute engine reset domains related workarounds Matt Roper 2022-03-01 23:15 ` [Intel-gfx] " Matt Roper 2022-03-02 0:07 ` Matt Roper 2022-03-02 0:07 ` [Intel-gfx] " Matt Roper 2022-03-02 2:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Prepare for Xe_HP compute engines (rev3) Patchwork 2022-03-02 2:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-02 2:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2022-03-02 6:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Prepare for Xe_HP compute engines (rev4) Patchwork 2022-03-02 6:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-02 6:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-02 13:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-03-02 14:54 ` Matt Roper
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