From: James Clark <james.clark@arm.com> To: suzuki.poulose@arm.com, coresight@lists.linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com Cc: mathieu.poirier@linaro.org, leo.yan@linaro.com, James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/15] coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses Date: Fri, 4 Mar 2022 17:19:09 +0000 [thread overview] Message-ID: <20220304171913.2292458-13-james.clark@arm.com> (raw) In-Reply-To: <20220304171913.2292458-1-james.clark@arm.com> This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +++--- drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 88353f8ba414..87299e99dabb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) - config->ss_status[i] &= ~BIT(31); + config->ss_status[i] &= ~TRCSSCSRn_STATUS; etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 29188b1a4646..7dd7636fc2a7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1792,9 +1792,9 @@ static ssize_t sshot_ctrl_store(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->ss_idx; - config->ss_ctrl[idx] = val & GENMASK(24, 0); + config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &= ~BIT(31); + config->ss_status[idx] &= ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); return size; } @@ -1844,7 +1844,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, idx = config->ss_idx; config->ss_pe_cmp[idx] = val & GENMASK(7, 0); /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &= ~BIT(31); + config->ss_status[idx] &= ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 802ddbe2eecd..b4217eaab450 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -214,6 +214,10 @@ #define TRCACATRn_CONTEXTTYPE_VMID BIT(3) #define TRCACATRn_CONTEXT_MASK GENMASK(6, 4) #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) + +#define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: James Clark <james.clark@arm.com> To: suzuki.poulose@arm.com, coresight@lists.linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com Cc: mathieu.poirier@linaro.org, leo.yan@linaro.com, James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/15] coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses Date: Fri, 4 Mar 2022 17:19:09 +0000 [thread overview] Message-ID: <20220304171913.2292458-13-james.clark@arm.com> (raw) In-Reply-To: <20220304171913.2292458-1-james.clark@arm.com> This is a no-op change for style and consistency and has no effect on the binary output by the compiler. In sysreg.h fields are defined as the register name followed by the field name and then _MASK. This allows for grepping for fields by name rather than using magic numbers. Signed-off-by: James Clark <james.clark@arm.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 +++--- drivers/hwtracing/coresight/coresight-etm4x.h | 4 ++++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 88353f8ba414..87299e99dabb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -443,7 +443,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) - config->ss_status[i] &= ~BIT(31); + config->ss_status[i] &= ~TRCSSCSRn_STATUS; etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 29188b1a4646..7dd7636fc2a7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1792,9 +1792,9 @@ static ssize_t sshot_ctrl_store(struct device *dev, spin_lock(&drvdata->spinlock); idx = config->ss_idx; - config->ss_ctrl[idx] = val & GENMASK(24, 0); + config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &= ~BIT(31); + config->ss_status[idx] &= ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); return size; } @@ -1844,7 +1844,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, idx = config->ss_idx; config->ss_pe_cmp[idx] = val & GENMASK(7, 0); /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &= ~BIT(31); + config->ss_status[idx] &= ~TRCSSCSRn_STATUS; spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 802ddbe2eecd..b4217eaab450 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -214,6 +214,10 @@ #define TRCACATRn_CONTEXTTYPE_VMID BIT(3) #define TRCACATRn_CONTEXT_MASK GENMASK(6, 4) #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) + +#define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-03-04 17:20 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-04 17:18 [PATCH v3 00/15] Make ETM register accesses consistent with sysreg.h James Clark 2022-03-04 17:18 ` James Clark 2022-03-04 17:18 ` [PATCH v3 01/15] coresight: etm4x: Cleanup TRCIDR0 register accesses James Clark 2022-03-04 17:18 ` James Clark 2022-04-12 8:28 ` Mike Leach 2022-04-12 8:28 ` Mike Leach 2022-03-04 17:18 ` [PATCH v3 02/15] coresight: etm4x: Cleanup TRCIDR2 " James Clark 2022-03-04 17:18 ` James Clark 2022-04-12 8:30 ` Mike Leach 2022-04-12 8:30 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 03/15] coresight: etm4x: Cleanup TRCIDR3 " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 8:34 ` Mike Leach 2022-04-12 8:34 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 04/15] coresight: etm4x: Cleanup TRCIDR4 " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 8:37 ` Mike Leach 2022-04-12 8:37 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 05/15] coresight: etm4x: Cleanup TRCIDR5 " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 8:41 ` Mike Leach 2022-04-12 8:41 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 06/15] coresight: etm4x: Cleanup TRCCONFIGR " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 8:49 ` Mike Leach 2022-04-12 8:49 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 07/15] coresight: etm4x: Cleanup TRCEVENTCTL1R " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 9:09 ` Mike Leach 2022-04-12 9:09 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 08/15] coresight: etm4x: Cleanup TRCSTALLCTLR " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 9:18 ` Mike Leach 2022-04-12 9:18 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 09/15] coresight: etm4x: Cleanup TRCVICTLR " James Clark 2022-03-04 17:19 ` James Clark 2022-03-23 15:59 ` Mathieu Poirier 2022-03-23 15:59 ` Mathieu Poirier 2022-03-28 10:41 ` James Clark 2022-03-28 10:41 ` James Clark 2022-04-12 10:15 ` Mike Leach 2022-04-12 10:15 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 10/15] coresight: etm3x: Cleanup ETMTECR1 " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 10:17 ` Mike Leach 2022-04-12 10:17 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 11/15] coresight: etm4x: Cleanup TRCACATRn " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 10:30 ` Mike Leach 2022-04-12 10:30 ` Mike Leach 2022-03-04 17:19 ` James Clark [this message] 2022-03-04 17:19 ` [PATCH v3 12/15] coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn " James Clark 2022-04-12 10:32 ` Mike Leach 2022-04-12 10:32 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 13/15] coresight: etm4x: Cleanup TRCSSPCICRn " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 10:39 ` Mike Leach 2022-04-12 10:39 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 14/15] coresight: etm4x: Cleanup TRCBBCTLR " James Clark 2022-03-04 17:19 ` James Clark 2022-04-12 10:41 ` Mike Leach 2022-04-12 10:41 ` Mike Leach 2022-03-04 17:19 ` [PATCH v3 15/15] coresight: etm4x: Cleanup TRCRSCTLRn " James Clark 2022-03-04 17:19 ` James Clark 2022-03-23 16:15 ` Mathieu Poirier 2022-03-23 16:15 ` Mathieu Poirier 2022-04-12 10:42 ` Mike Leach 2022-04-12 10:42 ` Mike Leach 2022-03-23 16:22 ` [PATCH v3 00/15] Make ETM register accesses consistent with sysreg.h Mathieu Poirier 2022-03-23 16:22 ` Mathieu Poirier 2022-03-28 10:41 ` James Clark 2022-03-28 10:41 ` James Clark 2022-04-13 17:08 ` Mathieu Poirier 2022-04-13 17:08 ` Mathieu Poirier 2022-04-14 8:57 ` James Clark 2022-04-14 8:57 ` James Clark
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