Re: [PATCH v3 13/15] coresight: etm4x: Cleanup TRCSSPCICRn register accesses

[Mike Leach <mike.leach@linaro.org>]

On Fri, 4 Mar 2022 at 17:19, James Clark <james.clark@arm.com> wrote:
>
> This is a no-op change for style and consistency and has no effect on
> the binary output by the compiler. In sysreg.h fields are defined as
> the register name followed by the field name and then _MASK. This
> allows for grepping for fields by name rather than using magic numbers.
>
> Signed-off-by: James Clark <james.clark@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
>  drivers/hwtracing/coresight/coresight-etm4x.h       | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 7dd7636fc2a7..25f76a656308 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1842,7 +1842,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
>
>         spin_lock(&drvdata->spinlock);
>         idx = config->ss_idx;
> -       config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
> +       config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
>         /* must clear bit 31 in related status register on programming */
>         config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
>         spin_unlock(&drvdata->spinlock);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index b4217eaab450..3b81c104a44b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -218,6 +218,8 @@
>  #define TRCSSCSRn_STATUS                       BIT(31)
>  #define TRCSSCCRn_SAC_ARC_RST_MASK             GENMASK(24, 0)
>
> +#define TRCSSPCICRn_PC_MASK                    GENMASK(7, 0)
> +
>  /*
>   * System instructions to access ETM registers.
>   * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> --
> 2.28.0
>

Reviewed-by: Mike Leach <mike.leach@linaro.org>

-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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