From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: linuxarm@huawei.com, qemu-devel@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>, "Marcel Apfelbaum" <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Markus Armbruster" <armbru@redhat.com> Cc: linux-cxl@vger.kernel.org, "Ben Widawsky" <ben.widawsky@intel.com>, "Peter Maydell" <peter.maydell@linaro.org>, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Saransh Gupta1" <saransh@ibm.com>, "Shreyas Shah" <shreyas.shah@elastics.cloud>, "Chris Browy" <cbrowy@avery-design.com>, "Samarth Saxena" <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: [PATCH v7 28/46] acpi/cxl: Introduce CFMWS structures in CEDT Date: Sun, 6 Mar 2022 17:41:19 +0000 [thread overview] Message-ID: <20220306174137.5707-29-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20220306174137.5707-1-Jonathan.Cameron@huawei.com> From: Ben Widawsky <ben.widawsky@intel.com> The CEDT CXL Fixed Window Memory Window Structures (CFMWs) define regions of the host phyiscal address map which (via an impdef means) are configured such that they have a particular interleave setup across one or more CXL Host Bridges. Reported-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> --- hw/acpi/cxl.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index 442f836a3e..50efc7f690 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -60,6 +60,64 @@ static void cedt_build_chbs(GArray *table_data, PXBDev *cxl) build_append_int_noprefix(table_data, memory_region_size(mr), 8); } +/* + * CFMWS entries in CXL 2.0 ECN: CEDT CFMWS & QTG _DSM. + * Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory + * interleaving. + */ +static void cedt_build_cfmws(GArray *table_data, MachineState *ms) +{ + CXLState *cxls = ms->cxl_devices_state; + GList *it; + + for (it = cxls->fixed_windows; it; it = it->next) { + CXLFixedWindow *fw = it->data; + int i; + + /* Type */ + build_append_int_noprefix(table_data, 1, 1); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); + + /* Record Length */ + build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + + /* Base HPA */ + build_append_int_noprefix(table_data, fw->mr.addr, 8); + + /* Window Size */ + build_append_int_noprefix(table_data, fw->size, 8); + + /* Host Bridge Interleave Ways */ + build_append_int_noprefix(table_data, fw->enc_int_ways, 1); + + /* Host Bridge Interleave Arithmetic */ + build_append_int_noprefix(table_data, 0, 1); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + + /* Host Bridge Interleave Granularity */ + build_append_int_noprefix(table_data, fw->enc_int_gran, 4); + + /* Window Restrictions */ + build_append_int_noprefix(table_data, 0x0f, 2); /* No restrictions */ + + /* QTG ID */ + build_append_int_noprefix(table_data, 0, 2); + + /* Host Bridge List (list of UIDs - currently bus_nr) */ + for (i = 0; i < fw->num_targets; i++) { + g_assert(fw->target_hbs[i]); + build_append_int_noprefix(table_data, fw->target_hbs[i]->bus_nr, 4); + } + } +} + static int cxl_foreach_pxb_hb(Object *obj, void *opaque) { Aml *cedt = opaque; @@ -86,6 +144,7 @@ void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data, /* reserve space for CEDT header */ object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, cedt); + cedt_build_cfmws(cedt->buf, ms); /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len); -- 2.32.0
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org> To: linuxarm@huawei.com, qemu-devel@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>, "Marcel Apfelbaum" <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, "Markus Armbruster" <armbru@redhat.com> Cc: linux-cxl@vger.kernel.org, "Ben Widawsky" <ben.widawsky@intel.com>, "Peter Maydell" <peter.maydell@linaro.org>, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Saransh Gupta1" <saransh@ibm.com>, "Shreyas Shah" <shreyas.shah@elastics.cloud>, "Chris Browy" <cbrowy@avery-design.com>, "Samarth Saxena" <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: [PATCH v7 28/46] acpi/cxl: Introduce CFMWS structures in CEDT Date: Sun, 6 Mar 2022 17:41:19 +0000 [thread overview] Message-ID: <20220306174137.5707-29-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20220306174137.5707-1-Jonathan.Cameron@huawei.com> From: Ben Widawsky <ben.widawsky@intel.com> The CEDT CXL Fixed Window Memory Window Structures (CFMWs) define regions of the host phyiscal address map which (via an impdef means) are configured such that they have a particular interleave setup across one or more CXL Host Bridges. Reported-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> --- hw/acpi/cxl.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index 442f836a3e..50efc7f690 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -60,6 +60,64 @@ static void cedt_build_chbs(GArray *table_data, PXBDev *cxl) build_append_int_noprefix(table_data, memory_region_size(mr), 8); } +/* + * CFMWS entries in CXL 2.0 ECN: CEDT CFMWS & QTG _DSM. + * Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory + * interleaving. + */ +static void cedt_build_cfmws(GArray *table_data, MachineState *ms) +{ + CXLState *cxls = ms->cxl_devices_state; + GList *it; + + for (it = cxls->fixed_windows; it; it = it->next) { + CXLFixedWindow *fw = it->data; + int i; + + /* Type */ + build_append_int_noprefix(table_data, 1, 1); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); + + /* Record Length */ + build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + + /* Base HPA */ + build_append_int_noprefix(table_data, fw->mr.addr, 8); + + /* Window Size */ + build_append_int_noprefix(table_data, fw->size, 8); + + /* Host Bridge Interleave Ways */ + build_append_int_noprefix(table_data, fw->enc_int_ways, 1); + + /* Host Bridge Interleave Arithmetic */ + build_append_int_noprefix(table_data, 0, 1); + + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); + + /* Host Bridge Interleave Granularity */ + build_append_int_noprefix(table_data, fw->enc_int_gran, 4); + + /* Window Restrictions */ + build_append_int_noprefix(table_data, 0x0f, 2); /* No restrictions */ + + /* QTG ID */ + build_append_int_noprefix(table_data, 0, 2); + + /* Host Bridge List (list of UIDs - currently bus_nr) */ + for (i = 0; i < fw->num_targets; i++) { + g_assert(fw->target_hbs[i]); + build_append_int_noprefix(table_data, fw->target_hbs[i]->bus_nr, 4); + } + } +} + static int cxl_foreach_pxb_hb(Object *obj, void *opaque) { Aml *cedt = opaque; @@ -86,6 +144,7 @@ void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data, /* reserve space for CEDT header */ object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, cedt); + cedt_build_cfmws(cedt->buf, ms); /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len); -- 2.32.0
next prev parent reply other threads:[~2022-03-06 17:55 UTC|newest] Thread overview: 124+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-06 17:40 [PATCH v7 00/46] CXl 2.0 emulation Support Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 01/46] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 02/46] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 03/46] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 04/46] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 05/46] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 06/46] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 07/46] hw/cxl/device: Add memory device utilities Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:40 ` [PATCH v7 08/46] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron 2022-03-06 17:40 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 09/46] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 10/46] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 11/46] hw/pxb: Use a type for realizing expanders Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 12/46] hw/pci/cxl: Create a CXL bus type Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 13/46] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 14/46] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 15/46] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 16/46] hw/cxl/rp: Add a root port Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 17/46] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 18/46] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 19/46] hw/cxl/device: Add some trivial commands Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 20/46] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 21/46] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 22/46] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 23/46] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 24/46] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 21:31 ` Michael S. Tsirkin 2022-03-06 21:31 ` Michael S. Tsirkin 2022-03-07 17:01 ` Jonathan Cameron 2022-03-07 17:01 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 25/46] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 26/46] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 27/46] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` Jonathan Cameron [this message] 2022-03-06 17:41 ` [PATCH v7 28/46] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 29/46] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 30/46] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 31/46] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 32/46] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 33/46] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 34/46] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 35/46] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 36/46] i386/pc: Enable CXL fixed memory windows Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 37/46] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 38/46] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 39/46] tests/acpi: Add tables " Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 40/46] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 41/46] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 42/46] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 43/46] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 44/46] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 45/46] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 17:41 ` [PATCH v7 46/46] cxl/cxl-host: Support interleave decoding with one level of switches Jonathan Cameron 2022-03-06 17:41 ` Jonathan Cameron via 2022-03-06 21:33 ` [PATCH v7 00/46] CXl 2.0 emulation Support Michael S. Tsirkin 2022-03-06 21:33 ` Michael S. Tsirkin 2022-03-07 9:39 ` Jonathan Cameron via 2022-03-07 9:39 ` Jonathan Cameron 2022-03-09 8:15 ` Peter Xu 2022-03-09 8:15 ` Peter Xu 2022-03-09 11:28 ` Jonathan Cameron 2022-03-09 11:28 ` Jonathan Cameron via 2022-03-10 8:02 ` Peter Xu 2022-03-10 8:02 ` Peter Xu 2022-03-16 16:50 ` Jonathan Cameron 2022-03-16 16:50 ` Jonathan Cameron via 2022-03-16 17:16 ` Mark Cave-Ayland 2022-03-16 17:16 ` Mark Cave-Ayland 2022-03-16 17:58 ` Jonathan Cameron 2022-03-16 17:58 ` Jonathan Cameron via 2022-03-16 18:26 ` Jonathan Cameron 2022-03-16 18:26 ` Jonathan Cameron via 2022-03-17 8:12 ` Mark Cave-Ayland 2022-03-17 8:12 ` Mark Cave-Ayland 2022-03-17 16:47 ` Jonathan Cameron 2022-03-17 16:47 ` Jonathan Cameron via 2022-03-18 8:14 ` Mark Cave-Ayland 2022-03-18 8:14 ` Mark Cave-Ayland 2022-03-18 10:08 ` Jonathan Cameron 2022-03-18 10:08 ` Jonathan Cameron via
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220306174137.5707-29-Jonathan.Cameron@huawei.com \ --to=jonathan.cameron@huawei.com \ --cc=alex.bennee@linaro.org \ --cc=armbru@redhat.com \ --cc=ben.widawsky@intel.com \ --cc=cbrowy@avery-design.com \ --cc=dan.j.williams@intel.com \ --cc=f4bug@amsat.org \ --cc=imammedo@redhat.com \ --cc=linux-cxl@vger.kernel.org \ --cc=linuxarm@huawei.com \ --cc=marcel@redhat.com \ --cc=mst@redhat.com \ --cc=peter.maydell@linaro.org \ --cc=qemu-devel@nongnu.org \ --cc=samarths@cadence.com \ --cc=saransh@ibm.com \ --cc=shameerali.kolothum.thodi@huawei.com \ --cc=shreyas.shah@elastics.cloud \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.