* [PATCH v4 0/4] Add basic node support for Mediatek MT8186 SoC
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
MT8186 is a SoC based on 64bit ARMv8 architecture.
It contains 6 CA55 and 2 CA78 cores.
MT8186 share many HW IP with MT65xx series.
This patchset was tested on MT8186 evaluation board to shell.
Based on tag: next-20220310, linux-next/master.
changes since v3:
- remove serial, mmc and phy patch from series. (already merged)
- remove mcusysoff node
- move oscillator nodes at the head of dts
- change name from usb-phy to t-phy
changes since v2:$
- add soc {} in mt8186.dtsi
changes since v1:
- add dt-bindings: arm: Add compatible for Mediatek MT8186
Allen-KH Cheng (4):
dt-bindings: timer: Add compatible for Mediatek MT8186
dt-bindings: watchdog: Add compatible for Mediatek MT8186
dt-bindings: arm: Add compatible for Mediatek MT8186
arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and
Makefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../bindings/timer/mediatek,mtk-timer.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++
6 files changed, 387 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
--
2.18.0
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v4 0/4] Add basic node support for Mediatek MT8186 SoC
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
MT8186 is a SoC based on 64bit ARMv8 architecture.
It contains 6 CA55 and 2 CA78 cores.
MT8186 share many HW IP with MT65xx series.
This patchset was tested on MT8186 evaluation board to shell.
Based on tag: next-20220310, linux-next/master.
changes since v3:
- remove serial, mmc and phy patch from series. (already merged)
- remove mcusysoff node
- move oscillator nodes at the head of dts
- change name from usb-phy to t-phy
changes since v2:$
- add soc {} in mt8186.dtsi
changes since v1:
- add dt-bindings: arm: Add compatible for Mediatek MT8186
Allen-KH Cheng (4):
dt-bindings: timer: Add compatible for Mediatek MT8186
dt-bindings: watchdog: Add compatible for Mediatek MT8186
dt-bindings: arm: Add compatible for Mediatek MT8186
arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and
Makefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../bindings/timer/mediatek,mtk-timer.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++
6 files changed, 387 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v4 0/4] Add basic node support for Mediatek MT8186 SoC
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
MT8186 is a SoC based on 64bit ARMv8 architecture.
It contains 6 CA55 and 2 CA78 cores.
MT8186 share many HW IP with MT65xx series.
This patchset was tested on MT8186 evaluation board to shell.
Based on tag: next-20220310, linux-next/master.
changes since v3:
- remove serial, mmc and phy patch from series. (already merged)
- remove mcusysoff node
- move oscillator nodes at the head of dts
- change name from usb-phy to t-phy
changes since v2:$
- add soc {} in mt8186.dtsi
changes since v1:
- add dt-bindings: arm: Add compatible for Mediatek MT8186
Allen-KH Cheng (4):
dt-bindings: timer: Add compatible for Mediatek MT8186
dt-bindings: watchdog: Add compatible for Mediatek MT8186
dt-bindings: arm: Add compatible for Mediatek MT8186
arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and
Makefile
.../devicetree/bindings/arm/mediatek.yaml | 4 +
.../bindings/timer/mediatek,mtk-timer.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++
6 files changed, 387 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 13:07 ` Allen-KH Cheng
-1 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index fbd76a8e023b..6f1f9dba6e88 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -23,6 +23,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
--
2.18.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index fbd76a8e023b..6f1f9dba6e88 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -23,6 +23,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index fbd76a8e023b..6f1f9dba6e88 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -23,6 +23,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 13:07 ` Allen-KH Cheng
-1 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of watchdog for Mediatek
MT8186 SoC Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index a97418c74f6b..762c62e428ef 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
+ "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
--
2.18.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of watchdog for Mediatek
MT8186 SoC Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index a97418c74f6b..762c62e428ef 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
+ "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation of watchdog for Mediatek
MT8186 SoC Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index a97418c74f6b..762c62e428ef 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
+ "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 3/4] dt-bindings: arm: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 13:07 ` Allen-KH Cheng
-1 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation for the Mediatek MT8186
reference board.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index ab0593c77321..ac5a64523b21 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8186-evb
+ - const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8195-evb
--
2.18.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 3/4] dt-bindings: arm: Add compatible for Mediatek MT8186
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation for the Mediatek MT8186
reference board.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index ab0593c77321..ac5a64523b21 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8186-evb
+ - const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8195-evb
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 3/4] dt-bindings: arm: Add compatible for Mediatek MT8186
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
This commit adds dt-binding documentation for the Mediatek MT8186
reference board.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index ab0593c77321..ac5a64523b21 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -131,6 +131,10 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - items:
+ - enum:
+ - mediatek,mt8186-evb
+ - const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8195-evb
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 13:07 ` Allen-KH Cheng
-1 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Add basic chip support for Mediatek MT8186.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++
3 files changed, 381 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..d32fdcf9afc6 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
new file mode 100644
index 000000000000..eb23d1f19f87
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8186.dtsi"
+
+/ {
+ model = "MediaTek MT8186 evaluation board";
+ compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
new file mode 100644
index 000000000000..aa45c75b18c7
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
+ */
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8186";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk13m: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: oscillator1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0600>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0700>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ cpuoff_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1600>;
+ };
+
+ cpuoff_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1400>;
+ };
+
+ clusteroff_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <2100>;
+ };
+
+ clusteroff_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <1900>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, // distributor
+ <0 0x0c040000 0 0x200000>; // redistributor
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8186-wdt",
+ "mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
+ reg = <0 0x10007000 0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8186-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk13m>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11018000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8186-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg", "ahb_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8186-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: t-phy@11c80000 {
+ compatible = "mediatek,mt8186-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11c80000 0x1000>;
+
+ u2port1: usb2-phy1@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb3-phy1@700 {
+ reg = <0x700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy1: t-phy@11ca0000 {
+ compatible = "mediatek,mt8186-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11ca0000 0x1000>;
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,discth = <0x8>;
+ };
+ };
+ };
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Add basic chip support for Mediatek MT8186.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++
3 files changed, 381 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..d32fdcf9afc6 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
new file mode 100644
index 000000000000..eb23d1f19f87
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8186.dtsi"
+
+/ {
+ model = "MediaTek MT8186 evaluation board";
+ compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
new file mode 100644
index 000000000000..aa45c75b18c7
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
+ */
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8186";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk13m: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: oscillator1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0600>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0700>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ cpuoff_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1600>;
+ };
+
+ cpuoff_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1400>;
+ };
+
+ clusteroff_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <2100>;
+ };
+
+ clusteroff_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <1900>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, // distributor
+ <0 0x0c040000 0 0x200000>; // redistributor
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8186-wdt",
+ "mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
+ reg = <0 0x10007000 0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8186-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk13m>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11018000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8186-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg", "ahb_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8186-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: t-phy@11c80000 {
+ compatible = "mediatek,mt8186-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11c80000 0x1000>;
+
+ u2port1: usb2-phy1@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb3-phy1@700 {
+ reg = <0x700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy1: t-phy@11ca0000 {
+ compatible = "mediatek,mt8186-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11ca0000 0x1000>;
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,discth = <0x8>;
+ };
+ };
+ };
+};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-03-11 13:07 ` Allen-KH Cheng
0 siblings, 0 replies; 43+ messages in thread
From: Allen-KH Cheng @ 2022-03-11 13:07 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog,
Allen-KH Cheng
From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Add basic chip support for Mediatek MT8186.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++
3 files changed, 381 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..d32fdcf9afc6 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
new file mode 100644
index 000000000000..eb23d1f19f87
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8186.dtsi"
+
+/ {
+ model = "MediaTek MT8186 evaluation board";
+ compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
new file mode 100644
index 000000000000..aa45c75b18c7
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
+ */
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8186";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk13m: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: oscillator1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x0500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l>;
+ next-level-cache = <&l2_0>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0600>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75", "arm,armv8";
+ reg = <0x0700>;
+ enable-method = "psci";
+ clock-frequency = <2050000000>;
+ cpu-idle-states = <&cpuoff_b &clusteroff_b>;
+ next-level-cache = <&l2_1>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ cpuoff_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1600>;
+ };
+
+ cpuoff_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <1400>;
+ };
+
+ clusteroff_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <2100>;
+ };
+
+ clusteroff_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <100>;
+ exit-latency-us = <250>;
+ min-residency-us = <1900>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, // distributor
+ <0 0x0c040000 0 0x200000>; // redistributor
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8186-wdt",
+ "mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
+ reg = <0 0x10007000 0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8186-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk13m>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11018000 {
+ compatible = "mediatek,mt8186-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8186-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg", "ahb_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8186-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: t-phy@11c80000 {
+ compatible = "mediatek,mt8186-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11c80000 0x1000>;
+
+ u2port1: usb2-phy1@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb3-phy1@700 {
+ reg = <0x700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy1: t-phy@11ca0000 {
+ compatible = "mediatek,mt8186-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11ca0000 0x1000>;
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ mediatek,discth = <0x8>;
+ };
+ };
+ };
+};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 15:50 ` Rob Herring
-1 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: hsinyi, Thomas Gleixner, Guenter Roeck, Allen-KH Cheng,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Daniel Lezcano, Wim Van Sebroeck, Matthias Brugger,
Kishon Vijay Abraham I
On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
> Platform.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-03-11 15:50 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: hsinyi, Thomas Gleixner, Guenter Roeck, Allen-KH Cheng,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Daniel Lezcano, Wim Van Sebroeck, Matthias Brugger,
Kishon Vijay Abraham I
On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
> Platform.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-03-11 15:50 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: hsinyi, Thomas Gleixner, Guenter Roeck, Allen-KH Cheng,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Daniel Lezcano, Wim Van Sebroeck, Matthias Brugger,
Kishon Vijay Abraham I
On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
> Platform.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 15:50 ` Rob Herring
-1 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Guenter Roeck, Rob Herring, Allen-KH Cheng, linux-arm-kernel,
linux-kernel, Thomas Gleixner, linux-mediatek, linux-watchdog,
devicetree, Kishon Vijay Abraham I, Wim Van Sebroeck, hsinyi,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Daniel Lezcano
On Fri, 11 Mar 2022 21:07:30 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation of watchdog for Mediatek
> MT8186 SoC Platform.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-03-11 15:50 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Guenter Roeck, Rob Herring, Allen-KH Cheng, linux-arm-kernel,
linux-kernel, Thomas Gleixner, linux-mediatek, linux-watchdog,
devicetree, Kishon Vijay Abraham I, Wim Van Sebroeck, hsinyi,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Daniel Lezcano
On Fri, 11 Mar 2022 21:07:30 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation of watchdog for Mediatek
> MT8186 SoC Platform.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-03-11 15:50 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:50 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Guenter Roeck, Rob Herring, Allen-KH Cheng, linux-arm-kernel,
linux-kernel, Thomas Gleixner, linux-mediatek, linux-watchdog,
devicetree, Kishon Vijay Abraham I, Wim Van Sebroeck, hsinyi,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Daniel Lezcano
On Fri, 11 Mar 2022 21:07:30 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation of watchdog for Mediatek
> MT8186 SoC Platform.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 3/4] dt-bindings: arm: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-11 15:51 ` Rob Herring
-1 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:51 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Thomas Gleixner, Guenter Roeck, linux-watchdog, Rob Herring,
devicetree, Project_Global_Chrome_Upstream_Group, linux-mediatek,
Allen-KH Cheng, hsinyi, Wim Van Sebroeck, Matthias Brugger,
linux-arm-kernel, Daniel Lezcano, Kishon Vijay Abraham I,
linux-kernel
On Fri, 11 Mar 2022 21:07:31 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation for the Mediatek MT8186
> reference board.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 3/4] dt-bindings: arm: Add compatible for Mediatek MT8186
@ 2022-03-11 15:51 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:51 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Thomas Gleixner, Guenter Roeck, linux-watchdog, Rob Herring,
devicetree, Project_Global_Chrome_Upstream_Group, linux-mediatek,
Allen-KH Cheng, hsinyi, Wim Van Sebroeck, Matthias Brugger,
linux-arm-kernel, Daniel Lezcano, Kishon Vijay Abraham I,
linux-kernel
On Fri, 11 Mar 2022 21:07:31 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation for the Mediatek MT8186
> reference board.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 3/4] dt-bindings: arm: Add compatible for Mediatek MT8186
@ 2022-03-11 15:51 ` Rob Herring
0 siblings, 0 replies; 43+ messages in thread
From: Rob Herring @ 2022-03-11 15:51 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Thomas Gleixner, Guenter Roeck, linux-watchdog, Rob Herring,
devicetree, Project_Global_Chrome_Upstream_Group, linux-mediatek,
Allen-KH Cheng, hsinyi, Wim Van Sebroeck, Matthias Brugger,
linux-arm-kernel, Daniel Lezcano, Kishon Vijay Abraham I,
linux-kernel
On Fri, 11 Mar 2022 21:07:31 +0800, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> This commit adds dt-binding documentation for the Mediatek MT8186
> reference board.
>
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
2022-03-11 15:50 ` Rob Herring
(?)
@ 2022-03-14 1:46 ` Rex-BC Chen
-1 siblings, 0 replies; 43+ messages in thread
From: Rex-BC Chen @ 2022-03-14 1:46 UTC (permalink / raw)
To: Rob Herring, Allen-KH Cheng
Cc: Guenter Roeck, Rob Herring, linux-arm-kernel, linux-kernel,
Thomas Gleixner, linux-mediatek, linux-watchdog, devicetree,
Kishon Vijay Abraham I, Wim Van Sebroeck, hsinyi,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Daniel Lezcano
On Fri, 2022-03-11 at 09:50 -0600, Rob Herring wrote:
> On Fri, 11 Mar 2022 21:07:30 +0800, Allen-KH Cheng wrote:
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > This commit adds dt-binding documentation of watchdog for Mediatek
> > MT8186 SoC Platform.
> >
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>
Hello Allen,
I have mentioned I also upstreamed wdt serires for MT8186 which is
inclduing binding patch, and my patch is accepted by Guenter in [1].
Please drop this patch in next version.
Thanks.
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git/commit/?h=watchdog-next&id=888423f98c8fbf67e8cb2df8099678ff57274911
BRs,
Rex
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-03-14 1:46 ` Rex-BC Chen
0 siblings, 0 replies; 43+ messages in thread
From: Rex-BC Chen @ 2022-03-14 1:46 UTC (permalink / raw)
To: Rob Herring, Allen-KH Cheng
Cc: Guenter Roeck, Rob Herring, linux-arm-kernel, linux-kernel,
Thomas Gleixner, linux-mediatek, linux-watchdog, devicetree,
Kishon Vijay Abraham I, Wim Van Sebroeck, hsinyi,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Daniel Lezcano
On Fri, 2022-03-11 at 09:50 -0600, Rob Herring wrote:
> On Fri, 11 Mar 2022 21:07:30 +0800, Allen-KH Cheng wrote:
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > This commit adds dt-binding documentation of watchdog for Mediatek
> > MT8186 SoC Platform.
> >
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>
Hello Allen,
I have mentioned I also upstreamed wdt serires for MT8186 which is
inclduing binding patch, and my patch is accepted by Guenter in [1].
Please drop this patch in next version.
Thanks.
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git/commit/?h=watchdog-next&id=888423f98c8fbf67e8cb2df8099678ff57274911
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: watchdog: Add compatible for Mediatek MT8186
@ 2022-03-14 1:46 ` Rex-BC Chen
0 siblings, 0 replies; 43+ messages in thread
From: Rex-BC Chen @ 2022-03-14 1:46 UTC (permalink / raw)
To: Rob Herring, Allen-KH Cheng
Cc: Guenter Roeck, Rob Herring, linux-arm-kernel, linux-kernel,
Thomas Gleixner, linux-mediatek, linux-watchdog, devicetree,
Kishon Vijay Abraham I, Wim Van Sebroeck, hsinyi,
Project_Global_Chrome_Upstream_Group, Matthias Brugger,
Daniel Lezcano
On Fri, 2022-03-11 at 09:50 -0600, Rob Herring wrote:
> On Fri, 11 Mar 2022 21:07:30 +0800, Allen-KH Cheng wrote:
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > This commit adds dt-binding documentation of watchdog for Mediatek
> > MT8186 SoC Platform.
> >
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <robh@kernel.org>
Hello Allen,
I have mentioned I also upstreamed wdt serires for MT8186 which is
inclduing binding patch, and my patch is accepted by Guenter in [1].
Please drop this patch in next version.
Thanks.
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git/commit/?h=watchdog-next&id=888423f98c8fbf67e8cb2df8099678ff57274911
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-03-11 13:07 ` Allen-KH Cheng
(?)
@ 2022-03-29 14:56 ` Matthias Brugger
-1 siblings, 0 replies; 43+ messages in thread
From: Matthias Brugger @ 2022-03-29 14:56 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
On 11/03/2022 14:07, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> Add basic chip support for Mediatek MT8186.
>
Thanks for your patch. I would love to wait a bit longer to see if we can get
the clock driver accepted. This way we could get rid of all the dummy clocks
defined in here.
Please send a new version once the clock driver is accepeted by Stephen, or ping
this series in a few month.
Thanks,
Matthias
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++
> 3 files changed, 381 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 8c1e18032f9f..d32fdcf9afc6 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> new file mode 100644
> index 000000000000..eb23d1f19f87
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +#include "mt8186.dtsi"
> +
> +/ {
> + model = "MediaTek MT8186 evaluation board";
> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> new file mode 100644
> index 000000000000..aa45c75b18c7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -0,0 +1,356 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8186";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clk13m: oscillator0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <13000000>;
> + clock-output-names = "clk13m";
> + };
> +
> + clk26m: oscillator1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk32k: oscillator2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + clock-output-names = "clk32k";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0600>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0700>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + cpuoff_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1600>;
> + };
> +
> + cpuoff_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1400>;
> + };
> +
> + clusteroff_l: cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <2100>;
> + };
> +
> + clusteroff_b: cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <1900>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <13000000>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #redistributor-regions = <1>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, // distributor
> + <0 0x0c040000 0 0x200000>; // redistributor
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8186-wdt",
> + "mediatek,mt6589-wdt";
> + mediatek,disable-extrst;
> + reg = <0 0x10007000 0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> + systimer: timer@10017000 {
> + compatible = "mediatek,mt8186-timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk13m>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11018000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8186-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg", "ahb_clk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8186-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: t-phy@11c80000 {
> + compatible = "mediatek,mt8186-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x11c80000 0x1000>;
> +
> + u2port1: usb2-phy1@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> +
> + u3port1: usb3-phy1@700 {
> + reg = <0x700 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + u3phy1: t-phy@11ca0000 {
> + compatible = "mediatek,mt8186-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> +
> + u2port0: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,discth = <0x8>;
> + };
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-03-29 14:56 ` Matthias Brugger
0 siblings, 0 replies; 43+ messages in thread
From: Matthias Brugger @ 2022-03-29 14:56 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
On 11/03/2022 14:07, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> Add basic chip support for Mediatek MT8186.
>
Thanks for your patch. I would love to wait a bit longer to see if we can get
the clock driver accepted. This way we could get rid of all the dummy clocks
defined in here.
Please send a new version once the clock driver is accepeted by Stephen, or ping
this series in a few month.
Thanks,
Matthias
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++
> 3 files changed, 381 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 8c1e18032f9f..d32fdcf9afc6 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> new file mode 100644
> index 000000000000..eb23d1f19f87
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +#include "mt8186.dtsi"
> +
> +/ {
> + model = "MediaTek MT8186 evaluation board";
> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> new file mode 100644
> index 000000000000..aa45c75b18c7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -0,0 +1,356 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8186";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clk13m: oscillator0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <13000000>;
> + clock-output-names = "clk13m";
> + };
> +
> + clk26m: oscillator1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk32k: oscillator2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + clock-output-names = "clk32k";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0600>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0700>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + cpuoff_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1600>;
> + };
> +
> + cpuoff_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1400>;
> + };
> +
> + clusteroff_l: cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <2100>;
> + };
> +
> + clusteroff_b: cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <1900>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <13000000>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #redistributor-regions = <1>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, // distributor
> + <0 0x0c040000 0 0x200000>; // redistributor
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8186-wdt",
> + "mediatek,mt6589-wdt";
> + mediatek,disable-extrst;
> + reg = <0 0x10007000 0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> + systimer: timer@10017000 {
> + compatible = "mediatek,mt8186-timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk13m>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11018000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8186-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg", "ahb_clk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8186-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: t-phy@11c80000 {
> + compatible = "mediatek,mt8186-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x11c80000 0x1000>;
> +
> + u2port1: usb2-phy1@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> +
> + u3port1: usb3-phy1@700 {
> + reg = <0x700 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + u3phy1: t-phy@11ca0000 {
> + compatible = "mediatek,mt8186-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> +
> + u2port0: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,discth = <0x8>;
> + };
> + };
> + };
> +};
_______________________________________________
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-03-29 14:56 ` Matthias Brugger
0 siblings, 0 replies; 43+ messages in thread
From: Matthias Brugger @ 2022-03-29 14:56 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
On 11/03/2022 14:07, Allen-KH Cheng wrote:
> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>
> Add basic chip support for Mediatek MT8186.
>
Thanks for your patch. I would love to wait a bit longer to see if we can get
the clock driver accepted. This way we could get rid of all the dummy clocks
defined in here.
Please send a new version once the clock driver is accepeted by Stephen, or ping
this series in a few month.
Thanks,
Matthias
> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 ++++++++++++++++++++
> 3 files changed, 381 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 8c1e18032f9f..d32fdcf9afc6 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> new file mode 100644
> index 000000000000..eb23d1f19f87
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +/dts-v1/;
> +#include "mt8186.dtsi"
> +
> +/ {
> + model = "MediaTek MT8186 evaluation board";
> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> new file mode 100644
> index 000000000000..aa45c75b18c7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -0,0 +1,356 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8186";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clk13m: oscillator0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <13000000>;
> + clock-output-names = "clk13m";
> + };
> +
> + clk26m: oscillator1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk32k: oscillator2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32000>;
> + clock-output-names = "clk32k";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0000>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0100>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0200>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0300>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu4: cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0400>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu5: cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55", "arm,armv8";
> + reg = <0x0500>;
> + enable-method = "psci";
> + clock-frequency = <2000000000>;
> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> + next-level-cache = <&l2_0>;
> + };
> +
> + cpu6: cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0600>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu7: cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a75", "arm,armv8";
> + reg = <0x0700>;
> + enable-method = "psci";
> + clock-frequency = <2050000000>;
> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> + next-level-cache = <&l2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> +
> + core5 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> +
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + cpuoff_l: cpu-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1600>;
> + };
> +
> + cpuoff_b: cpu-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <1400>;
> + };
> +
> + clusteroff_l: cluster-off-l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <2100>;
> + };
> +
> + clusteroff_b: cluster-off-b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010001>;
> + local-timer-stop;
> + entry-latency-us = <100>;
> + exit-latency-us = <250>;
> + min-residency-us = <1900>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + next-level-cache = <&l3_0>;
> + };
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <13000000>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #redistributor-regions = <1>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, // distributor
> + <0 0x0c040000 0 0x200000>; // redistributor
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8186-wdt",
> + "mediatek,mt6589-wdt";
> + mediatek,disable-extrst;
> + reg = <0 0x10007000 0 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> + systimer: timer@10017000 {
> + compatible = "mediatek,mt8186-timer",
> + "mediatek,mt6765-timer";
> + reg = <0 0x10017000 0 0x1000>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk13m>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + uart2: serial@11018000 {
> + compatible = "mediatek,mt8186-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8186-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg", "ahb_clk";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8186-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: t-phy@11c80000 {
> + compatible = "mediatek,mt8186-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x11c80000 0x1000>;
> +
> + u2port1: usb2-phy1@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> +
> + u3port1: usb3-phy1@700 {
> + reg = <0x700 0x900>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + u3phy1: t-phy@11ca0000 {
> + compatible = "mediatek,mt8186-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> +
> + u2port0: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,discth = <0x8>;
> + };
> + };
> + };
> +};
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-03-29 14:56 ` Matthias Brugger
@ 2022-03-30 7:34 ` allen-kh.cheng
-1 siblings, 0 replies; 43+ messages in thread
From: allen-kh.cheng @ 2022-03-30 7:34 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Matthias,
On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
>
> On 11/03/2022 14:07, Allen-KH Cheng wrote:
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > Add basic chip support for Mediatek MT8186.
> >
>
> Thanks for your patch. I would love to wait a bit longer to see if we
> can get
> the clock driver accepted. This way we could get rid of all the dummy
> clocks
> defined in here.
>
> Please send a new version once the clock driver is accepeted by
> Stephen, or ping
> this series in a few month.
>
> Thanks,
> Matthias
>
Sure, that's great.
I will send a new version after the clock driver is accepted.
Thanks,
Allen
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
> > ++++++++++++++++++++
> > 3 files changed, 381 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 8c1e18032f9f..d32fdcf9afc6 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > kodama-sku32.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > new file mode 100644
> > index 000000000000..eb23d1f19f87
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > @@ -0,0 +1,24 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +/dts-v1/;
> > +#include "mt8186.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT8186 evaluation board";
> > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x80000000>;
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > new file mode 100644
> > index 000000000000..aa45c75b18c7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -0,0 +1,356 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> > + */
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/phy/phy.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt8186";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + clk13m: oscillator0 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <13000000>;
> > + clock-output-names = "clk13m";
> > + };
> > +
> > + clk26m: oscillator1 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <26000000>;
> > + clock-output-names = "clk26m";
> > + };
> > +
> > + clk32k: oscillator2 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32000>;
> > + clock-output-names = "clk32k";
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@000 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0000>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu1: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0100>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0200>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu3: cpu@300 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0300>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu4: cpu@400 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0400>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu5: cpu@500 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0500>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu6: cpu@600 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0600>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu7: cpu@700 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0700>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > +
> > + core2 {
> > + cpu = <&cpu2>;
> > + };
> > +
> > + core3 {
> > + cpu = <&cpu3>;
> > + };
> > +
> > + core4 {
> > + cpu = <&cpu4>;
> > + };
> > +
> > + core5 {
> > + cpu = <&cpu5>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu6>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu7>;
> > + };
> > + };
> > + };
> > +
> > + idle-states {
> > + entry-method = "arm,psci";
> > +
> > + cpuoff_l: cpu-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1600>;
> > + };
> > +
> > + cpuoff_b: cpu-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1400>;
> > + };
> > +
> > + clusteroff_l: cluster-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <2100>;
> > + };
> > +
> > + clusteroff_b: cluster-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <1900>;
> > + };
> > + };
> > +
> > + l2_0: l2-cache0 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l2_1: l2-cache1 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l3_0: l3-cache {
> > + compatible = "cache";
> > + };
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + timer: timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + clock-frequency = <13000000>;
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + gic: interrupt-controller@c000000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + #redistributor-regions = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + reg = <0 0x0c000000 0 0x40000>, // distributor
> > + <0 0x0c040000 0 0x200000>; //
> > redistributor
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + watchdog: watchdog@10007000 {
> > + compatible = "mediatek,mt8186-wdt",
> > + "mediatek,mt6589-wdt";
> > + mediatek,disable-extrst;
> > + reg = <0 0x10007000 0 0x1000>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + systimer: timer@10017000 {
> > + compatible = "mediatek,mt8186-timer",
> > + "mediatek,mt6765-timer";
> > + reg = <0 0x10017000 0 0x1000>;
> > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk13m>;
> > + };
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x1000>;
> > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x1000>;
> > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11018000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11018000 0 0x1000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + mmc0: mmc@11230000 {
> > + compatible = "mediatek,mt8186-mmc",
> > + "mediatek,mt8183-mmc";
> > + reg = <0 0x11230000 0 0x1000>,
> > + <0 0x11cd0000 0 0x1000>;
> > + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
> > + <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg",
> > "ahb_clk";
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@11240000 {
> > + compatible = "mediatek,mt8186-mmc",
> > + "mediatek,mt8183-mmc";
> > + reg = <0 0x11240000 0 0x1000>,
> > + <0 0x11c90000 0 0x1000>;
> > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg";
> > + status = "disabled";
> > + };
> > +
> > + u3phy0: t-phy@11c80000 {
> > + compatible = "mediatek,mt8186-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x0 0x11c80000 0x1000>;
> > +
> > + u2port1: usb2-phy1@0 {
> > + reg = <0x0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + };
> > +
> > + u3port1: usb3-phy1@700 {
> > + reg = <0x700 0x900>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + };
> > + };
> > +
> > + u3phy1: t-phy@11ca0000 {
> > + compatible = "mediatek,mt8186-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> > +
> > + u2port0: usb-phy@0 {
> > + reg = <0x0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + mediatek,discth = <0x8>;
> > + };
> > + };
> > + };
> > +};
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-03-30 7:34 ` allen-kh.cheng
0 siblings, 0 replies; 43+ messages in thread
From: allen-kh.cheng @ 2022-03-30 7:34 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Matthias,
On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
>
> On 11/03/2022 14:07, Allen-KH Cheng wrote:
> > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> >
> > Add basic chip support for Mediatek MT8186.
> >
>
> Thanks for your patch. I would love to wait a bit longer to see if we
> can get
> the clock driver accepted. This way we could get rid of all the dummy
> clocks
> defined in here.
>
> Please send a new version once the clock driver is accepeted by
> Stephen, or ping
> this series in a few month.
>
> Thanks,
> Matthias
>
Sure, that's great.
I will send a new version after the clock driver is accepted.
Thanks,
Allen
> > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
> > ++++++++++++++++++++
> > 3 files changed, 381 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 8c1e18032f9f..d32fdcf9afc6 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > kodama-sku32.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > new file mode 100644
> > index 000000000000..eb23d1f19f87
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > @@ -0,0 +1,24 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +/dts-v1/;
> > +#include "mt8186.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT8186 evaluation board";
> > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x80000000>;
> > + };
> > +};
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > new file mode 100644
> > index 000000000000..aa45c75b18c7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > @@ -0,0 +1,356 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> > + */
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/phy/phy.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt8186";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + clk13m: oscillator0 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <13000000>;
> > + clock-output-names = "clk13m";
> > + };
> > +
> > + clk26m: oscillator1 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <26000000>;
> > + clock-output-names = "clk26m";
> > + };
> > +
> > + clk32k: oscillator2 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32000>;
> > + clock-output-names = "clk32k";
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@000 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0000>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu1: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0100>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0200>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu3: cpu@300 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0300>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu4: cpu@400 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0400>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu5: cpu@500 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a55", "arm,armv8";
> > + reg = <0x0500>;
> > + enable-method = "psci";
> > + clock-frequency = <2000000000>;
> > + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
> > + next-level-cache = <&l2_0>;
> > + };
> > +
> > + cpu6: cpu@600 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0600>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu7: cpu@700 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a75", "arm,armv8";
> > + reg = <0x0700>;
> > + enable-method = "psci";
> > + clock-frequency = <2050000000>;
> > + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
> > + next-level-cache = <&l2_1>;
> > + };
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > +
> > + core2 {
> > + cpu = <&cpu2>;
> > + };
> > +
> > + core3 {
> > + cpu = <&cpu3>;
> > + };
> > +
> > + core4 {
> > + cpu = <&cpu4>;
> > + };
> > +
> > + core5 {
> > + cpu = <&cpu5>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu6>;
> > + };
> > +
> > + core1 {
> > + cpu = <&cpu7>;
> > + };
> > + };
> > + };
> > +
> > + idle-states {
> > + entry-method = "arm,psci";
> > +
> > + cpuoff_l: cpu-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1600>;
> > + };
> > +
> > + cpuoff_b: cpu-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x00010001>;
> > + local-timer-stop;
> > + entry-latency-us = <50>;
> > + exit-latency-us = <100>;
> > + min-residency-us = <1400>;
> > + };
> > +
> > + clusteroff_l: cluster-off-l {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <2100>;
> > + };
> > +
> > + clusteroff_b: cluster-off-b {
> > + compatible = "arm,idle-state";
> > + arm,psci-suspend-param = <0x01010001>;
> > + local-timer-stop;
> > + entry-latency-us = <100>;
> > + exit-latency-us = <250>;
> > + min-residency-us = <1900>;
> > + };
> > + };
> > +
> > + l2_0: l2-cache0 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l2_1: l2-cache1 {
> > + compatible = "cache";
> > + next-level-cache = <&l3_0>;
> > + };
> > +
> > + l3_0: l3-cache {
> > + compatible = "cache";
> > + };
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + timer: timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > + clock-frequency = <13000000>;
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + gic: interrupt-controller@c000000 {
> > + compatible = "arm,gic-v3";
> > + #interrupt-cells = <3>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + #redistributor-regions = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + reg = <0 0x0c000000 0 0x40000>, // distributor
> > + <0 0x0c040000 0 0x200000>; //
> > redistributor
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + watchdog: watchdog@10007000 {
> > + compatible = "mediatek,mt8186-wdt",
> > + "mediatek,mt6589-wdt";
> > + mediatek,disable-extrst;
> > + reg = <0 0x10007000 0 0x1000>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + systimer: timer@10017000 {
> > + compatible = "mediatek,mt8186-timer",
> > + "mediatek,mt6765-timer";
> > + reg = <0 0x10017000 0 0x1000>;
> > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk13m>;
> > + };
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x1000>;
> > + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x1000>;
> > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11018000 {
> > + compatible = "mediatek,mt8186-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11018000 0 0x1000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + mmc0: mmc@11230000 {
> > + compatible = "mediatek,mt8186-mmc",
> > + "mediatek,mt8183-mmc";
> > + reg = <0 0x11230000 0 0x1000>,
> > + <0 0x11cd0000 0 0x1000>;
> > + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
> > + <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg",
> > "ahb_clk";
> > + status = "disabled";
> > + };
> > +
> > + mmc1: mmc@11240000 {
> > + compatible = "mediatek,mt8186-mmc",
> > + "mediatek,mt8183-mmc";
> > + reg = <0 0x11240000 0 0x1000>,
> > + <0 0x11c90000 0 0x1000>;
> > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> > + clock-names = "source", "hclk", "source_cg";
> > + status = "disabled";
> > + };
> > +
> > + u3phy0: t-phy@11c80000 {
> > + compatible = "mediatek,mt8186-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x0 0x11c80000 0x1000>;
> > +
> > + u2port1: usb2-phy1@0 {
> > + reg = <0x0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + };
> > +
> > + u3port1: usb3-phy1@700 {
> > + reg = <0x700 0x900>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + };
> > + };
> > +
> > + u3phy1: t-phy@11ca0000 {
> > + compatible = "mediatek,mt8186-tphy",
> > + "mediatek,generic-tphy-v2";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> > +
> > + u2port0: usb-phy@0 {
> > + reg = <0x0 0x700>;
> > + clocks = <&clk26m>;
> > + clock-names = "ref";
> > + #phy-cells = <1>;
> > + mediatek,discth = <0x8>;
> > + };
> > + };
> > + };
> > +};
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
2022-03-11 15:50 ` Rob Herring
(?)
@ 2022-03-30 11:49 ` Daniel Lezcano
-1 siblings, 0 replies; 43+ messages in thread
From: Daniel Lezcano @ 2022-03-30 11:49 UTC (permalink / raw)
To: Rob Herring, Allen-KH Cheng
Cc: hsinyi, Thomas Gleixner, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Wim Van Sebroeck, Matthias Brugger, Kishon Vijay Abraham I
On 11/03/2022 16:50, Rob Herring wrote:
> On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
>> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>
>> This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
>> Platform.
>>
>> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>> ---
>> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Acked-by: Rob Herring <robh@kernel.org>
Applied, thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-03-30 11:49 ` Daniel Lezcano
0 siblings, 0 replies; 43+ messages in thread
From: Daniel Lezcano @ 2022-03-30 11:49 UTC (permalink / raw)
To: Rob Herring, Allen-KH Cheng
Cc: hsinyi, Thomas Gleixner, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Wim Van Sebroeck, Matthias Brugger, Kishon Vijay Abraham I
On 11/03/2022 16:50, Rob Herring wrote:
> On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
>> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>
>> This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
>> Platform.
>>
>> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>> ---
>> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Acked-by: Rob Herring <robh@kernel.org>
Applied, thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-03-30 11:49 ` Daniel Lezcano
0 siblings, 0 replies; 43+ messages in thread
From: Daniel Lezcano @ 2022-03-30 11:49 UTC (permalink / raw)
To: Rob Herring, Allen-KH Cheng
Cc: hsinyi, Thomas Gleixner, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Wim Van Sebroeck, Matthias Brugger, Kishon Vijay Abraham I
On 11/03/2022 16:50, Rob Herring wrote:
> On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
>> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>
>> This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
>> Platform.
>>
>> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>> ---
>> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Acked-by: Rob Herring <robh@kernel.org>
Applied, thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-03-30 7:34 ` allen-kh.cheng
(?)
@ 2022-04-26 10:28 ` Matthias Brugger
-1 siblings, 0 replies; 43+ messages in thread
From: Matthias Brugger @ 2022-04-26 10:28 UTC (permalink / raw)
To: allen-kh.cheng, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Allen,
On 30/03/2022 09:34, allen-kh.cheng wrote:
> Hi Matthias,
>
> On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
>>
>> On 11/03/2022 14:07, Allen-KH Cheng wrote:
>>> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>>
>>> Add basic chip support for Mediatek MT8186.
>>>
>>
>> Thanks for your patch. I would love to wait a bit longer to see if we
>> can get
>> the clock driver accepted. This way we could get rid of all the dummy
>> clocks
>> defined in here.
>>
>> Please send a new version once the clock driver is accepeted by
>> Stephen, or ping
>> this series in a few month.
>>
>> Thanks,
>> Matthias
>>
>
> Sure, that's great.
>
> I will send a new version after the clock driver is accepted.
>
I've seen that the clock driver got accepted. Can you please send a new patch
adding the correct clocks to the nodes?
Thanks a lot.
Matthias
> Thanks,
> Allen
>
>>> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>> ---
>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
>>> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
>>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
>>> ++++++++++++++++++++
>>> 3 files changed, 381 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
>>> b/arch/arm64/boot/dts/mediatek/Makefile
>>> index 8c1e18032f9f..d32fdcf9afc6 100644
>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
>>> kodama-sku32.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> new file mode 100644
>>> index 000000000000..eb23d1f19f87
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> @@ -0,0 +1,24 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2022 MediaTek Inc.
>>> + */
>>> +/dts-v1/;
>>> +#include "mt8186.dtsi"
>>> +
>>> +/ {
>>> + model = "MediaTek MT8186 evaluation board";
>>> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
>>> +
>>> + aliases {
>>> + serial0 = &uart0;
>>> + };
>>> +
>>> + chosen {
>>> + stdout-path = "serial0:921600n8";
>>> + };
>>> +
>>> + memory {
>>> + device_type = "memory";
>>> + reg = <0 0x40000000 0 0x80000000>;
>>> + };
>>> +};
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> new file mode 100644
>>> index 000000000000..aa45c75b18c7
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> @@ -0,0 +1,356 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2022 MediaTek Inc.
>>> + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
>>> + */
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/phy/phy.h>
>>> +
>>> +/ {
>>> + compatible = "mediatek,mt8186";
>>> + interrupt-parent = <&gic>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + clk13m: oscillator0 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <13000000>;
>>> + clock-output-names = "clk13m";
>>> + };
>>> +
>>> + clk26m: oscillator1 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <26000000>;
>>> + clock-output-names = "clk26m";
>>> + };
>>> +
>>> + clk32k: oscillator2 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <32000>;
>>> + clock-output-names = "clk32k";
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu0: cpu@000 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0000>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu1: cpu@100 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0100>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu2: cpu@200 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0200>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu3: cpu@300 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0300>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu4: cpu@400 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0400>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu5: cpu@500 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0500>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu6: cpu@600 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a75", "arm,armv8";
>>> + reg = <0x0600>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2050000000>;
>>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
>>> + next-level-cache = <&l2_1>;
>>> + };
>>> +
>>> + cpu7: cpu@700 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a75", "arm,armv8";
>>> + reg = <0x0700>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2050000000>;
>>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
>>> + next-level-cache = <&l2_1>;
>>> + };
>>> +
>>> + cpu-map {
>>> + cluster0 {
>>> + core0 {
>>> + cpu = <&cpu0>;
>>> + };
>>> +
>>> + core1 {
>>> + cpu = <&cpu1>;
>>> + };
>>> +
>>> + core2 {
>>> + cpu = <&cpu2>;
>>> + };
>>> +
>>> + core3 {
>>> + cpu = <&cpu3>;
>>> + };
>>> +
>>> + core4 {
>>> + cpu = <&cpu4>;
>>> + };
>>> +
>>> + core5 {
>>> + cpu = <&cpu5>;
>>> + };
>>> + };
>>> +
>>> + cluster1 {
>>> + core0 {
>>> + cpu = <&cpu6>;
>>> + };
>>> +
>>> + core1 {
>>> + cpu = <&cpu7>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + idle-states {
>>> + entry-method = "arm,psci";
>>> +
>>> + cpuoff_l: cpu-off-l {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x00010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <50>;
>>> + exit-latency-us = <100>;
>>> + min-residency-us = <1600>;
>>> + };
>>> +
>>> + cpuoff_b: cpu-off-b {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x00010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <50>;
>>> + exit-latency-us = <100>;
>>> + min-residency-us = <1400>;
>>> + };
>>> +
>>> + clusteroff_l: cluster-off-l {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x01010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <100>;
>>> + exit-latency-us = <250>;
>>> + min-residency-us = <2100>;
>>> + };
>>> +
>>> + clusteroff_b: cluster-off-b {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x01010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <100>;
>>> + exit-latency-us = <250>;
>>> + min-residency-us = <1900>;
>>> + };
>>> + };
>>> +
>>> + l2_0: l2-cache0 {
>>> + compatible = "cache";
>>> + next-level-cache = <&l3_0>;
>>> + };
>>> +
>>> + l2_1: l2-cache1 {
>>> + compatible = "cache";
>>> + next-level-cache = <&l3_0>;
>>> + };
>>> +
>>> + l3_0: l3-cache {
>>> + compatible = "cache";
>>> + };
>>> + };
>>> +
>>> + psci {
>>> + compatible = "arm,psci-1.0";
>>> + method = "smc";
>>> + };
>>> +
>>> + timer: timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>>> + clock-frequency = <13000000>;
>>> + };
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + gic: interrupt-controller@c000000 {
>>> + compatible = "arm,gic-v3";
>>> + #interrupt-cells = <3>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + #redistributor-regions = <1>;
>>> + interrupt-parent = <&gic>;
>>> + interrupt-controller;
>>> + reg = <0 0x0c000000 0 0x40000>, // distributor
>>> + <0 0x0c040000 0 0x200000>; //
>>> redistributor
>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> + };
>>> +
>>> + watchdog: watchdog@10007000 {
>>> + compatible = "mediatek,mt8186-wdt",
>>> + "mediatek,mt6589-wdt";
>>> + mediatek,disable-extrst;
>>> + reg = <0 0x10007000 0 0x1000>;
>>> + #reset-cells = <1>;
>>> + };
>>> +
>>> + systimer: timer@10017000 {
>>> + compatible = "mediatek,mt8186-timer",
>>> + "mediatek,mt6765-timer";
>>> + reg = <0 0x10017000 0 0x1000>;
>>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk13m>;
>>> + };
>>> +
>>> + uart0: serial@11002000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11002000 0 0x1000>;
>>> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + };
>>> +
>>> + uart1: serial@11003000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11003000 0 0x1000>;
>>> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart2: serial@11018000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11018000 0 0x1000>;
>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + mmc0: mmc@11230000 {
>>> + compatible = "mediatek,mt8186-mmc",
>>> + "mediatek,mt8183-mmc";
>>> + reg = <0 0x11230000 0 0x1000>,
>>> + <0 0x11cd0000 0 0x1000>;
>>> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
>>> + <&clk26m>;
>>> + clock-names = "source", "hclk", "source_cg",
>>> "ahb_clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + mmc1: mmc@11240000 {
>>> + compatible = "mediatek,mt8186-mmc",
>>> + "mediatek,mt8183-mmc";
>>> + reg = <0 0x11240000 0 0x1000>,
>>> + <0 0x11c90000 0 0x1000>;
>>> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
>>> + clock-names = "source", "hclk", "source_cg";
>>> + status = "disabled";
>>> + };
>>> +
>>> + u3phy0: t-phy@11c80000 {
>>> + compatible = "mediatek,mt8186-tphy",
>>> + "mediatek,generic-tphy-v2";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x11c80000 0x1000>;
>>> +
>>> + u2port1: usb2-phy1@0 {
>>> + reg = <0x0 0x700>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + };
>>> +
>>> + u3port1: usb3-phy1@700 {
>>> + reg = <0x700 0x900>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + };
>>> + };
>>> +
>>> + u3phy1: t-phy@11ca0000 {
>>> + compatible = "mediatek,mt8186-tphy",
>>> + "mediatek,generic-tphy-v2";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x11ca0000 0x1000>;
>>> +
>>> + u2port0: usb-phy@0 {
>>> + reg = <0x0 0x700>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + mediatek,discth = <0x8>;
>>> + };
>>> + };
>>> + };
>>> +};
>
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-04-26 10:28 ` Matthias Brugger
0 siblings, 0 replies; 43+ messages in thread
From: Matthias Brugger @ 2022-04-26 10:28 UTC (permalink / raw)
To: allen-kh.cheng, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Allen,
On 30/03/2022 09:34, allen-kh.cheng wrote:
> Hi Matthias,
>
> On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
>>
>> On 11/03/2022 14:07, Allen-KH Cheng wrote:
>>> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>>
>>> Add basic chip support for Mediatek MT8186.
>>>
>>
>> Thanks for your patch. I would love to wait a bit longer to see if we
>> can get
>> the clock driver accepted. This way we could get rid of all the dummy
>> clocks
>> defined in here.
>>
>> Please send a new version once the clock driver is accepeted by
>> Stephen, or ping
>> this series in a few month.
>>
>> Thanks,
>> Matthias
>>
>
> Sure, that's great.
>
> I will send a new version after the clock driver is accepted.
>
I've seen that the clock driver got accepted. Can you please send a new patch
adding the correct clocks to the nodes?
Thanks a lot.
Matthias
> Thanks,
> Allen
>
>>> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>> ---
>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
>>> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
>>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
>>> ++++++++++++++++++++
>>> 3 files changed, 381 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
>>> b/arch/arm64/boot/dts/mediatek/Makefile
>>> index 8c1e18032f9f..d32fdcf9afc6 100644
>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
>>> kodama-sku32.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> new file mode 100644
>>> index 000000000000..eb23d1f19f87
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> @@ -0,0 +1,24 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2022 MediaTek Inc.
>>> + */
>>> +/dts-v1/;
>>> +#include "mt8186.dtsi"
>>> +
>>> +/ {
>>> + model = "MediaTek MT8186 evaluation board";
>>> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
>>> +
>>> + aliases {
>>> + serial0 = &uart0;
>>> + };
>>> +
>>> + chosen {
>>> + stdout-path = "serial0:921600n8";
>>> + };
>>> +
>>> + memory {
>>> + device_type = "memory";
>>> + reg = <0 0x40000000 0 0x80000000>;
>>> + };
>>> +};
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> new file mode 100644
>>> index 000000000000..aa45c75b18c7
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> @@ -0,0 +1,356 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2022 MediaTek Inc.
>>> + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
>>> + */
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/phy/phy.h>
>>> +
>>> +/ {
>>> + compatible = "mediatek,mt8186";
>>> + interrupt-parent = <&gic>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + clk13m: oscillator0 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <13000000>;
>>> + clock-output-names = "clk13m";
>>> + };
>>> +
>>> + clk26m: oscillator1 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <26000000>;
>>> + clock-output-names = "clk26m";
>>> + };
>>> +
>>> + clk32k: oscillator2 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <32000>;
>>> + clock-output-names = "clk32k";
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu0: cpu@000 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0000>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu1: cpu@100 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0100>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu2: cpu@200 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0200>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu3: cpu@300 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0300>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu4: cpu@400 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0400>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu5: cpu@500 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0500>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu6: cpu@600 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a75", "arm,armv8";
>>> + reg = <0x0600>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2050000000>;
>>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
>>> + next-level-cache = <&l2_1>;
>>> + };
>>> +
>>> + cpu7: cpu@700 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a75", "arm,armv8";
>>> + reg = <0x0700>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2050000000>;
>>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
>>> + next-level-cache = <&l2_1>;
>>> + };
>>> +
>>> + cpu-map {
>>> + cluster0 {
>>> + core0 {
>>> + cpu = <&cpu0>;
>>> + };
>>> +
>>> + core1 {
>>> + cpu = <&cpu1>;
>>> + };
>>> +
>>> + core2 {
>>> + cpu = <&cpu2>;
>>> + };
>>> +
>>> + core3 {
>>> + cpu = <&cpu3>;
>>> + };
>>> +
>>> + core4 {
>>> + cpu = <&cpu4>;
>>> + };
>>> +
>>> + core5 {
>>> + cpu = <&cpu5>;
>>> + };
>>> + };
>>> +
>>> + cluster1 {
>>> + core0 {
>>> + cpu = <&cpu6>;
>>> + };
>>> +
>>> + core1 {
>>> + cpu = <&cpu7>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + idle-states {
>>> + entry-method = "arm,psci";
>>> +
>>> + cpuoff_l: cpu-off-l {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x00010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <50>;
>>> + exit-latency-us = <100>;
>>> + min-residency-us = <1600>;
>>> + };
>>> +
>>> + cpuoff_b: cpu-off-b {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x00010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <50>;
>>> + exit-latency-us = <100>;
>>> + min-residency-us = <1400>;
>>> + };
>>> +
>>> + clusteroff_l: cluster-off-l {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x01010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <100>;
>>> + exit-latency-us = <250>;
>>> + min-residency-us = <2100>;
>>> + };
>>> +
>>> + clusteroff_b: cluster-off-b {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x01010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <100>;
>>> + exit-latency-us = <250>;
>>> + min-residency-us = <1900>;
>>> + };
>>> + };
>>> +
>>> + l2_0: l2-cache0 {
>>> + compatible = "cache";
>>> + next-level-cache = <&l3_0>;
>>> + };
>>> +
>>> + l2_1: l2-cache1 {
>>> + compatible = "cache";
>>> + next-level-cache = <&l3_0>;
>>> + };
>>> +
>>> + l3_0: l3-cache {
>>> + compatible = "cache";
>>> + };
>>> + };
>>> +
>>> + psci {
>>> + compatible = "arm,psci-1.0";
>>> + method = "smc";
>>> + };
>>> +
>>> + timer: timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>>> + clock-frequency = <13000000>;
>>> + };
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + gic: interrupt-controller@c000000 {
>>> + compatible = "arm,gic-v3";
>>> + #interrupt-cells = <3>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + #redistributor-regions = <1>;
>>> + interrupt-parent = <&gic>;
>>> + interrupt-controller;
>>> + reg = <0 0x0c000000 0 0x40000>, // distributor
>>> + <0 0x0c040000 0 0x200000>; //
>>> redistributor
>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> + };
>>> +
>>> + watchdog: watchdog@10007000 {
>>> + compatible = "mediatek,mt8186-wdt",
>>> + "mediatek,mt6589-wdt";
>>> + mediatek,disable-extrst;
>>> + reg = <0 0x10007000 0 0x1000>;
>>> + #reset-cells = <1>;
>>> + };
>>> +
>>> + systimer: timer@10017000 {
>>> + compatible = "mediatek,mt8186-timer",
>>> + "mediatek,mt6765-timer";
>>> + reg = <0 0x10017000 0 0x1000>;
>>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk13m>;
>>> + };
>>> +
>>> + uart0: serial@11002000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11002000 0 0x1000>;
>>> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + };
>>> +
>>> + uart1: serial@11003000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11003000 0 0x1000>;
>>> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart2: serial@11018000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11018000 0 0x1000>;
>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + mmc0: mmc@11230000 {
>>> + compatible = "mediatek,mt8186-mmc",
>>> + "mediatek,mt8183-mmc";
>>> + reg = <0 0x11230000 0 0x1000>,
>>> + <0 0x11cd0000 0 0x1000>;
>>> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
>>> + <&clk26m>;
>>> + clock-names = "source", "hclk", "source_cg",
>>> "ahb_clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + mmc1: mmc@11240000 {
>>> + compatible = "mediatek,mt8186-mmc",
>>> + "mediatek,mt8183-mmc";
>>> + reg = <0 0x11240000 0 0x1000>,
>>> + <0 0x11c90000 0 0x1000>;
>>> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
>>> + clock-names = "source", "hclk", "source_cg";
>>> + status = "disabled";
>>> + };
>>> +
>>> + u3phy0: t-phy@11c80000 {
>>> + compatible = "mediatek,mt8186-tphy",
>>> + "mediatek,generic-tphy-v2";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x11c80000 0x1000>;
>>> +
>>> + u2port1: usb2-phy1@0 {
>>> + reg = <0x0 0x700>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + };
>>> +
>>> + u3port1: usb3-phy1@700 {
>>> + reg = <0x700 0x900>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + };
>>> + };
>>> +
>>> + u3phy1: t-phy@11ca0000 {
>>> + compatible = "mediatek,mt8186-tphy",
>>> + "mediatek,generic-tphy-v2";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x11ca0000 0x1000>;
>>> +
>>> + u2port0: usb-phy@0 {
>>> + reg = <0x0 0x700>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + mediatek,discth = <0x8>;
>>> + };
>>> + };
>>> + };
>>> +};
>
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-04-26 10:28 ` Matthias Brugger
0 siblings, 0 replies; 43+ messages in thread
From: Matthias Brugger @ 2022-04-26 10:28 UTC (permalink / raw)
To: allen-kh.cheng, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Allen,
On 30/03/2022 09:34, allen-kh.cheng wrote:
> Hi Matthias,
>
> On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
>>
>> On 11/03/2022 14:07, Allen-KH Cheng wrote:
>>> From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>>
>>> Add basic chip support for Mediatek MT8186.
>>>
>>
>> Thanks for your patch. I would love to wait a bit longer to see if we
>> can get
>> the clock driver accepted. This way we could get rid of all the dummy
>> clocks
>> defined in here.
>>
>> Please send a new version once the clock driver is accepeted by
>> Stephen, or ping
>> this series in a few month.
>>
>> Thanks,
>> Matthias
>>
>
> Sure, that's great.
>
> I will send a new version after the clock driver is accepted.
>
I've seen that the clock driver got accepted. Can you please send a new patch
adding the correct clocks to the nodes?
Thanks a lot.
Matthias
> Thanks,
> Allen
>
>>> Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
>>> ---
>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
>>> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
>>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
>>> ++++++++++++++++++++
>>> 3 files changed, 381 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
>>> b/arch/arm64/boot/dts/mediatek/Makefile
>>> index 8c1e18032f9f..d32fdcf9afc6 100644
>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
>>> kodama-sku32.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> new file mode 100644
>>> index 000000000000..eb23d1f19f87
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
>>> @@ -0,0 +1,24 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2022 MediaTek Inc.
>>> + */
>>> +/dts-v1/;
>>> +#include "mt8186.dtsi"
>>> +
>>> +/ {
>>> + model = "MediaTek MT8186 evaluation board";
>>> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
>>> +
>>> + aliases {
>>> + serial0 = &uart0;
>>> + };
>>> +
>>> + chosen {
>>> + stdout-path = "serial0:921600n8";
>>> + };
>>> +
>>> + memory {
>>> + device_type = "memory";
>>> + reg = <0 0x40000000 0 0x80000000>;
>>> + };
>>> +};
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> new file mode 100644
>>> index 000000000000..aa45c75b18c7
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> @@ -0,0 +1,356 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2022 MediaTek Inc.
>>> + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
>>> + */
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/phy/phy.h>
>>> +
>>> +/ {
>>> + compatible = "mediatek,mt8186";
>>> + interrupt-parent = <&gic>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + clk13m: oscillator0 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <13000000>;
>>> + clock-output-names = "clk13m";
>>> + };
>>> +
>>> + clk26m: oscillator1 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <26000000>;
>>> + clock-output-names = "clk26m";
>>> + };
>>> +
>>> + clk32k: oscillator2 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <32000>;
>>> + clock-output-names = "clk32k";
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu0: cpu@000 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0000>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu1: cpu@100 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0100>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu2: cpu@200 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0200>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu3: cpu@300 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0300>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu4: cpu@400 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0400>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu5: cpu@500 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a55", "arm,armv8";
>>> + reg = <0x0500>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2000000000>;
>>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>;
>>> + next-level-cache = <&l2_0>;
>>> + };
>>> +
>>> + cpu6: cpu@600 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a75", "arm,armv8";
>>> + reg = <0x0600>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2050000000>;
>>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
>>> + next-level-cache = <&l2_1>;
>>> + };
>>> +
>>> + cpu7: cpu@700 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a75", "arm,armv8";
>>> + reg = <0x0700>;
>>> + enable-method = "psci";
>>> + clock-frequency = <2050000000>;
>>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>;
>>> + next-level-cache = <&l2_1>;
>>> + };
>>> +
>>> + cpu-map {
>>> + cluster0 {
>>> + core0 {
>>> + cpu = <&cpu0>;
>>> + };
>>> +
>>> + core1 {
>>> + cpu = <&cpu1>;
>>> + };
>>> +
>>> + core2 {
>>> + cpu = <&cpu2>;
>>> + };
>>> +
>>> + core3 {
>>> + cpu = <&cpu3>;
>>> + };
>>> +
>>> + core4 {
>>> + cpu = <&cpu4>;
>>> + };
>>> +
>>> + core5 {
>>> + cpu = <&cpu5>;
>>> + };
>>> + };
>>> +
>>> + cluster1 {
>>> + core0 {
>>> + cpu = <&cpu6>;
>>> + };
>>> +
>>> + core1 {
>>> + cpu = <&cpu7>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + idle-states {
>>> + entry-method = "arm,psci";
>>> +
>>> + cpuoff_l: cpu-off-l {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x00010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <50>;
>>> + exit-latency-us = <100>;
>>> + min-residency-us = <1600>;
>>> + };
>>> +
>>> + cpuoff_b: cpu-off-b {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x00010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <50>;
>>> + exit-latency-us = <100>;
>>> + min-residency-us = <1400>;
>>> + };
>>> +
>>> + clusteroff_l: cluster-off-l {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x01010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <100>;
>>> + exit-latency-us = <250>;
>>> + min-residency-us = <2100>;
>>> + };
>>> +
>>> + clusteroff_b: cluster-off-b {
>>> + compatible = "arm,idle-state";
>>> + arm,psci-suspend-param = <0x01010001>;
>>> + local-timer-stop;
>>> + entry-latency-us = <100>;
>>> + exit-latency-us = <250>;
>>> + min-residency-us = <1900>;
>>> + };
>>> + };
>>> +
>>> + l2_0: l2-cache0 {
>>> + compatible = "cache";
>>> + next-level-cache = <&l3_0>;
>>> + };
>>> +
>>> + l2_1: l2-cache1 {
>>> + compatible = "cache";
>>> + next-level-cache = <&l3_0>;
>>> + };
>>> +
>>> + l3_0: l3-cache {
>>> + compatible = "cache";
>>> + };
>>> + };
>>> +
>>> + psci {
>>> + compatible = "arm,psci-1.0";
>>> + method = "smc";
>>> + };
>>> +
>>> + timer: timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>>> + clock-frequency = <13000000>;
>>> + };
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + gic: interrupt-controller@c000000 {
>>> + compatible = "arm,gic-v3";
>>> + #interrupt-cells = <3>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + #redistributor-regions = <1>;
>>> + interrupt-parent = <&gic>;
>>> + interrupt-controller;
>>> + reg = <0 0x0c000000 0 0x40000>, // distributor
>>> + <0 0x0c040000 0 0x200000>; //
>>> redistributor
>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> + };
>>> +
>>> + watchdog: watchdog@10007000 {
>>> + compatible = "mediatek,mt8186-wdt",
>>> + "mediatek,mt6589-wdt";
>>> + mediatek,disable-extrst;
>>> + reg = <0 0x10007000 0 0x1000>;
>>> + #reset-cells = <1>;
>>> + };
>>> +
>>> + systimer: timer@10017000 {
>>> + compatible = "mediatek,mt8186-timer",
>>> + "mediatek,mt6765-timer";
>>> + reg = <0 0x10017000 0 0x1000>;
>>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk13m>;
>>> + };
>>> +
>>> + uart0: serial@11002000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11002000 0 0x1000>;
>>> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + };
>>> +
>>> + uart1: serial@11003000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11003000 0 0x1000>;
>>> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart2: serial@11018000 {
>>> + compatible = "mediatek,mt8186-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11018000 0 0x1000>;
>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + mmc0: mmc@11230000 {
>>> + compatible = "mediatek,mt8186-mmc",
>>> + "mediatek,mt8183-mmc";
>>> + reg = <0 0x11230000 0 0x1000>,
>>> + <0 0x11cd0000 0 0x1000>;
>>> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>,
>>> + <&clk26m>;
>>> + clock-names = "source", "hclk", "source_cg",
>>> "ahb_clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + mmc1: mmc@11240000 {
>>> + compatible = "mediatek,mt8186-mmc",
>>> + "mediatek,mt8183-mmc";
>>> + reg = <0 0x11240000 0 0x1000>,
>>> + <0 0x11c90000 0 0x1000>;
>>> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>;
>>> + clock-names = "source", "hclk", "source_cg";
>>> + status = "disabled";
>>> + };
>>> +
>>> + u3phy0: t-phy@11c80000 {
>>> + compatible = "mediatek,mt8186-tphy",
>>> + "mediatek,generic-tphy-v2";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x11c80000 0x1000>;
>>> +
>>> + u2port1: usb2-phy1@0 {
>>> + reg = <0x0 0x700>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + };
>>> +
>>> + u3port1: usb3-phy1@700 {
>>> + reg = <0x700 0x900>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + };
>>> + };
>>> +
>>> + u3phy1: t-phy@11ca0000 {
>>> + compatible = "mediatek,mt8186-tphy",
>>> + "mediatek,generic-tphy-v2";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x11ca0000 0x1000>;
>>> +
>>> + u2port0: usb-phy@0 {
>>> + reg = <0x0 0x700>;
>>> + clocks = <&clk26m>;
>>> + clock-names = "ref";
>>> + #phy-cells = <1>;
>>> + mediatek,discth = <0x8>;
>>> + };
>>> + };
>>> + };
>>> +};
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
2022-04-26 10:28 ` Matthias Brugger
@ 2022-04-26 11:12 ` allen-kh.cheng
-1 siblings, 0 replies; 43+ messages in thread
From: allen-kh.cheng @ 2022-04-26 11:12 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Matthias,
On Tue, 2022-04-26 at 12:28 +0200, Matthias Brugger wrote:
> Hi Allen,
>
> On 30/03/2022 09:34, allen-kh.cheng wrote:
> > Hi Matthias,
> >
> > On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
> > >
> > > On 11/03/2022 14:07, Allen-KH Cheng wrote:
> > > > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > > >
> > > > Add basic chip support for Mediatek MT8186.
> > > >
> > >
> > > Thanks for your patch. I would love to wait a bit longer to see
> > > if we
> > > can get
> > > the clock driver accepted. This way we could get rid of all the
> > > dummy
> > > clocks
> > > defined in here.
> > >
> > > Please send a new version once the clock driver is accepeted by
> > > Stephen, or ping
> > > this series in a few month.
> > >
> > > Thanks,
> > > Matthias
> > >
> >
> > Sure, that's great.
> >
> > I will send a new version after the clock driver is accepted.
> >
>
> I've seen that the clock driver got accepted. Can you please send a
> new patch
> adding the correct clocks to the nodes?
>
> Thanks a lot.
> Matthias
>
Sure, I am going to prepare the PATCH.
I will send a new patch ASAP.
Thanks,
Allen
> > Thanks,
> > Allen
> >
> > > > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > > > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > > > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
> > > > ++++++++++++++++++++
> > > > 3 files changed, 381 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-
> > > > evb.dts
> > > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > > > b/arch/arm64/boot/dts/mediatek/Makefile
> > > > index 8c1e18032f9f..d32fdcf9afc6 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > > > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > > > @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > > > kodama-sku32.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > > > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > new file mode 100644
> > > > index 000000000000..eb23d1f19f87
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > @@ -0,0 +1,24 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + */
> > > > +/dts-v1/;
> > > > +#include "mt8186.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "MediaTek MT8186 evaluation board";
> > > > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > > > +
> > > > + aliases {
> > > > + serial0 = &uart0;
> > > > + };
> > > > +
> > > > + chosen {
> > > > + stdout-path = "serial0:921600n8";
> > > > + };
> > > > +
> > > > + memory {
> > > > + device_type = "memory";
> > > > + reg = <0 0x40000000 0 0x80000000>;
> > > > + };
> > > > +};
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > new file mode 100644
> > > > index 000000000000..aa45c75b18c7
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > @@ -0,0 +1,356 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> > > > + */
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +#include <dt-bindings/phy/phy.h>
> > > > +
> > > > +/ {
> > > > + compatible = "mediatek,mt8186";
> > > > + interrupt-parent = <&gic>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > +
> > > > + clk13m: oscillator0 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <13000000>;
> > > > + clock-output-names = "clk13m";
> > > > + };
> > > > +
> > > > + clk26m: oscillator1 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <26000000>;
> > > > + clock-output-names = "clk26m";
> > > > + };
> > > > +
> > > > + clk32k: oscillator2 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <32000>;
> > > > + clock-output-names = "clk32k";
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + cpu0: cpu@000 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0000>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu1: cpu@100 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0100>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu2: cpu@200 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0200>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu3: cpu@300 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0300>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu4: cpu@400 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0400>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu5: cpu@500 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0500>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu6: cpu@600 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a75",
> > > > "arm,armv8";
> > > > + reg = <0x0600>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2050000000>;
> > > > + cpu-idle-states = <&cpuoff_b
> > > > &clusteroff_b>;
> > > > + next-level-cache = <&l2_1>;
> > > > + };
> > > > +
> > > > + cpu7: cpu@700 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a75",
> > > > "arm,armv8";
> > > > + reg = <0x0700>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2050000000>;
> > > > + cpu-idle-states = <&cpuoff_b
> > > > &clusteroff_b>;
> > > > + next-level-cache = <&l2_1>;
> > > > + };
> > > > +
> > > > + cpu-map {
> > > > + cluster0 {
> > > > + core0 {
> > > > + cpu = <&cpu0>;
> > > > + };
> > > > +
> > > > + core1 {
> > > > + cpu = <&cpu1>;
> > > > + };
> > > > +
> > > > + core2 {
> > > > + cpu = <&cpu2>;
> > > > + };
> > > > +
> > > > + core3 {
> > > > + cpu = <&cpu3>;
> > > > + };
> > > > +
> > > > + core4 {
> > > > + cpu = <&cpu4>;
> > > > + };
> > > > +
> > > > + core5 {
> > > > + cpu = <&cpu5>;
> > > > + };
> > > > + };
> > > > +
> > > > + cluster1 {
> > > > + core0 {
> > > > + cpu = <&cpu6>;
> > > > + };
> > > > +
> > > > + core1 {
> > > > + cpu = <&cpu7>;
> > > > + };
> > > > + };
> > > > + };
> > > > +
> > > > + idle-states {
> > > > + entry-method = "arm,psci";
> > > > +
> > > > + cpuoff_l: cpu-off-l {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x00010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <50>;
> > > > + exit-latency-us = <100>;
> > > > + min-residency-us = <1600>;
> > > > + };
> > > > +
> > > > + cpuoff_b: cpu-off-b {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x00010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <50>;
> > > > + exit-latency-us = <100>;
> > > > + min-residency-us = <1400>;
> > > > + };
> > > > +
> > > > + clusteroff_l: cluster-off-l {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x01010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <100>;
> > > > + exit-latency-us = <250>;
> > > > + min-residency-us = <2100>;
> > > > + };
> > > > +
> > > > + clusteroff_b: cluster-off-b {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x01010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <100>;
> > > > + exit-latency-us = <250>;
> > > > + min-residency-us = <1900>;
> > > > + };
> > > > + };
> > > > +
> > > > + l2_0: l2-cache0 {
> > > > + compatible = "cache";
> > > > + next-level-cache = <&l3_0>;
> > > > + };
> > > > +
> > > > + l2_1: l2-cache1 {
> > > > + compatible = "cache";
> > > > + next-level-cache = <&l3_0>;
> > > > + };
> > > > +
> > > > + l3_0: l3-cache {
> > > > + compatible = "cache";
> > > > + };
> > > > + };
> > > > +
> > > > + psci {
> > > > + compatible = "arm,psci-1.0";
> > > > + method = "smc";
> > > > + };
> > > > +
> > > > + timer: timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupt-parent = <&gic>;
> > > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > > > + clock-frequency = <13000000>;
> > > > + };
> > > > +
> > > > + soc {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + compatible = "simple-bus";
> > > > + ranges;
> > > > +
> > > > + gic: interrupt-controller@c000000 {
> > > > + compatible = "arm,gic-v3";
> > > > + #interrupt-cells = <3>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + #redistributor-regions = <1>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupt-controller;
> > > > + reg = <0 0x0c000000 0 0x40000>, //
> > > > distributor
> > > > + <0 0x0c040000 0 0x200000>; //
> > > > redistributor
> > > > + interrupts = <GIC_PPI 9
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + watchdog: watchdog@10007000 {
> > > > + compatible = "mediatek,mt8186-wdt",
> > > > + "mediatek,mt6589-wdt";
> > > > + mediatek,disable-extrst;
> > > > + reg = <0 0x10007000 0 0x1000>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > +
> > > > + systimer: timer@10017000 {
> > > > + compatible = "mediatek,mt8186-timer",
> > > > + "mediatek,mt6765-timer";
> > > > + reg = <0 0x10017000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 207
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk13m>;
> > > > + };
> > > > +
> > > > + uart0: serial@11002000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11002000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 112
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + };
> > > > +
> > > > + uart1: serial@11003000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11003000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 113
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart2: serial@11018000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11018000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 246
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc0: mmc@11230000 {
> > > > + compatible = "mediatek,mt8186-mmc",
> > > > + "mediatek,mt8183-mmc";
> > > > + reg = <0 0x11230000 0 0x1000>,
> > > > + <0 0x11cd0000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 100
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>,
> > > > <&clk26m>,
> > > > + <&clk26m>;
> > > > + clock-names = "source", "hclk",
> > > > "source_cg",
> > > > "ahb_clk";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc1: mmc@11240000 {
> > > > + compatible = "mediatek,mt8186-mmc",
> > > > + "mediatek,mt8183-mmc";
> > > > + reg = <0 0x11240000 0 0x1000>,
> > > > + <0 0x11c90000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 101
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>,
> > > > <&clk26m>;
> > > > + clock-names = "source", "hclk",
> > > > "source_cg";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + u3phy0: t-phy@11c80000 {
> > > > + compatible = "mediatek,mt8186-tphy",
> > > > + "mediatek,generic-tphy-
> > > > v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x11c80000 0x1000>;
> > > > +
> > > > + u2port1: usb2-phy1@0 {
> > > > + reg = <0x0 0x700>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + };
> > > > +
> > > > + u3port1: usb3-phy1@700 {
> > > > + reg = <0x700 0x900>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + u3phy1: t-phy@11ca0000 {
> > > > + compatible = "mediatek,mt8186-tphy",
> > > > + "mediatek,generic-tphy-
> > > > v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> > > > +
> > > > + u2port0: usb-phy@0 {
> > > > + reg = <0x0 0x700>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + mediatek,discth = <0x8>;
> > > > + };
> > > > + };
> > > > + };
> > > > +};
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
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^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
@ 2022-04-26 11:12 ` allen-kh.cheng
0 siblings, 0 replies; 43+ messages in thread
From: allen-kh.cheng @ 2022-04-26 11:12 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Kishon Vijay Abraham I,
Daniel Lezcano, Thomas Gleixner, Wim Van Sebroeck, Guenter Roeck
Cc: hsinyi, Project_Global_Chrome_Upstream_Group, linux-kernel,
devicetree, linux-mediatek, linux-arm-kernel, linux-watchdog
Hi Matthias,
On Tue, 2022-04-26 at 12:28 +0200, Matthias Brugger wrote:
> Hi Allen,
>
> On 30/03/2022 09:34, allen-kh.cheng wrote:
> > Hi Matthias,
> >
> > On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
> > >
> > > On 11/03/2022 14:07, Allen-KH Cheng wrote:
> > > > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > > >
> > > > Add basic chip support for Mediatek MT8186.
> > > >
> > >
> > > Thanks for your patch. I would love to wait a bit longer to see
> > > if we
> > > can get
> > > the clock driver accepted. This way we could get rid of all the
> > > dummy
> > > clocks
> > > defined in here.
> > >
> > > Please send a new version once the clock driver is accepeted by
> > > Stephen, or ping
> > > this series in a few month.
> > >
> > > Thanks,
> > > Matthias
> > >
> >
> > Sure, that's great.
> >
> > I will send a new version after the clock driver is accepted.
> >
>
> I've seen that the clock driver got accepted. Can you please send a
> new patch
> adding the correct clocks to the nodes?
>
> Thanks a lot.
> Matthias
>
Sure, I am going to prepare the PATCH.
I will send a new patch ASAP.
Thanks,
Allen
> > Thanks,
> > Allen
> >
> > > > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > > > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > > > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
> > > > ++++++++++++++++++++
> > > > 3 files changed, 381 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-
> > > > evb.dts
> > > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > > > b/arch/arm64/boot/dts/mediatek/Makefile
> > > > index 8c1e18032f9f..d32fdcf9afc6 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > > > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > > > @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > > > kodama-sku32.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > > > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > new file mode 100644
> > > > index 000000000000..eb23d1f19f87
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > @@ -0,0 +1,24 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + */
> > > > +/dts-v1/;
> > > > +#include "mt8186.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "MediaTek MT8186 evaluation board";
> > > > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > > > +
> > > > + aliases {
> > > > + serial0 = &uart0;
> > > > + };
> > > > +
> > > > + chosen {
> > > > + stdout-path = "serial0:921600n8";
> > > > + };
> > > > +
> > > > + memory {
> > > > + device_type = "memory";
> > > > + reg = <0 0x40000000 0 0x80000000>;
> > > > + };
> > > > +};
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > new file mode 100644
> > > > index 000000000000..aa45c75b18c7
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > @@ -0,0 +1,356 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + * Author: Allen-KH Cheng <allenn-kh.cheng@mediatek.com>
> > > > + */
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +#include <dt-bindings/phy/phy.h>
> > > > +
> > > > +/ {
> > > > + compatible = "mediatek,mt8186";
> > > > + interrupt-parent = <&gic>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > +
> > > > + clk13m: oscillator0 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <13000000>;
> > > > + clock-output-names = "clk13m";
> > > > + };
> > > > +
> > > > + clk26m: oscillator1 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <26000000>;
> > > > + clock-output-names = "clk26m";
> > > > + };
> > > > +
> > > > + clk32k: oscillator2 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <32000>;
> > > > + clock-output-names = "clk32k";
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + cpu0: cpu@000 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0000>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu1: cpu@100 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0100>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu2: cpu@200 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0200>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu3: cpu@300 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0300>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu4: cpu@400 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0400>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu5: cpu@500 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0500>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu6: cpu@600 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a75",
> > > > "arm,armv8";
> > > > + reg = <0x0600>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2050000000>;
> > > > + cpu-idle-states = <&cpuoff_b
> > > > &clusteroff_b>;
> > > > + next-level-cache = <&l2_1>;
> > > > + };
> > > > +
> > > > + cpu7: cpu@700 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a75",
> > > > "arm,armv8";
> > > > + reg = <0x0700>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2050000000>;
> > > > + cpu-idle-states = <&cpuoff_b
> > > > &clusteroff_b>;
> > > > + next-level-cache = <&l2_1>;
> > > > + };
> > > > +
> > > > + cpu-map {
> > > > + cluster0 {
> > > > + core0 {
> > > > + cpu = <&cpu0>;
> > > > + };
> > > > +
> > > > + core1 {
> > > > + cpu = <&cpu1>;
> > > > + };
> > > > +
> > > > + core2 {
> > > > + cpu = <&cpu2>;
> > > > + };
> > > > +
> > > > + core3 {
> > > > + cpu = <&cpu3>;
> > > > + };
> > > > +
> > > > + core4 {
> > > > + cpu = <&cpu4>;
> > > > + };
> > > > +
> > > > + core5 {
> > > > + cpu = <&cpu5>;
> > > > + };
> > > > + };
> > > > +
> > > > + cluster1 {
> > > > + core0 {
> > > > + cpu = <&cpu6>;
> > > > + };
> > > > +
> > > > + core1 {
> > > > + cpu = <&cpu7>;
> > > > + };
> > > > + };
> > > > + };
> > > > +
> > > > + idle-states {
> > > > + entry-method = "arm,psci";
> > > > +
> > > > + cpuoff_l: cpu-off-l {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x00010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <50>;
> > > > + exit-latency-us = <100>;
> > > > + min-residency-us = <1600>;
> > > > + };
> > > > +
> > > > + cpuoff_b: cpu-off-b {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x00010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <50>;
> > > > + exit-latency-us = <100>;
> > > > + min-residency-us = <1400>;
> > > > + };
> > > > +
> > > > + clusteroff_l: cluster-off-l {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x01010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <100>;
> > > > + exit-latency-us = <250>;
> > > > + min-residency-us = <2100>;
> > > > + };
> > > > +
> > > > + clusteroff_b: cluster-off-b {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x01010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <100>;
> > > > + exit-latency-us = <250>;
> > > > + min-residency-us = <1900>;
> > > > + };
> > > > + };
> > > > +
> > > > + l2_0: l2-cache0 {
> > > > + compatible = "cache";
> > > > + next-level-cache = <&l3_0>;
> > > > + };
> > > > +
> > > > + l2_1: l2-cache1 {
> > > > + compatible = "cache";
> > > > + next-level-cache = <&l3_0>;
> > > > + };
> > > > +
> > > > + l3_0: l3-cache {
> > > > + compatible = "cache";
> > > > + };
> > > > + };
> > > > +
> > > > + psci {
> > > > + compatible = "arm,psci-1.0";
> > > > + method = "smc";
> > > > + };
> > > > +
> > > > + timer: timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupt-parent = <&gic>;
> > > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > > > + clock-frequency = <13000000>;
> > > > + };
> > > > +
> > > > + soc {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + compatible = "simple-bus";
> > > > + ranges;
> > > > +
> > > > + gic: interrupt-controller@c000000 {
> > > > + compatible = "arm,gic-v3";
> > > > + #interrupt-cells = <3>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + #redistributor-regions = <1>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupt-controller;
> > > > + reg = <0 0x0c000000 0 0x40000>, //
> > > > distributor
> > > > + <0 0x0c040000 0 0x200000>; //
> > > > redistributor
> > > > + interrupts = <GIC_PPI 9
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + watchdog: watchdog@10007000 {
> > > > + compatible = "mediatek,mt8186-wdt",
> > > > + "mediatek,mt6589-wdt";
> > > > + mediatek,disable-extrst;
> > > > + reg = <0 0x10007000 0 0x1000>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > +
> > > > + systimer: timer@10017000 {
> > > > + compatible = "mediatek,mt8186-timer",
> > > > + "mediatek,mt6765-timer";
> > > > + reg = <0 0x10017000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 207
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk13m>;
> > > > + };
> > > > +
> > > > + uart0: serial@11002000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11002000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 112
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + };
> > > > +
> > > > + uart1: serial@11003000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11003000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 113
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart2: serial@11018000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11018000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 246
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc0: mmc@11230000 {
> > > > + compatible = "mediatek,mt8186-mmc",
> > > > + "mediatek,mt8183-mmc";
> > > > + reg = <0 0x11230000 0 0x1000>,
> > > > + <0 0x11cd0000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 100
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>,
> > > > <&clk26m>,
> > > > + <&clk26m>;
> > > > + clock-names = "source", "hclk",
> > > > "source_cg",
> > > > "ahb_clk";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc1: mmc@11240000 {
> > > > + compatible = "mediatek,mt8186-mmc",
> > > > + "mediatek,mt8183-mmc";
> > > > + reg = <0 0x11240000 0 0x1000>,
> > > > + <0 0x11c90000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 101
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>,
> > > > <&clk26m>;
> > > > + clock-names = "source", "hclk",
> > > > "source_cg";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + u3phy0: t-phy@11c80000 {
> > > > + compatible = "mediatek,mt8186-tphy",
> > > > + "mediatek,generic-tphy-
> > > > v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x11c80000 0x1000>;
> > > > +
> > > > + u2port1: usb2-phy1@0 {
> > > > + reg = <0x0 0x700>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + };
> > > > +
> > > > + u3port1: usb3-phy1@700 {
> > > > + reg = <0x700 0x900>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + u3phy1: t-phy@11ca0000 {
> > > > + compatible = "mediatek,mt8186-tphy",
> > > > + "mediatek,generic-tphy-
> > > > v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> > > > +
> > > > + u2port0: usb-phy@0 {
> > > > + reg = <0x0 0x700>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + mediatek,discth = <0x8>;
> > > > + };
> > > > + };
> > > > + };
> > > > +};
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
2022-03-30 11:49 ` Daniel Lezcano
@ 2022-04-26 12:30 ` allen-kh.cheng
-1 siblings, 0 replies; 43+ messages in thread
From: allen-kh.cheng @ 2022-04-26 12:30 UTC (permalink / raw)
To: Daniel Lezcano, Rob Herring
Cc: hsinyi, Thomas Gleixner, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Wim Van Sebroeck, Matthias Brugger, Kishon Vijay Abraham I
Hi Daniel,
I just want to check with you.
I cannot find the git repositories you applied.
Would you mind sharing the information to me?
Thanks,
Allen
On Wed, 2022-03-30 at 13:49 +0200, Daniel Lezcano wrote:
> On 11/03/2022 16:50, Rob Herring wrote:
> > On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
> > > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > >
> > > This commit adds dt-binding documentation of timer for Mediatek
> > > MT8186 SoC
> > > Platform.
> > >
> > > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > > ---
> > > Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> > > | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> >
> > Acked-by: Rob Herring <robh@kernel.org>
>
> Applied, thanks
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186
@ 2022-04-26 12:30 ` allen-kh.cheng
0 siblings, 0 replies; 43+ messages in thread
From: allen-kh.cheng @ 2022-04-26 12:30 UTC (permalink / raw)
To: Daniel Lezcano, Rob Herring
Cc: hsinyi, Thomas Gleixner, Guenter Roeck,
Project_Global_Chrome_Upstream_Group, linux-watchdog, devicetree,
linux-kernel, Rob Herring, linux-arm-kernel, linux-mediatek,
Wim Van Sebroeck, Matthias Brugger, Kishon Vijay Abraham I
Hi Daniel,
I just want to check with you.
I cannot find the git repositories you applied.
Would you mind sharing the information to me?
Thanks,
Allen
On Wed, 2022-03-30 at 13:49 +0200, Daniel Lezcano wrote:
> On 11/03/2022 16:50, Rob Herring wrote:
> > On Fri, 11 Mar 2022 21:07:29 +0800, Allen-KH Cheng wrote:
> > > From: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > >
> > > This commit adds dt-binding documentation of timer for Mediatek
> > > MT8186 SoC
> > > Platform.
> > >
> > > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
> > > ---
> > > Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> > > | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> >
> > Acked-by: Rob Herring <robh@kernel.org>
>
> Applied, thanks
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 43+ messages in thread
* [tip: timers/core] dt-bindings: timer: Add compatible for Mediatek MT8186
2022-03-11 13:07 ` Allen-KH Cheng
` (2 preceding siblings ...)
(?)
@ 2022-05-27 8:36 ` tip-bot2 for Allen-KH Cheng
-1 siblings, 0 replies; 43+ messages in thread
From: tip-bot2 for Allen-KH Cheng @ 2022-05-27 8:36 UTC (permalink / raw)
To: linux-tip-commits
Cc: Allen-KH Cheng, Rob Herring, Daniel Lezcano, x86, linux-kernel
The following commit has been merged into the timers/core branch of tip:
Commit-ID: b8b1ab133e593f0dbfa47b174a54b852af6f856e
Gitweb: https://git.kernel.org/tip/b8b1ab133e593f0dbfa47b174a54b852af6f856e
Author: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
AuthorDate: Fri, 11 Mar 2022 21:07:29 +08:00
Committer: Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Wed, 18 May 2022 11:08:52 +02:00
dt-bindings: timer: Add compatible for Mediatek MT8186
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC
Platform.
Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220311130732.22706-2-allen-kh.cheng@mediatek.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index fbd76a8..6f1f9db 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -23,6 +23,7 @@ Required properties:
For those SoCs that use SYST
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
+ * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
^ permalink raw reply related [flat|nested] 43+ messages in thread
end of thread, other threads:[~2022-05-27 8:37 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-11 13:07 [PATCH v4 0/4] Add basic node support for Mediatek MT8186 SoC Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 13:07 ` [PATCH v4 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186 Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 15:50 ` Rob Herring
2022-03-11 15:50 ` Rob Herring
2022-03-11 15:50 ` Rob Herring
2022-03-30 11:49 ` Daniel Lezcano
2022-03-30 11:49 ` Daniel Lezcano
2022-03-30 11:49 ` Daniel Lezcano
2022-04-26 12:30 ` allen-kh.cheng
2022-04-26 12:30 ` allen-kh.cheng
2022-05-27 8:36 ` [tip: timers/core] " tip-bot2 for Allen-KH Cheng
2022-03-11 13:07 ` [PATCH v4 2/4] dt-bindings: watchdog: " Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 15:50 ` Rob Herring
2022-03-11 15:50 ` Rob Herring
2022-03-11 15:50 ` Rob Herring
2022-03-14 1:46 ` Rex-BC Chen
2022-03-14 1:46 ` Rex-BC Chen
2022-03-14 1:46 ` Rex-BC Chen
2022-03-11 13:07 ` [PATCH v4 3/4] dt-bindings: arm: " Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 15:51 ` Rob Herring
2022-03-11 15:51 ` Rob Herring
2022-03-11 15:51 ` Rob Herring
2022-03-11 13:07 ` [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-11 13:07 ` Allen-KH Cheng
2022-03-29 14:56 ` Matthias Brugger
2022-03-29 14:56 ` Matthias Brugger
2022-03-29 14:56 ` Matthias Brugger
2022-03-30 7:34 ` allen-kh.cheng
2022-03-30 7:34 ` allen-kh.cheng
2022-04-26 10:28 ` Matthias Brugger
2022-04-26 10:28 ` Matthias Brugger
2022-04-26 10:28 ` Matthias Brugger
2022-04-26 11:12 ` allen-kh.cheng
2022-04-26 11:12 ` allen-kh.cheng
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