[PATCH V2 00/26] imx: imx8ulp: misc update from downstream

[PATCH V2 00/26] imx: imx8ulp: misc update from downstream

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

V2:
 Update commit log
 Drop patch 26 in V1
 Minor update

This patchset is to upstream NXP downstream i.MX8ULP patches
 - Support Nominal/Low Drive clock settings
 - Update mem map for TEE
 - Release CAAM
 - Support Dual boot
 - Enable handshake with M33
 - Update DDR and PHY settings
 - Misc clock update

Clark Wang (1):
  imx: imx8ulp: clock: Add clock support for i3c controller

Clement Faure (2):
  misc: S400_API: add ahab_release_caam
  imx: imx8ulp: release CAAM for the Cortex-A35

Ji Luo (1):
  imx: imx8ulp: reserve tee memory

Peng Fan (9):
  imx: imx8ulp: include pcc/cgc header in clock header
  imx: imx8ulp: add CAAM clock entry
  imx: imx8ulp: add ND/LD clock
  imx: imx8ulp: enable MU0_B clk by default
  imx: dynamic setting mmcdev and mmcroot
  imx: imx8ulp_evk: Enable SD/MMC port auto detect
  imx: imx8ulp: enable wdog_ad interrupt in CMC1
  imx: imx8ulp_evk: enlarge CONFIG_NR_DRAM_BANKS
  misc: imx8ulp: Update fuse driver

Ye Li (13):
  imx: imx8ulp: Set COUNTER_FREQUENCY to 1Mhz
  imx: imx8ulp: Add M33 handshake functions
  imx: imx8ulp_evk: Remove PMIC Bucks PWM mode settings
  imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
  imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init
  misc: imx8ulp: Add OEM SRK Hash fuse support
  imx: imx8ulp: Change LPAV assignment for dual boot
  imx: imx8ulp: Load the lposc fuse for dual boot
  misc: S400_API: Update S400 API for buffer dump
  imx: imx8ulp_evk: Update LPDDR4 PHY settings
  imx: imx8ulp_evk: call the handshake with M33
  imx: imx8ulp_evk: Power down the domains may used in u-boot
  imx: imx8ulp_evk: Enable multiple env storage devices

 arch/arm/include/asm/arch-imx8ulp/cgc.h       |    8 +-
 arch/arm/include/asm/arch-imx8ulp/clock.h     |    8 +-
 arch/arm/include/asm/arch-imx8ulp/imx-regs.h  |    1 +
 arch/arm/include/asm/arch-imx8ulp/pcc.h       |    1 +
 arch/arm/include/asm/arch-imx8ulp/s400_api.h  |    5 +-
 arch/arm/include/asm/arch-imx8ulp/sys_proto.h |    2 +
 arch/arm/include/asm/mach-imx/sys_proto.h     |    2 +
 arch/arm/mach-imx/imx8ulp/Kconfig             |    6 +
 arch/arm/mach-imx/imx8ulp/cgc.c               |  106 +-
 arch/arm/mach-imx/imx8ulp/clock.c             |   95 +-
 arch/arm/mach-imx/imx8ulp/pcc.c               |    1 +
 arch/arm/mach-imx/imx8ulp/soc.c               |  197 ++-
 board/freescale/common/Makefile               |    3 +
 board/freescale/common/mmc.c                  |   49 +
 board/freescale/imx8ulp_evk/Makefile          |    7 +-
 board/freescale/imx8ulp_evk/imx8ulp_evk.c     |   43 +-
 board/freescale/imx8ulp_evk/lpddr4_timing.c   |   32 +-
 .../freescale/imx8ulp_evk/lpddr4_timing_266.c | 1109 +++++++++++++++++
 board/freescale/imx8ulp_evk/spl.c             |   59 +-
 configs/imx8ulp_evk_defconfig                 |    2 +-
 drivers/misc/imx8ulp/fuse.c                   |    4 +-
 drivers/misc/imx8ulp/s400_api.c               |   63 +
 include/configs/imx8ulp_evk.h                 |    2 +
 23 files changed, 1696 insertions(+), 109 deletions(-)
 create mode 100644 board/freescale/common/mmc.c
 create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing_266.c

-- 
2.35.1

[PATCH V2 01/26] imx: imx8ulp: Set COUNTER_FREQUENCY to 1Mhz

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

The COUNTER_FREQUENCY is missed in 8ulp configs, it will cause SPL
and u-boot not set the cntfrq_el0. For u-boot, this is ok, because
ATF has set it. But for SPL, it will lead delay and get_timer
not working.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/configs/imx8ulp_evk.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index ddb3d444f03..e6886746320 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -27,6 +27,8 @@
 
 #endif
 
+#define COUNTER_FREQUENCY		1000000 /* 1MHz */
+
 /* ENET Config */
 #if defined(CONFIG_FEC_MXC)
 #define PHY_ANEG_TIMEOUT		20000
-- 
2.35.1

[PATCH V2 01/26] imx: imx8ulp: Set COUNTER_FREQUENCY to 1Mhz

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> The COUNTER_FREQUENCY is missed in 8ulp configs, it will cause SPL
> and u-boot not set the cntfrq_el0. For u-boot, this is ok, because
> ATF has set it. But for SPL, it will lead delay and get_timer
> not working.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 02/26] imx: imx8ulp: include pcc/cgc header in clock header

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

With this change, we no need to include pcc/cgc header files both.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/clock.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index c0f32cc087f..d7c92f7058d 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -6,6 +6,9 @@
 #ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
 #define _ASM_ARCH_IMX8ULP_CLOCK_H
 
+#include <asm/arch/pcc.h>
+#include <asm/arch/cgc.h>
+
 /* Mainly for compatible to imx common code. */
 enum mxc_clock {
 	MXC_ARM_CLK = 0,
-- 
2.35.1

[PATCH V2 02/26] imx: imx8ulp: include pcc/cgc header in clock header

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> With this change, we no need to include pcc/cgc header files both.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 03/26] imx: imx8ulp: Add M33 handshake functions

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/imx-regs.h  |  1 +
 arch/arm/include/asm/arch-imx8ulp/sys_proto.h |  2 ++
 arch/arm/mach-imx/imx8ulp/soc.c               | 36 +++++++++++++++++++
 3 files changed, 39 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 91adc85525c..723bab584c3 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -14,6 +14,7 @@
 
 #define CMC0_RBASE		0x28025000
 
+#define MU0_B_BASE_ADDR		0x29220000
 #define CMC1_BASE_ADDR		0x29240000
 
 #define SIM1_BASE_ADDR		0x29290000
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 284ccafc988..5f030eaa0ad 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -18,4 +18,6 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
 enum boot_device get_boot_device(void);
 void set_lpav_qos(void);
 void load_lposc_fuse(void);
+bool m33_image_booted(void);
+int m33_image_handshake(ulong timeout_ms);
 #endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index e6d417ed48b..9a632b9cc6a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -26,6 +26,7 @@
 #include <dm/uclass-internal.h>
 #include <fuse.h>
 #include <thermal.h>
+#include <linux/iopoll.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -137,6 +138,41 @@ enum bt_mode get_boot_mode(void)
 	return LOW_POWER_BOOT;
 }
 
+bool m33_image_booted(void)
+{
+	u32 gp6;
+
+	/* DGO_GP6 */
+	gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
+	if (gp6 & BIT(5))
+		return true;
+
+	return false;
+}
+
+int m33_image_handshake(ulong timeout_ms)
+{
+	u32 fsr;
+	int ret;
+	ulong timeout_us = timeout_ms * 1000;
+
+	/* enable MU0_MUB clock before access the register of MU0_MUB */
+	pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
+
+	/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
+	setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
+
+	/*
+	 * Wait m33 to set FCR F0 flag of MU0_MUA
+	 * Clear FCR F0 flag of MU0_MUB after m33 has set FCR F0 flag of MU0_MUA
+	 */
+	ret = readl_poll_sleep_timeout(MU0_B_BASE_ADDR + 0x104, fsr, fsr & BIT(0), 10, timeout_us);
+	if (!ret)
+		clrbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0));
+
+	return ret;
+}
+
 #define CMC_SRS_TAMPER                    BIT(31)
 #define CMC_SRS_SECURITY                  BIT(30)
 #define CMC_SRS_TZWDG                     BIT(29)
-- 
2.35.1

[PATCH V2 03/26] imx: imx8ulp: Add M33 handshake functions

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Add functions to check if M33 image is booted and handshake with M33
> image via MU. A core notifies M33 to start init by FCR F0, then wait
> M33 init done signal by checking FSR F0.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Biwen Li <biwen.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 04/26] imx: imx8ulp: clock: Add clock support for i3c controller

[Peng Fan (OSS)]

From: Clark Wang <xiaoning.wang@nxp.com>

Add i3c controller clock enable/disable function for imx8ulp.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/clock.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 91580b2c29c..a2b3ce78cc1 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -237,6 +237,26 @@ u32 imx_get_i2cclk(u32 i2c_num)
 }
 #endif
 
+#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C)
+int enable_i3c_clk(unsigned char enable, u32 i3c_num)
+{
+	if (enable) {
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+		pcc_clock_sel(3, I3C2_PCC3_SLOT, SOSC_DIV2);
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, true);
+		pcc_reset_peripheral(3, I3C2_PCC3_SLOT, false);
+	} else {
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+	}
+	return 0;
+}
+
+u32 imx_get_i3cclk(u32 i3c_num)
+{
+	return pcc_clock_get_rate(3, I3C2_PCC3_SLOT);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
 	if (enable) {
-- 
2.35.1

[PATCH V2 04/26] imx: imx8ulp: clock: Add clock support for i3c controller

[sbabic]

> From: Clark Wang <xiaoning.wang@nxp.com>
> Add i3c controller clock enable/disable function for imx8ulp.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 05/26] imx: imx8ulp: add CAAM clock entry

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add CAAM clock entry in PCC3

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/pcc.h | 1 +
 arch/arm/mach-imx/imx8ulp/pcc.c         | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h
index 46386f1aba4..d9b2d7c2998 100644
--- a/arch/arm/include/asm/arch-imx8ulp/pcc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h
@@ -52,6 +52,7 @@ enum pcc3_entry {
 	UPOWER_PCC3_SLOT = 40,
 	WDOG3_PCC3_SLOT = 42,
 	WDOG4_PCC3_SLOT = 43,
+	CAAM_PCC3_SLOT = 46,
 	XRDC_MGR_PCC3_SLOT = 47,
 	SEMA42_1_PCC3_SLOT = 48,
 	ROMCP1_PCC3_SLOT = 49,
diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c
index 7909d770afe..e3c6d6760be 100644
--- a/arch/arm/mach-imx/imx8ulp/pcc.c
+++ b/arch/arm/mach-imx/imx8ulp/pcc.c
@@ -135,6 +135,7 @@ static struct pcc_entry pcc3_arrays[] = {
 	{PCC3_RBASE, UPOWER_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
 	{PCC3_RBASE, WDOG3_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
 	{PCC3_RBASE, WDOG4_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
+	{PCC3_RBASE, CAAM_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B},
 	{PCC3_RBASE, XRDC_MGR_PCC3_SLOT,	CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
 	{PCC3_RBASE, SEMA42_1_PCC3_SLOT,	CLKSRC_PER_BUS, PCC_NO_DIV, PCC_NO_RST_B},
 	{PCC3_RBASE, ROMCP1_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
-- 
2.35.1

[PATCH V2 05/26] imx: imx8ulp: add CAAM clock entry

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Add CAAM clock entry in PCC3
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 06/26] imx: imx8ulp_evk: Remove PMIC Bucks PWM mode settings

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

This workaround is not needed on i.MX8ULP proto-1B EVK as board has
fixed the problem. Because we don't support proto-1A any longer,
remove the PMIC settings.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/spl.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index c17d5eff7dc..b3149014098 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -35,24 +35,6 @@ u32 spl_boot_device(void)
 
 int power_init_board(void)
 {
-	u32 pmic_reg;
-
-	/* PMIC set bucks1-4 to PWM mode */
-	upower_pmic_i2c_read(0x10, &pmic_reg);
-	upower_pmic_i2c_read(0x14, &pmic_reg);
-	upower_pmic_i2c_read(0x21, &pmic_reg);
-	upower_pmic_i2c_read(0x2e, &pmic_reg);
-
-	upower_pmic_i2c_write(0x10, 0x3d);
-	upower_pmic_i2c_write(0x14, 0x7d);
-	upower_pmic_i2c_write(0x21, 0x7d);
-	upower_pmic_i2c_write(0x2e, 0x3d);
-
-	upower_pmic_i2c_read(0x10, &pmic_reg);
-	upower_pmic_i2c_read(0x14, &pmic_reg);
-	upower_pmic_i2c_read(0x21, &pmic_reg);
-	upower_pmic_i2c_read(0x2e, &pmic_reg);
-
 	/* Set buck3 to 1.1v OD */
 	upower_pmic_i2c_write(0x22, 0x28);
 	return 0;
-- 
2.35.1

[PATCH V2 06/26] imx: imx8ulp_evk: Remove PMIC Bucks PWM mode settings

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> This workaround is not needed on i.MX8ULP proto-1B EVK as board has
> fixed the problem. Because we don't support proto-1A any longer,
> remove the PMIC settings.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 07/26] imx: imx8ulp: add ND/LD clock

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.

Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/cgc.h       |    6 +-
 arch/arm/include/asm/arch-imx8ulp/clock.h     |    5 +-
 arch/arm/mach-imx/imx8ulp/Kconfig             |    6 +
 arch/arm/mach-imx/imx8ulp/cgc.c               |   78 +-
 arch/arm/mach-imx/imx8ulp/clock.c             |   70 +-
 arch/arm/mach-imx/imx8ulp/soc.c               |    2 +-
 board/freescale/imx8ulp_evk/Makefile          |    7 +-
 .../freescale/imx8ulp_evk/lpddr4_timing_266.c | 1109 +++++++++++++++++
 board/freescale/imx8ulp_evk/spl.c             |   15 +-
 9 files changed, 1251 insertions(+), 47 deletions(-)
 create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing_266.c

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index ad3edc85adb..e45f04624db 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -146,10 +146,10 @@ struct cgc2_regs {
 };
 
 u32 cgc_clk_get_rate(enum cgc_clk clk);
-void cgc1_pll3_init(void);
-void cgc1_pll2_init(void);
+void cgc1_pll3_init(ulong freq);
+void cgc1_pll2_init(ulong freq);
 void cgc1_soscdiv_init(void);
-void cgc1_init_core_clk(void);
+void cgc1_init_core_clk(ulong freq);
 void cgc2_pll4_init(void);
 void cgc2_ddrclk_config(u32 src, u32 div);
 void cgc2_ddrclk_wait_unlock(void);
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index d7c92f7058d..2946cc19119 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -9,6 +9,8 @@
 #include <asm/arch/pcc.h>
 #include <asm/arch/cgc.h>
 
+#define MHZ(X)	((X) * 1000000UL)
+
 /* Mainly for compatible to imx common code. */
 enum mxc_clock {
 	MXC_ARM_CLK = 0,
@@ -39,7 +41,8 @@ void init_clk_usdhc(u32 index);
 void init_clk_fspi(int index);
 void init_clk_ddr(void);
 int set_ddr_clk(u32 phy_freq_mhz);
-void clock_init(void);
+void clock_init_early(void);
+void clock_init_late(void);
 void cgc1_enet_stamp_sel(u32 clk_src);
 void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
 void reset_lcdclk(void);
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig
index 963fc93d34f..98b6ecdf301 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -7,6 +7,12 @@ config IMX8ULP
 config SYS_SOC
 	default "imx8ulp"
 
+config IMX8ULP_LD_MODE
+	bool
+
+config IMX8ULP_ND_MODE
+	bool "i.MX8ULP Low Driver Mode"
+
 choice
 	prompt "i.MX8ULP board select"
 	optional
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 38bcbb91e6e..494ddb0f329 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -9,9 +9,11 @@
 #include <errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/cgc.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
 #include <linux/delay.h>
+#include <hang.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,7 +31,7 @@ void cgc1_soscdiv_init(void)
 	clrbits_le32(&cgc1_regs->frodiv, BIT(7));
 }
 
-void cgc1_pll2_init(void)
+void cgc1_pll2_init(ulong freq)
 {
 	u32 reg;
 
@@ -44,8 +46,8 @@ void cgc1_pll2_init(void)
 	while ((readl(&cgc1_regs->pll2csr) & BIT(24)))
 		;
 
-	/* Select SOSC as source, freq = 31 * 24 =744mhz */
-	reg = 31 << 16;
+	/* Select SOSC as source */
+	reg = (freq / MHZ(24)) << 16;
 	writel(reg, &cgc1_regs->pll2cfg);
 
 	/* Enable PLL2 */
@@ -74,7 +76,7 @@ static void cgc1_set_a35_clk(u32 clk_src, u32 div_core)
 		;
 }
 
-void cgc1_init_core_clk(void)
+void cgc1_init_core_clk(ulong freq)
 {
 	u32 reg = readl(&cgc1_regs->ca35clk);
 
@@ -82,8 +84,7 @@ void cgc1_init_core_clk(void)
 	if (((reg >> 28) & 0x3) == 0x1)
 		cgc1_set_a35_clk(0, 1);
 
-	/* Set pll2 to 750Mhz for 1V  */
-	cgc1_pll2_init();
+	cgc1_pll2_init(freq);
 
 	/* Set A35 clock to pll2 */
 	cgc1_set_a35_clk(1, 1);
@@ -94,7 +95,7 @@ void cgc1_enet_stamp_sel(u32 clk_src)
 	writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp);
 }
 
-void cgc1_pll3_init(void)
+void cgc1_pll3_init(ulong freq)
 {
 	/* Gate off VCO */
 	setbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
@@ -115,11 +116,15 @@ void cgc1_pll3_init(void)
 	/* Select SOSC as source */
 	clrbits_le32(&cgc1_regs->pll3cfg, BIT(0));
 
-	//setbits_le32(&cgc1_regs->pll3cfg, 22 << 16);
-	writel(22 << 16, &cgc1_regs->pll3cfg);
-
-	writel(578, &cgc1_regs->pll3num);
-	writel(1000, &cgc1_regs->pll3denom);
+	switch (freq) {
+	case 540672000:
+		writel(0x16 << 16, &cgc1_regs->pll3cfg);
+		writel(0x16e3600, &cgc1_regs->pll3denom);
+		writel(0xc15c00, &cgc1_regs->pll3num);
+		break;
+	default:
+		hang();
+	}
 
 	/* Enable PLL3 */
 	setbits_le32(&cgc1_regs->pll3csr, BIT(0));
@@ -130,23 +135,30 @@ void cgc1_pll3_init(void)
 	/* Gate on VCO */
 	clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
 
-	/*
-	 * PFD0: 380MHz/396/396/328
-	 */
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
+
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0);
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */
+	} else {
+		setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */
+	}
+
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16);
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
 		;
@@ -166,6 +178,13 @@ void cgc1_pll3_init(void)
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15));
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
+
+	if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		/* nicclk select pll3 pfd0 */
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28));
+		while (!(readl(&cgc1_regs->nicclk) & BIT(27)))
+			;
+	}
 }
 
 void cgc2_pll4_init(void)
@@ -189,10 +208,21 @@ void cgc2_pll4_init(void)
 		;
 
 	/* Enable all 4 PFDs */
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0);
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
+		/* 99Mhz for NIC_LPAV */
+		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21);
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
+		/* 198Mhz for NIC_LPAV */
+		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
+	} else {
+		setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
+		clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
+	}
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */
 
 	clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 
@@ -203,6 +233,10 @@ void cgc2_pll4_init(void)
 	/* Enable PFD DIV */
 	clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 	clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
+
+	clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
+	while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+		;
 }
 
 void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index a2b3ce78cc1..46971578a91 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -102,7 +102,7 @@ void init_clk_ddr(void)
 
 	/* enable pll4 and ddrclk*/
 	cgc2_pll4_init();
-	cgc2_ddrclk_config(1, 1);
+	cgc2_ddrclk_config(4, 1);
 
 	/* enable ddr pcc */
 	writel(0xd0000000, PCC5_LPDDR4_ADDR);
@@ -153,30 +153,66 @@ int set_ddr_clk(u32 phy_freq_mhz)
 	return 0;
 }
 
-void clock_init(void)
+void clock_init_early(void)
 {
 	cgc1_soscdiv_init();
-	cgc1_init_core_clk();
 
 	init_clk_lpuart();
 
-	pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
-	pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
-	pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
-	pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+	/* Enable upower mu1 clk */
+	pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+}
 
-	pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
-	pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
-	pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
-	pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+/* This will be invoked after pmic voltage setting */
+void clock_init_late(void)
+{
 
-	pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
-	pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
-	pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
-	pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE))
+		cgc1_init_core_clk(MHZ(500));
+	else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
+		cgc1_init_core_clk(MHZ(750));
+	else
+		cgc1_init_core_clk(MHZ(960));
 
-	/* Enable upower mu1 clk */
-	pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+	/*
+	 * Audio use this frequency in kernel dts,
+	 * however nic use pll3 pfd0, we have to
+	 * make the freqency same as kernel to make nic
+	 * not being disabled
+	 */
+	cgc1_pll3_init(540672000);
+
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+	} else {
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+	}
 
 	/*
 	 * Enable clock division
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 9a632b9cc6a..85bf57b8e51 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -597,7 +597,7 @@ int arch_cpu_init(void)
 
 		xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
 
-		clock_init();
+		clock_init_early();
 	} else {
 		/* reconfigure core0 reset vector to ROM */
 		set_core0_reset_vector(0x1000);
diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile
index b2e72b4e85d..b6ca238de5d 100644
--- a/board/freescale/imx8ulp_evk/Makefile
+++ b/board/freescale/imx8ulp_evk/Makefile
@@ -3,5 +3,10 @@
 obj-y   += imx8ulp_evk.o
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o ddr_init.o lpddr4_timing.o
+obj-y += spl.o ddr_init.o
+ifdef CONFIG_IMX8ULP_ND_MODE
+obj-y += lpddr4_timing_264.o
+else
+obj-y += lpddr4_timing.o
+endif
 endif
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
new file mode 100644
index 00000000000..e48cb965c1e
--- /dev/null
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -0,0 +1,1109 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 NXP
+ *
+ * Generated code from MX8ULP_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/** CTL settings **/
+struct dram_cfg_param ddr_ctl_cfg[] = {
+	{ 0x2e060000, 0xb00 },	/* 0 */
+	{ 0x2e060028, 0x258100 },	/* 10 */
+	{ 0x2e06002c, 0x17702 },	/* 11 */
+	{ 0x2e060030, 0x5 },	/* 12 */
+	{ 0x2e060034, 0x61 },	/* 13 */
+	{ 0x2e060038, 0xce3f },	/* 14 */
+	{ 0x2e06003c, 0x80e70 },	/* 15 */
+	{ 0x2e060040, 0x5 },	/* 16 */
+	{ 0x2e060044, 0x210 },	/* 17 */
+	{ 0x2e060048, 0x19c7d },	/* 18 */
+	{ 0x2e06004c, 0x101cdf },	/* 19 */
+	{ 0x2e060050, 0x5 },	/* 20 */
+	{ 0x2e060054, 0x420 },	/* 21 */
+	{ 0x2e060058, 0x1010000 },	/* 22 */
+	{ 0x2e06005c, 0x1011001 },	/* 23 */
+	{ 0x2e060060, 0x10000 },	/* 24 */
+	{ 0x2e060064, 0x102 },	/* 25 */
+	{ 0x2e060068, 0xa },	/* 26 */
+	{ 0x2e06006c, 0x19 },	/* 27 */
+	{ 0x2e060078, 0x2020200 },	/* 30 */
+	{ 0x2e06007c, 0x160b },	/* 31 */
+	{ 0x2e060090, 0x10 },	/* 36 */
+	{ 0x2e0600a4, 0x40c040c },	/* 41 */
+	{ 0x2e0600a8, 0x8040614 },	/* 42 */
+	{ 0x2e0600ac, 0x604 },	/* 43 */
+	{ 0x2e0600b0, 0x3090003 },	/* 44 */
+	{ 0x2e0600b4, 0x40002 },	/* 45 */
+	{ 0x2e0600b8, 0xc0011 },	/* 46 */
+	{ 0x2e0600bc, 0xb0509 },	/* 47 */
+	{ 0x2e0600c0, 0x2106 },	/* 48 */
+	{ 0x2e0600c4, 0xa090017 },	/* 49 */
+	{ 0x2e0600c8, 0x8200016 },	/* 50 */
+	{ 0x2e0600cc, 0xa0a },	/* 51 */
+	{ 0x2e0600d0, 0x4000694 },	/* 52 */
+	{ 0x2e0600d4, 0xa0a0804 },	/* 53 */
+	{ 0x2e0600d8, 0x4002432 },	/* 54 */
+	{ 0x2e0600dc, 0xa0a0804 },	/* 55 */
+	{ 0x2e0600e0, 0x4004864 },	/* 56 */
+	{ 0x2e0600e4, 0x2030404 },	/* 57 */
+	{ 0x2e0600e8, 0x5040400 },	/* 58 */
+	{ 0x2e0600ec, 0x80b0a06 },	/* 59 */
+	{ 0x2e0600f0, 0x7010100 },	/* 60 */
+	{ 0x2e0600f4, 0x4150b },	/* 61 */
+	{ 0x2e0600fc, 0x1010000 },	/* 63 */
+	{ 0x2e060100, 0x1000000 },	/* 64 */
+	{ 0x2e060104, 0xe0403 },	/* 65 */
+	{ 0x2e060108, 0xb3 },	/* 66 */
+	{ 0x2e06010c, 0x4a },	/* 67 */
+	{ 0x2e060110, 0x3fd },	/* 68 */
+	{ 0x2e060114, 0x94 },	/* 69 */
+	{ 0x2e060118, 0x803 },	/* 70 */
+	{ 0x2e06011c, 0x5 },	/* 71 */
+	{ 0x2e060120, 0x70000 },	/* 72 */
+	{ 0x2e060124, 0x25000f },	/* 73 */
+	{ 0x2e060128, 0x4a0078 },	/* 74 */
+	{ 0x2e06012c, 0x4000f9 },	/* 75 */
+	{ 0x2e060130, 0x120103 },	/* 76 */
+	{ 0x2e060134, 0x50005 },	/* 77 */
+	{ 0x2e060138, 0x8070005 },	/* 78 */
+	{ 0x2e06013c, 0x505010d },	/* 79 */
+	{ 0x2e060140, 0x101030a },	/* 80 */
+	{ 0x2e060144, 0x30a0505 },	/* 81 */
+	{ 0x2e060148, 0x5050101 },	/* 82 */
+	{ 0x2e06014c, 0x1030a },	/* 83 */
+	{ 0x2e060150, 0xe000e },	/* 84 */
+	{ 0x2e060154, 0x4c004c },	/* 85 */
+	{ 0x2e060158, 0x980098 },	/* 86 */
+	{ 0x2e06015c, 0x3050505 },	/* 87 */
+	{ 0x2e060160, 0x3010403 },	/* 88 */
+	{ 0x2e060164, 0x4050505 },	/* 89 */
+	{ 0x2e060168, 0x3010403 },	/* 90 */
+	{ 0x2e06016c, 0x8050505 },	/* 91 */
+	{ 0x2e060170, 0x3010403 },	/* 92 */
+	{ 0x2e060174, 0x3010000 },	/* 93 */
+	{ 0x2e060178, 0x10000 },	/* 94 */
+	{ 0x2e060180, 0x1000000 },	/* 96 */
+	{ 0x2e060184, 0x80104002 },	/* 97 */
+	{ 0x2e060188, 0x40003 },	/* 98 */
+	{ 0x2e06018c, 0x40005 },	/* 99 */
+	{ 0x2e060190, 0x30000 },	/* 100 */
+	{ 0x2e060194, 0x50004 },	/* 101 */
+	{ 0x2e060198, 0x4 },	/* 102 */
+	{ 0x2e06019c, 0x40003 },	/* 103 */
+	{ 0x2e0601a0, 0x40005 },	/* 104 */
+	{ 0x2e0601a8, 0x2cc0 },	/* 106 */
+	{ 0x2e0601ac, 0x2cc0 },	/* 107 */
+	{ 0x2e0601b0, 0x2cc0 },	/* 108 */
+	{ 0x2e0601b4, 0x2cc0 },	/* 109 */
+	{ 0x2e0601b8, 0x2cc0 },	/* 110 */
+	{ 0x2e0601c0, 0x4e5 },	/* 112 */
+	{ 0x2e0601c4, 0xff40 },	/* 113 */
+	{ 0x2e0601c8, 0xff40 },	/* 114 */
+	{ 0x2e0601cc, 0xff40 },	/* 115 */
+	{ 0x2e0601d0, 0xff40 },	/* 116 */
+	{ 0x2e0601d4, 0xff40 },	/* 117 */
+	{ 0x2e0601dc, 0x1beb },	/* 119 */
+	{ 0x2e0601e0, 0x200c0 },	/* 120 */
+	{ 0x2e0601e4, 0x200c0 },	/* 121 */
+	{ 0x2e0601e8, 0x200c0 },	/* 122 */
+	{ 0x2e0601ec, 0x200c0 },	/* 123 */
+	{ 0x2e0601f0, 0x200c0 },	/* 124 */
+	{ 0x2e0601f8, 0x3815 },	/* 126 */
+	{ 0x2e06021c, 0x5000000 },	/* 135 */
+	{ 0x2e060220, 0x5030503 },	/* 136 */
+	{ 0x2e060224, 0x3 },	/* 137 */
+	{ 0x2e060228, 0x7010a09 },	/* 138 */
+	{ 0x2e06022c, 0xe0a09 },	/* 139 */
+	{ 0x2e060230, 0x10a0900 },	/* 140 */
+	{ 0x2e060234, 0xe0a0907 },	/* 141 */
+	{ 0x2e060238, 0xa090000 },	/* 142 */
+	{ 0x2e06023c, 0xa090701 },	/* 143 */
+	{ 0x2e060240, 0x101000e },	/* 144 */
+	{ 0x2e060244, 0x40003 },	/* 145 */
+	{ 0x2e060248, 0x7 },	/* 146 */
+	{ 0x2e060264, 0x4040100 },	/* 153 */
+	{ 0x2e060268, 0x1000000 },	/* 154 */
+	{ 0x2e06026c, 0x100000c0 },	/* 155 */
+	{ 0x2e060270, 0x100000c0 },	/* 156 */
+	{ 0x2e060274, 0x100000c0 },	/* 157 */
+	{ 0x2e06027c, 0x1600 },	/* 159 */
+	{ 0x2e060284, 0x1 },	/* 161 */
+	{ 0x2e060288, 0x2 },	/* 162 */
+	{ 0x2e06028c, 0x100e },	/* 163 */
+	{ 0x2e0602a4, 0xa0000 },	/* 169 */
+	{ 0x2e0602a8, 0xd0005 },	/* 170 */
+	{ 0x2e0602ac, 0x404 },	/* 171 */
+	{ 0x2e0602b0, 0xd },	/* 172 */
+	{ 0x2e0602b4, 0x1b0035 },	/* 173 */
+	{ 0x2e0602b8, 0x4040042 },	/* 174 */
+	{ 0x2e0602bc, 0x42 },	/* 175 */
+	{ 0x2e0602c0, 0x35006a },	/* 176 */
+	{ 0x2e0602c4, 0x4040084 },	/* 177 */
+	{ 0x2e0602c8, 0x84 },	/* 178 */
+	{ 0x2e0602d8, 0x40004 },	/* 182 */
+	{ 0x2e0602dc, 0x30000914 },	/* 183 */
+	{ 0x2e0602e0, 0x3030 },	/* 184 */
+	{ 0x2e0602e4, 0x44440000 },	/* 185 */
+	{ 0x2e0602e8, 0x19191944 },	/* 186 */
+	{ 0x2e0602ec, 0x19191908 },	/* 187 */
+	{ 0x2e0602f0, 0x4000000 },	/* 188 */
+	{ 0x2e0602f4, 0x40404 },	/* 189 */
+	{ 0x2e0602f8, 0x9140004 },	/* 190 */
+	{ 0x2e0602fc, 0x30303000 },	/* 191 */
+	{ 0x2e060304, 0x19444444 },	/* 193 */
+	{ 0x2e060308, 0x19081919 },	/* 194 */
+	{ 0x2e06030c, 0x1919 },	/* 195 */
+	{ 0x2e060310, 0x4040400 },	/* 196 */
+	{ 0x2e060314, 0x1010120 },	/* 197 */
+	{ 0x2e060318, 0x1000100 },	/* 198 */
+	{ 0x2e06031c, 0x1 },	/* 199 */
+	{ 0x2e060324, 0x1000000 },	/* 201 */
+	{ 0x2e060328, 0x1 },	/* 202 */
+	{ 0x2e060354, 0x11000000 },	/* 213 */
+	{ 0x2e060358, 0x40c1815 },	/* 214 */
+	{ 0x2e060390, 0x30000 },	/* 228 */
+	{ 0x2e060394, 0x1000200 },	/* 229 */
+	{ 0x2e060398, 0x310040 },	/* 230 */
+	{ 0x2e06039c, 0x20002 },	/* 231 */
+	{ 0x2e0603a0, 0x400100 },	/* 232 */
+	{ 0x2e0603a4, 0x80108 },	/* 233 */
+	{ 0x2e0603a8, 0x1000200 },	/* 234 */
+	{ 0x2e0603ac, 0x2100040 },	/* 235 */
+	{ 0x2e0603b0, 0x10 },	/* 236 */
+	{ 0x2e0603b4, 0xe0003 },	/* 237 */
+	{ 0x2e0603b8, 0x100001b },	/* 238 */
+	{ 0x2e0603d8, 0xffff0b00 },	/* 246 */
+	{ 0x2e0603dc, 0x1010001 },	/* 247 */
+	{ 0x2e0603e0, 0x1010101 },	/* 248 */
+	{ 0x2e0603e4, 0x10b0101 },	/* 249 */
+	{ 0x2e0603e8, 0x10000 },	/* 250 */
+	{ 0x2e0603ec, 0x4010101 },	/* 251 */
+	{ 0x2e0603f0, 0x1010000 },	/* 252 */
+	{ 0x2e0603f4, 0x4 },	/* 253 */
+	{ 0x2e0603fc, 0x3030101 },	/* 255 */
+	{ 0x2e060400, 0x103 },	/* 256 */
+	{ 0x2e0604a4, 0x2020101 },	/* 297 */
+	{ 0x2e0604a8, 0x10100 },	/* 298 */
+	{ 0x2e0604ac, 0x1000101 },	/* 299 */
+	{ 0x2e0604b0, 0x1010101 },	/* 300 */
+	{ 0x2e0604b4, 0x4030300 },	/* 301 */
+	{ 0x2e0604b8, 0x8080505 },	/* 302 */
+	{ 0x2e0604bc, 0x8020808 },	/* 303 */
+	{ 0x2e0604c0, 0x8020e00 },	/* 304 */
+	{ 0x2e0604c4, 0xa020e00 },	/* 305 */
+	{ 0x2e0604c8, 0x8000f00 },	/* 306 */
+	{ 0x2e0604cc, 0xa08 },	/* 307 */
+	{ 0x2e0604d0, 0x1010101 },	/* 308 */
+	{ 0x2e0604d4, 0x102 },	/* 309 */
+	{ 0x2e0604d8, 0x404 },	/* 310 */
+	{ 0x2e0604dc, 0x40400 },	/* 311 */
+	{ 0x2e0604e0, 0x4040000 },	/* 312 */
+	{ 0x2e0604e4, 0x4000000 },	/* 313 */
+	{ 0x2e0604e8, 0x10004 },	/* 314 */
+	{ 0x2e0604f0, 0xfffff },	/* 316 */
+	{ 0x2e0604f8, 0xfffff },	/* 318 */
+	{ 0x2e060500, 0xfffff },	/* 320 */
+	{ 0x2e060508, 0xfffff },	/* 322 */
+	{ 0x2e060510, 0xfffff },	/* 324 */
+	{ 0x2e060518, 0xfffff },	/* 326 */
+	{ 0x2e060520, 0xfffff },	/* 328 */
+	{ 0x2e060528, 0xfffff },	/* 330 */
+	{ 0x2e060530, 0xfffff },	/* 332 */
+	{ 0x2e060538, 0xfffff },	/* 334 */
+	{ 0x2e060540, 0xfffff },	/* 336 */
+	{ 0x2e060548, 0xfffff },	/* 338 */
+	{ 0x2e060550, 0xfffff },	/* 340 */
+	{ 0x2e060558, 0xfffff },	/* 342 */
+	{ 0x2e060560, 0xfffff },	/* 344 */
+	{ 0x2e060568, 0xfffff },	/* 346 */
+	{ 0x2e060570, 0xfffff },	/* 348 */
+	{ 0x2e060578, 0xfffff },	/* 350 */
+	{ 0x2e060580, 0xfffff },	/* 352 */
+	{ 0x2e060588, 0xfffff },	/* 354 */
+	{ 0x2e060590, 0xfffff },	/* 356 */
+	{ 0x2e060598, 0xfffff },	/* 358 */
+	{ 0x2e0605a0, 0xfffff },	/* 360 */
+	{ 0x2e0605a8, 0xfffff },	/* 362 */
+	{ 0x2e0605b0, 0xfffff },	/* 364 */
+	{ 0x2e0605b8, 0xfffff },	/* 366 */
+	{ 0x2e0605c0, 0xfffff },	/* 368 */
+	{ 0x2e0605c8, 0xfffff },	/* 370 */
+	{ 0x2e0605d0, 0xfffff },	/* 372 */
+	{ 0x2e0605d8, 0xfffff },	/* 374 */
+	{ 0x2e0605e0, 0xfffff },	/* 376 */
+	{ 0x2e0605e8, 0xfffff },	/* 378 */
+	{ 0x2e0605f0, 0xfffff },	/* 380 */
+	{ 0x2e0605f8, 0xfffff },	/* 382 */
+	{ 0x2e060600, 0xfffff },	/* 384 */
+	{ 0x2e060608, 0xfffff },	/* 386 */
+	{ 0x2e060610, 0xfffff },	/* 388 */
+	{ 0x2e060618, 0xfffff },	/* 390 */
+	{ 0x2e060620, 0xfffff },	/* 392 */
+	{ 0x2e060628, 0xfffff },	/* 394 */
+	{ 0x2e060630, 0xfffff },	/* 396 */
+	{ 0x2e060638, 0xfffff },	/* 398 */
+	{ 0x2e060640, 0xfffff },	/* 400 */
+	{ 0x2e060648, 0xfffff },	/* 402 */
+	{ 0x2e060650, 0xfffff },	/* 404 */
+	{ 0x2e060658, 0xfffff },	/* 406 */
+	{ 0x2e060660, 0xfffff },	/* 408 */
+	{ 0x2e060668, 0xfffff },	/* 410 */
+	{ 0x2e060670, 0xfffff },	/* 412 */
+	{ 0x2e060678, 0xfffff },	/* 414 */
+	{ 0x2e060680, 0xfffff },	/* 416 */
+	{ 0x2e060688, 0xfffff },	/* 418 */
+	{ 0x2e060690, 0xfffff },	/* 420 */
+	{ 0x2e060698, 0xfffff },	/* 422 */
+	{ 0x2e0606a0, 0xfffff },	/* 424 */
+	{ 0x2e0606a8, 0xfffff },	/* 426 */
+	{ 0x2e0606b0, 0xfffff },	/* 428 */
+	{ 0x2e0606b8, 0xfffff },	/* 430 */
+	{ 0x2e0606c0, 0xfffff },	/* 432 */
+	{ 0x2e0606c8, 0xfffff },	/* 434 */
+	{ 0x2e0606d0, 0xfffff },	/* 436 */
+	{ 0x2e0606d8, 0xfffff },	/* 438 */
+	{ 0x2e0606e0, 0xfffff },	/* 440 */
+	{ 0x2e0606e8, 0x30fffff },	/* 442 */
+	{ 0x2e0606ec, 0xffffffff },	/* 443 */
+	{ 0x2e0606f0, 0x30f0f },	/* 444 */
+	{ 0x2e0606f4, 0xffffffff },	/* 445 */
+	{ 0x2e0606f8, 0x30f0f },	/* 446 */
+	{ 0x2e0606fc, 0xffffffff },	/* 447 */
+	{ 0x2e060700, 0x30f0f },	/* 448 */
+	{ 0x2e060704, 0xffffffff },	/* 449 */
+	{ 0x2e060708, 0x30f0f },	/* 450 */
+	{ 0x2e06070c, 0xffffffff },	/* 451 */
+	{ 0x2e060710, 0x30f0f },	/* 452 */
+	{ 0x2e060714, 0xffffffff },	/* 453 */
+	{ 0x2e060718, 0x30f0f },	/* 454 */
+	{ 0x2e06071c, 0xffffffff },	/* 455 */
+	{ 0x2e060720, 0x30f0f },	/* 456 */
+	{ 0x2e060724, 0xffffffff },	/* 457 */
+	{ 0x2e060728, 0x30f0f },	/* 458 */
+	{ 0x2e06072c, 0xffffffff },	/* 459 */
+	{ 0x2e060730, 0x30f0f },	/* 460 */
+	{ 0x2e060734, 0xffffffff },	/* 461 */
+	{ 0x2e060738, 0x30f0f },	/* 462 */
+	{ 0x2e06073c, 0xffffffff },	/* 463 */
+	{ 0x2e060740, 0x30f0f },	/* 464 */
+	{ 0x2e060744, 0xffffffff },	/* 465 */
+	{ 0x2e060748, 0x30f0f },	/* 466 */
+	{ 0x2e06074c, 0xffffffff },	/* 467 */
+	{ 0x2e060750, 0x30f0f },	/* 468 */
+	{ 0x2e060754, 0xffffffff },	/* 469 */
+	{ 0x2e060758, 0x30f0f },	/* 470 */
+	{ 0x2e06075c, 0xffffffff },	/* 471 */
+	{ 0x2e060760, 0x30f0f },	/* 472 */
+	{ 0x2e060764, 0xffffffff },	/* 473 */
+	{ 0x2e060768, 0x30f0f },	/* 474 */
+	{ 0x2e06076c, 0xffffffff },	/* 475 */
+	{ 0x2e060770, 0x30f0f },	/* 476 */
+	{ 0x2e060774, 0xffffffff },	/* 477 */
+	{ 0x2e060778, 0x30f0f },	/* 478 */
+	{ 0x2e06077c, 0xffffffff },	/* 479 */
+	{ 0x2e060780, 0x30f0f },	/* 480 */
+	{ 0x2e060784, 0xffffffff },	/* 481 */
+	{ 0x2e060788, 0x30f0f },	/* 482 */
+	{ 0x2e06078c, 0xffffffff },	/* 483 */
+	{ 0x2e060790, 0x30f0f },	/* 484 */
+	{ 0x2e060794, 0xffffffff },	/* 485 */
+	{ 0x2e060798, 0x30f0f },	/* 486 */
+	{ 0x2e06079c, 0xffffffff },	/* 487 */
+	{ 0x2e0607a0, 0x30f0f },	/* 488 */
+	{ 0x2e0607a4, 0xffffffff },	/* 489 */
+	{ 0x2e0607a8, 0x30f0f },	/* 490 */
+	{ 0x2e0607ac, 0xffffffff },	/* 491 */
+	{ 0x2e0607b0, 0x30f0f },	/* 492 */
+	{ 0x2e0607b4, 0xffffffff },	/* 493 */
+	{ 0x2e0607b8, 0x30f0f },	/* 494 */
+	{ 0x2e0607bc, 0xffffffff },	/* 495 */
+	{ 0x2e0607c0, 0x30f0f },	/* 496 */
+	{ 0x2e0607c4, 0xffffffff },	/* 497 */
+	{ 0x2e0607c8, 0x30f0f },	/* 498 */
+	{ 0x2e0607cc, 0xffffffff },	/* 499 */
+	{ 0x2e0607d0, 0x30f0f },	/* 500 */
+	{ 0x2e0607d4, 0xffffffff },	/* 501 */
+	{ 0x2e0607d8, 0x30f0f },	/* 502 */
+	{ 0x2e0607dc, 0xffffffff },	/* 503 */
+	{ 0x2e0607e0, 0x30f0f },	/* 504 */
+	{ 0x2e0607e4, 0xffffffff },	/* 505 */
+	{ 0x2e0607e8, 0x30f0f },	/* 506 */
+	{ 0x2e0607ec, 0xffffffff },	/* 507 */
+	{ 0x2e0607f0, 0x30f0f },	/* 508 */
+	{ 0x2e0607f4, 0xffffffff },	/* 509 */
+	{ 0x2e0607f8, 0x30f0f },	/* 510 */
+	{ 0x2e0607fc, 0xffffffff },	/* 511 */
+	{ 0x2e060800, 0x30f0f },	/* 512 */
+	{ 0x2e060804, 0xffffffff },	/* 513 */
+	{ 0x2e060808, 0x30f0f },	/* 514 */
+	{ 0x2e06080c, 0xffffffff },	/* 515 */
+	{ 0x2e060810, 0x30f0f },	/* 516 */
+	{ 0x2e060814, 0xffffffff },	/* 517 */
+	{ 0x2e060818, 0x30f0f },	/* 518 */
+	{ 0x2e06081c, 0xffffffff },	/* 519 */
+	{ 0x2e060820, 0x30f0f },	/* 520 */
+	{ 0x2e060824, 0xffffffff },	/* 521 */
+	{ 0x2e060828, 0x30f0f },	/* 522 */
+	{ 0x2e06082c, 0xffffffff },	/* 523 */
+	{ 0x2e060830, 0x30f0f },	/* 524 */
+	{ 0x2e060834, 0xffffffff },	/* 525 */
+	{ 0x2e060838, 0x30f0f },	/* 526 */
+	{ 0x2e06083c, 0xffffffff },	/* 527 */
+	{ 0x2e060840, 0x30f0f },	/* 528 */
+	{ 0x2e060844, 0xffffffff },	/* 529 */
+	{ 0x2e060848, 0x30f0f },	/* 530 */
+	{ 0x2e06084c, 0xffffffff },	/* 531 */
+	{ 0x2e060850, 0x30f0f },	/* 532 */
+	{ 0x2e060854, 0xffffffff },	/* 533 */
+	{ 0x2e060858, 0x30f0f },	/* 534 */
+	{ 0x2e06085c, 0xffffffff },	/* 535 */
+	{ 0x2e060860, 0x30f0f },	/* 536 */
+	{ 0x2e060864, 0xffffffff },	/* 537 */
+	{ 0x2e060868, 0x30f0f },	/* 538 */
+	{ 0x2e06086c, 0xffffffff },	/* 539 */
+	{ 0x2e060870, 0x30f0f },	/* 540 */
+	{ 0x2e060874, 0xffffffff },	/* 541 */
+	{ 0x2e060878, 0x30f0f },	/* 542 */
+	{ 0x2e06087c, 0xffffffff },	/* 543 */
+	{ 0x2e060880, 0x30f0f },	/* 544 */
+	{ 0x2e060884, 0xffffffff },	/* 545 */
+	{ 0x2e060888, 0x30f0f },	/* 546 */
+	{ 0x2e06088c, 0xffffffff },	/* 547 */
+	{ 0x2e060890, 0x30f0f },	/* 548 */
+	{ 0x2e060894, 0xffffffff },	/* 549 */
+	{ 0x2e060898, 0x30f0f },	/* 550 */
+	{ 0x2e06089c, 0xffffffff },	/* 551 */
+	{ 0x2e0608a0, 0x30f0f },	/* 552 */
+	{ 0x2e0608a4, 0xffffffff },	/* 553 */
+	{ 0x2e0608a8, 0x30f0f },	/* 554 */
+	{ 0x2e0608ac, 0xffffffff },	/* 555 */
+	{ 0x2e0608b0, 0x30f0f },	/* 556 */
+	{ 0x2e0608b4, 0xffffffff },	/* 557 */
+	{ 0x2e0608b8, 0x30f0f },	/* 558 */
+	{ 0x2e0608bc, 0xffffffff },	/* 559 */
+	{ 0x2e0608c0, 0x30f0f },	/* 560 */
+	{ 0x2e0608c4, 0xffffffff },	/* 561 */
+	{ 0x2e0608c8, 0x30f0f },	/* 562 */
+	{ 0x2e0608cc, 0xffffffff },	/* 563 */
+	{ 0x2e0608d0, 0x30f0f },	/* 564 */
+	{ 0x2e0608d4, 0xffffffff },	/* 565 */
+	{ 0x2e0608d8, 0x30f0f },	/* 566 */
+	{ 0x2e0608dc, 0xffffffff },	/* 567 */
+	{ 0x2e0608e0, 0x30f0f },	/* 568 */
+	{ 0x2e0608e4, 0xffffffff },	/* 569 */
+	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
+	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608f0, 0x13200 },	/* 572 */
+	{ 0x2e0608f4, 0x132 },	/* 573 */
+	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
+	{ 0x2e060900, 0x21 },	/* 576 */
+	{ 0x2e060904, 0xa },	/* 577 */
+	{ 0x2e060908, 0x166 },	/* 578 */
+	{ 0x2e06090c, 0x200 },	/* 579 */
+	{ 0x2e060910, 0x200 },	/* 580 */
+	{ 0x2e060914, 0x200 },	/* 581 */
+	{ 0x2e060918, 0x200 },	/* 582 */
+	{ 0x2e06091c, 0x432 },	/* 583 */
+	{ 0x2e060920, 0xdfc },	/* 584 */
+	{ 0x2e060924, 0x204 },	/* 585 */
+	{ 0x2e060928, 0x7fa },	/* 586 */
+	{ 0x2e06092c, 0x200 },	/* 587 */
+	{ 0x2e060930, 0x200 },	/* 588 */
+	{ 0x2e060934, 0x200 },	/* 589 */
+	{ 0x2e060938, 0x200 },	/* 590 */
+	{ 0x2e06093c, 0x17ee },	/* 591 */
+	{ 0x2e060940, 0x4fc4 },	/* 592 */
+	{ 0x2e060944, 0x204 },	/* 593 */
+	{ 0x2e060948, 0x1006 },	/* 594 */
+	{ 0x2e06094c, 0x200 },	/* 595 */
+	{ 0x2e060950, 0x200 },	/* 596 */
+	{ 0x2e060954, 0x200 },	/* 597 */
+	{ 0x2e060958, 0x200 },	/* 598 */
+	{ 0x2e06095c, 0x3012 },	/* 599 */
+	{ 0x2e060960, 0xa03c },	/* 600 */
+	{ 0x2e060964, 0x2020406 },	/* 601 */
+	{ 0x2e060968, 0x2030202 },	/* 602 */
+	{ 0x2e06096c, 0x1000202 },	/* 603 */
+	{ 0x2e060970, 0x3040100 },	/* 604 */
+	{ 0x2e060974, 0x10105 },	/* 605 */
+	{ 0x2e060978, 0x10101 },	/* 606 */
+	{ 0x2e06097c, 0x10101 },	/* 607 */
+	{ 0x2e060980, 0x10001 },	/* 608 */
+	{ 0x2e060984, 0x101 },	/* 609 */
+	{ 0x2e060988, 0x2000201 },	/* 610 */
+	{ 0x2e06098c, 0x2010000 },	/* 611 */
+	{ 0x2e060990, 0x6000200 },	/* 612 */
+	{ 0x2e060994, 0x3000a06 },	/* 613 */
+	{ 0x2e060998, 0x2000c06 },	/* 614 */
+};
+
+/** PI settings **/
+struct dram_cfg_param ddr_pi_cfg[] = {
+	{ 0x2e062000, 0xb00 },	/* 0 */
+	{ 0x2e062004, 0xbeedb66f },	/* 1 */
+	{ 0x2e062008, 0xabef6bd },	/* 2 */
+	{ 0x2e06200c, 0x1001387 },	/* 3 */
+	{ 0x2e062010, 0x1 },	/* 4 */
+	{ 0x2e062014, 0x10064 },	/* 5 */
+	{ 0x2e06202c, 0x101 },	/* 11 */
+	{ 0x2e062030, 0x3 },	/* 12 */
+	{ 0x2e062034, 0x50001 },	/* 13 */
+	{ 0x2e062038, 0x3030800 },	/* 14 */
+	{ 0x2e06203c, 0x1 },	/* 15 */
+	{ 0x2e062040, 0x5 },	/* 16 */
+	{ 0x2e062064, 0x1000000 },	/* 25 */
+	{ 0x2e062068, 0xa000001 },	/* 26 */
+	{ 0x2e06206c, 0x28 },	/* 27 */
+	{ 0x2e062070, 0x1 },	/* 28 */
+	{ 0x2e062074, 0x320005 },	/* 29 */
+	{ 0x2e062080, 0x10102 },	/* 32 */
+	{ 0x2e062084, 0x1 },	/* 33 */
+	{ 0x2e062088, 0xaa },	/* 34 */
+	{ 0x2e06208c, 0x55 },	/* 35 */
+	{ 0x2e062090, 0xb5 },	/* 36 */
+	{ 0x2e062094, 0x4a },	/* 37 */
+	{ 0x2e062098, 0x56 },	/* 38 */
+	{ 0x2e06209c, 0xa9 },	/* 39 */
+	{ 0x2e0620a0, 0xa9 },	/* 40 */
+	{ 0x2e0620a4, 0xb5 },	/* 41 */
+	{ 0x2e0620a8, 0x10000 },	/* 42 */
+	{ 0x2e0620ac, 0x100 },	/* 43 */
+	{ 0x2e0620b0, 0x5050000 },	/* 44 */
+	{ 0x2e0620b4, 0x13 },	/* 45 */
+	{ 0x2e0620b8, 0x7d0 },	/* 46 */
+	{ 0x2e0620bc, 0x300 },	/* 47 */
+	{ 0x2e0620c8, 0x1000000 },	/* 50 */
+	{ 0x2e0620cc, 0x10101 },	/* 51 */
+	{ 0x2e0620d8, 0x10003 },	/* 54 */
+	{ 0x2e0620dc, 0x170500 },	/* 55 */
+	{ 0x2e0620ec, 0xa140a01 },	/* 59 */
+	{ 0x2e0620f0, 0x204010a },	/* 60 */
+	{ 0x2e0620f4, 0x21010 },	/* 61 */
+	{ 0x2e0620f8, 0x40401 },	/* 62 */
+	{ 0x2e0620fc, 0x10e0005 },	/* 63 */
+	{ 0x2e062100, 0x5000001 },	/* 64 */
+	{ 0x2e062104, 0x204 },	/* 65 */
+	{ 0x2e062108, 0x34 },	/* 66 */
+	{ 0x2e062114, 0x1000000 },	/* 69 */
+	{ 0x2e062118, 0x1000000 },	/* 70 */
+	{ 0x2e06211c, 0x80200 },	/* 71 */
+	{ 0x2e062120, 0x2000200 },	/* 72 */
+	{ 0x2e062124, 0x1000100 },	/* 73 */
+	{ 0x2e062128, 0x1000000 },	/* 74 */
+	{ 0x2e06212c, 0x2000200 },	/* 75 */
+	{ 0x2e062130, 0x200 },	/* 76 */
+	{ 0x2e062164, 0x400 },	/* 89 */
+	{ 0x2e062168, 0x2010000 },	/* 90 */
+	{ 0x2e06216c, 0x80103 },	/* 91 */
+	{ 0x2e062174, 0x10008 },	/* 93 */
+	{ 0x2e06217c, 0xaa00 },	/* 95 */
+	{ 0x2e062188, 0x10000 },	/* 98 */
+	{ 0x2e0621ec, 0x8 },	/* 123 */
+	{ 0x2e062218, 0xf0000 },	/* 134 */
+	{ 0x2e06221c, 0xa },	/* 135 */
+	{ 0x2e062220, 0x19 },	/* 136 */
+	{ 0x2e062224, 0x100 },	/* 137 */
+	{ 0x2e062228, 0x100 },	/* 138 */
+	{ 0x2e062238, 0x1000000 },	/* 142 */
+	{ 0x2e06223c, 0x10003 },	/* 143 */
+	{ 0x2e062240, 0x2000101 },	/* 144 */
+	{ 0x2e062244, 0x1030001 },	/* 145 */
+	{ 0x2e062248, 0x10400 },	/* 146 */
+	{ 0x2e06224c, 0x6000105 },	/* 147 */
+	{ 0x2e062250, 0x1070001 },	/* 148 */
+	{ 0x2e062260, 0x10001 },	/* 152 */
+	{ 0x2e062274, 0x401 },	/* 157 */
+	{ 0x2e06227c, 0x10000 },	/* 159 */
+	{ 0x2e062284, 0x6010000 },	/* 161 */
+	{ 0x2e062288, 0xb },	/* 162 */
+	{ 0x2e06228c, 0x34 },	/* 163 */
+	{ 0x2e062290, 0x36 },	/* 164 */
+	{ 0x2e062294, 0x2003c },	/* 165 */
+	{ 0x2e062298, 0x2000200 },	/* 166 */
+	{ 0x2e06229c, 0xc040c04 },	/* 167 */
+	{ 0x2e0622a0, 0xe1406 },	/* 168 */
+	{ 0x2e0622a4, 0xb3 },	/* 169 */
+	{ 0x2e0622a8, 0x4a },	/* 170 */
+	{ 0x2e0622ac, 0x3fd },	/* 171 */
+	{ 0x2e0622b0, 0x94 },	/* 172 */
+	{ 0x2e0622b4, 0x4000803 },	/* 173 */
+	{ 0x2e0622b8, 0x1010404 },	/* 174 */
+	{ 0x2e0622bc, 0x1501 },	/* 175 */
+	{ 0x2e0622c0, 0x1a0018 },	/* 176 */
+	{ 0x2e0622c4, 0x1000100 },	/* 177 */
+	{ 0x2e0622c8, 0x100 },	/* 178 */
+	{ 0x2e0622d0, 0x5040303 },	/* 180 */
+	{ 0x2e0622d4, 0x1010805 },	/* 181 */
+	{ 0x2e0622d8, 0x1010101 },	/* 182 */
+	{ 0x2e0622e8, 0x2060404 },	/* 186 */
+	{ 0x2e0622ec, 0x2020402 },	/* 187 */
+	{ 0x2e0622f0, 0x3102 },	/* 188 */
+	{ 0x2e0622f4, 0x340009 },	/* 189 */
+	{ 0x2e0622f8, 0x36000c },	/* 190 */
+	{ 0x2e0622fc, 0x101000e },	/* 191 */
+	{ 0x2e062300, 0xd0101 },	/* 192 */
+	{ 0x2e062304, 0x1004201 },	/* 193 */
+	{ 0x2e062308, 0x1000084 },	/* 194 */
+	{ 0x2e06230c, 0xe000e },	/* 195 */
+	{ 0x2e062310, 0x430100 },	/* 196 */
+	{ 0x2e062314, 0x1000043 },	/* 197 */
+	{ 0x2e062318, 0x850085 },	/* 198 */
+	{ 0x2e06231c, 0x220f220f },	/* 199 */
+	{ 0x2e062320, 0x101220f },	/* 200 */
+	{ 0x2e062324, 0xa070601 },	/* 201 */
+	{ 0x2e062328, 0xa07060d },	/* 202 */
+	{ 0x2e06232c, 0xa07070d },	/* 203 */
+	{ 0x2e062330, 0xc00d },	/* 204 */
+	{ 0x2e062334, 0xc01000 },	/* 205 */
+	{ 0x2e062338, 0xc01000 },	/* 206 */
+	{ 0x2e06233c, 0x21000 },	/* 207 */
+	{ 0x2e062340, 0x11000d },	/* 208 */
+	{ 0x2e062344, 0x140042 },	/* 209 */
+	{ 0x2e062348, 0x190084 },	/* 210 */
+	{ 0x2e06234c, 0x220f0056 },	/* 211 */
+	{ 0x2e062350, 0x101 },	/* 212 */
+	{ 0x2e062354, 0x560019 },	/* 213 */
+	{ 0x2e062358, 0x101220f },	/* 214 */
+	{ 0x2e06235c, 0x1b00 },	/* 215 */
+	{ 0x2e062360, 0x220f0056 },	/* 216 */
+	{ 0x2e062364, 0x8000101 },	/* 217 */
+	{ 0x2e062368, 0x4090403 },	/* 218 */
+	{ 0x2e06236c, 0x5eb },	/* 219 */
+	{ 0x2e062370, 0x20010003 },	/* 220 */
+	{ 0x2e062374, 0x80a0a03 },	/* 221 */
+	{ 0x2e062378, 0x6090506 },	/* 222 */
+	{ 0x2e06237c, 0x2093 },	/* 223 */
+	{ 0x2e062380, 0x2001000c },	/* 224 */
+	{ 0x2e062384, 0x80a0a04 },	/* 225 */
+	{ 0x2e062388, 0xb090a0c },	/* 226 */
+	{ 0x2e06238c, 0x4126 },	/* 227 */
+	{ 0x2e062390, 0x20020017 },	/* 228 */
+	{ 0x2e062394, 0xa0a08 },	/* 229 */
+	{ 0x2e062398, 0x166 },	/* 230 */
+	{ 0x2e06239c, 0xdfc },	/* 231 */
+	{ 0x2e0623a0, 0x7fa },	/* 232 */
+	{ 0x2e0623a4, 0x4fc4 },	/* 233 */
+	{ 0x2e0623a8, 0x1006 },	/* 234 */
+	{ 0x2e0623ac, 0xa03c },	/* 235 */
+	{ 0x2e0623b0, 0x4c000e },	/* 236 */
+	{ 0x2e0623b4, 0x3030098 },	/* 237 */
+	{ 0x2e0623b8, 0x258103 },	/* 238 */
+	{ 0x2e0623bc, 0x17702 },	/* 239 */
+	{ 0x2e0623c0, 0x5 },	/* 240 */
+	{ 0x2e0623c4, 0x61 },	/* 241 */
+	{ 0x2e0623c8, 0xe },	/* 242 */
+	{ 0x2e0623cc, 0xce3f },	/* 243 */
+	{ 0x2e0623d0, 0x80e70 },	/* 244 */
+	{ 0x2e0623d4, 0x5 },	/* 245 */
+	{ 0x2e0623d8, 0x210 },	/* 246 */
+	{ 0x2e0623dc, 0x4c },	/* 247 */
+	{ 0x2e0623e0, 0x19c7d },	/* 248 */
+	{ 0x2e0623e4, 0x101cdf },	/* 249 */
+	{ 0x2e0623e8, 0x5 },	/* 250 */
+	{ 0x2e0623ec, 0x420 },	/* 251 */
+	{ 0x2e0623f0, 0x1000098 },	/* 252 */
+	{ 0x2e0623f4, 0x310040 },	/* 253 */
+	{ 0x2e0623f8, 0x10002 },	/* 254 */
+	{ 0x2e0623fc, 0x1080040 },	/* 255 */
+	{ 0x2e062400, 0x10008 },	/* 256 */
+	{ 0x2e062404, 0x2100040 },	/* 257 */
+	{ 0x2e062408, 0x310 },	/* 258 */
+	{ 0x2e06240c, 0x1b000e },	/* 259 */
+	{ 0x2e062410, 0x1010101 },	/* 260 */
+	{ 0x2e062414, 0x2020101 },	/* 261 */
+	{ 0x2e062418, 0x8080404 },	/* 262 */
+	{ 0x2e06241c, 0x5508 },	/* 263 */
+	{ 0x2e062420, 0x83c5a00 },	/* 264 */
+	{ 0x2e062424, 0x55 },	/* 265 */
+	{ 0x2e062428, 0x55083c5a },	/* 266 */
+	{ 0x2e06242c, 0x5a000000 },	/* 267 */
+	{ 0x2e062430, 0x55083c },	/* 268 */
+	{ 0x2e062434, 0x3c5a0000 },	/* 269 */
+	{ 0x2e062438, 0xf0e0d0c },	/* 270 */
+	{ 0x2e06243c, 0xb0a0908 },	/* 271 */
+	{ 0x2e062440, 0x7060504 },	/* 272 */
+	{ 0x2e062444, 0x3020100 },	/* 273 */
+	{ 0x2e06244c, 0x2020101 },	/* 275 */
+	{ 0x2e062450, 0x8080404 },	/* 276 */
+	{ 0x2e062454, 0x44300004 },	/* 277 */
+	{ 0x2e062458, 0x4041919 },	/* 278 */
+	{ 0x2e06245c, 0x19443000 },	/* 279 */
+	{ 0x2e062460, 0x9140419 },	/* 280 */
+	{ 0x2e062464, 0x19194430 },	/* 281 */
+	{ 0x2e062468, 0x30000404 },	/* 282 */
+	{ 0x2e06246c, 0x4191944 },	/* 283 */
+	{ 0x2e062470, 0x44300004 },	/* 284 */
+	{ 0x2e062474, 0x14041919 },	/* 285 */
+	{ 0x2e062478, 0x19443009 },	/* 286 */
+	{ 0x2e06247c, 0x40419 },	/* 287 */
+	{ 0x2e062480, 0x19194430 },	/* 288 */
+	{ 0x2e062484, 0x30000404 },	/* 289 */
+	{ 0x2e062488, 0x4191944 },	/* 290 */
+	{ 0x2e06248c, 0x44300914 },	/* 291 */
+	{ 0x2e062490, 0x44041919 },	/* 292 */
+	{ 0x2e062494, 0x19443000 },	/* 293 */
+	{ 0x2e062498, 0x40419 },	/* 294 */
+	{ 0x2e06249c, 0x19194430 },	/* 295 */
+	{ 0x2e0624a0, 0x30091404 },	/* 296 */
+	{ 0x2e0624a4, 0x4191944 },	/* 297 */
+};
+
+/** PHY_F1 settings **/
+struct dram_cfg_param ddr_phy_f1_cfg[] = {
+	{ 0x2e064000, 0x4f0 },	/* 0 */
+	{ 0x2e064008, 0x1030200 },	/* 2 */
+	{ 0x2e064014, 0x3000000 },	/* 5 */
+	{ 0x2e064018, 0x1000001 },	/* 6 */
+	{ 0x2e06401c, 0x3000400 },	/* 7 */
+	{ 0x2e064020, 0x1 },	/* 8 */
+	{ 0x2e064024, 0x1 },	/* 9 */
+	{ 0x2e064030, 0x10000 },	/* 12 */
+	{ 0x2e064038, 0xc00004 },	/* 14 */
+	{ 0x2e06403c, 0xcc0008 },	/* 15 */
+	{ 0x2e064040, 0x660601 },	/* 16 */
+	{ 0x2e064044, 0x3 },	/* 17 */
+	{ 0x2e06404c, 0x1 },	/* 19 */
+	{ 0x2e064050, 0xaaaa },	/* 20 */
+	{ 0x2e064054, 0x5555 },	/* 21 */
+	{ 0x2e064058, 0xb5b5 },	/* 22 */
+	{ 0x2e06405c, 0x4a4a },	/* 23 */
+	{ 0x2e064060, 0x5656 },	/* 24 */
+	{ 0x2e064064, 0xa9a9 },	/* 25 */
+	{ 0x2e064068, 0xb7b7 },	/* 26 */
+	{ 0x2e06406c, 0x4848 },	/* 27 */
+	{ 0x2e064078, 0x8000000 },	/* 30 */
+	{ 0x2e06407c, 0x4010008 },	/* 31 */
+	{ 0x2e064080, 0x408 },	/* 32 */
+	{ 0x2e064084, 0x3102000 },	/* 33 */
+	{ 0x2e064088, 0xc0020 },	/* 34 */
+	{ 0x2e06408c, 0x10000 },	/* 35 */
+	{ 0x2e064090, 0x55555555 },	/* 36 */
+	{ 0x2e064094, 0xaaaaaaaa },	/* 37 */
+	{ 0x2e064098, 0x55555555 },	/* 38 */
+	{ 0x2e06409c, 0xaaaaaaaa },	/* 39 */
+	{ 0x2e0640a0, 0x5555 },	/* 40 */
+	{ 0x2e0640a4, 0x1000100 },	/* 41 */
+	{ 0x2e0640a8, 0x800180 },	/* 42 */
+	{ 0x2e0640ac, 0x1 },	/* 43 */
+	{ 0x2e064100, 0x4 },	/* 64 */
+	{ 0x2e06411c, 0x41f07ff },	/* 71 */
+	{ 0x2e064120, 0x1 },	/* 72 */
+	{ 0x2e064124, 0x1cc0800 },	/* 73 */
+	{ 0x2e064128, 0x3003cc08 },	/* 74 */
+	{ 0x2e06412c, 0x2000014e },	/* 75 */
+	{ 0x2e064130, 0x7ff0200 },	/* 76 */
+	{ 0x2e064134, 0x301 },	/* 77 */
+	{ 0x2e064140, 0x30000 },	/* 80 */
+	{ 0x2e064154, 0x2000000 },	/* 85 */
+	{ 0x2e064158, 0x51515042 },	/* 86 */
+	{ 0x2e06415c, 0x31c06000 },	/* 87 */
+	{ 0x2e064160, 0x6bf000a },	/* 88 */
+	{ 0x2e064164, 0xc0c000 },	/* 89 */
+	{ 0x2e064168, 0x1000000 },	/* 90 */
+	{ 0x2e06416c, 0x10001000 },	/* 91 */
+	{ 0x2e064170, 0xc043242 },	/* 92 */
+	{ 0x2e064174, 0xf0c1201 },	/* 93 */
+	{ 0x2e064178, 0x1000140 },	/* 94 */
+	{ 0x2e06417c, 0xc000120 },	/* 95 */
+	{ 0x2e064180, 0x143 },	/* 96 */
+	{ 0x2e064184, 0x1000203 },	/* 97 */
+	{ 0x2e064188, 0x56417032 },	/* 98 */
+	{ 0x2e06418c, 0x8 },	/* 99 */
+	{ 0x2e064190, 0x2c302c3 },	/* 100 */
+	{ 0x2e064194, 0x2c302c3 },	/* 101 */
+	{ 0x2e064198, 0x2c302c3 },	/* 102 */
+	{ 0x2e06419c, 0x2c302c3 },	/* 103 */
+	{ 0x2e0641a0, 0x2c3 },	/* 104 */
+	{ 0x2e0641a4, 0x8000 },	/* 105 */
+	{ 0x2e0641a8, 0x800080 },	/* 106 */
+	{ 0x2e0641ac, 0x800080 },	/* 107 */
+	{ 0x2e0641b0, 0x800080 },	/* 108 */
+	{ 0x2e0641b4, 0x800080 },	/* 109 */
+	{ 0x2e0641b8, 0x800080 },	/* 110 */
+	{ 0x2e0641bc, 0x800080 },	/* 111 */
+	{ 0x2e0641c0, 0x800080 },	/* 112 */
+	{ 0x2e0641c4, 0x800080 },	/* 113 */
+	{ 0x2e0641c8, 0x6b0080 },	/* 114 */
+	{ 0x2e0641cc, 0x1a00001 },	/* 115 */
+	{ 0x2e0641d4, 0x10000 },	/* 117 */
+	{ 0x2e0641d8, 0x80200 },	/* 118 */
+	{ 0x2e064400, 0x4f0 },	/* 256 */
+	{ 0x2e064408, 0x1030200 },	/* 258 */
+	{ 0x2e064414, 0x3000000 },	/* 261 */
+	{ 0x2e064418, 0x1000001 },	/* 262 */
+	{ 0x2e06441c, 0x3000400 },	/* 263 */
+	{ 0x2e064420, 0x1 },	/* 264 */
+	{ 0x2e064424, 0x1 },	/* 265 */
+	{ 0x2e064430, 0x10000 },	/* 268 */
+	{ 0x2e064438, 0xc00004 },	/* 270 */
+	{ 0x2e06443c, 0xcc0008 },	/* 271 */
+	{ 0x2e064440, 0x660601 },	/* 272 */
+	{ 0x2e064444, 0x3 },	/* 273 */
+	{ 0x2e06444c, 0x1 },	/* 275 */
+	{ 0x2e064450, 0xaaaa },	/* 276 */
+	{ 0x2e064454, 0x5555 },	/* 277 */
+	{ 0x2e064458, 0xb5b5 },	/* 278 */
+	{ 0x2e06445c, 0x4a4a },	/* 279 */
+	{ 0x2e064460, 0x5656 },	/* 280 */
+	{ 0x2e064464, 0xa9a9 },	/* 281 */
+	{ 0x2e064468, 0xb7b7 },	/* 282 */
+	{ 0x2e06446c, 0x4848 },	/* 283 */
+	{ 0x2e064478, 0x8000000 },	/* 286 */
+	{ 0x2e06447c, 0x4010008 },	/* 287 */
+	{ 0x2e064480, 0x408 },	/* 288 */
+	{ 0x2e064484, 0x3102000 },	/* 289 */
+	{ 0x2e064488, 0xc0020 },	/* 290 */
+	{ 0x2e06448c, 0x10000 },	/* 291 */
+	{ 0x2e064490, 0x55555555 },	/* 292 */
+	{ 0x2e064494, 0xaaaaaaaa },	/* 293 */
+	{ 0x2e064498, 0x55555555 },	/* 294 */
+	{ 0x2e06449c, 0xaaaaaaaa },	/* 295 */
+	{ 0x2e0644a0, 0x5555 },	/* 296 */
+	{ 0x2e0644a4, 0x1000100 },	/* 297 */
+	{ 0x2e0644a8, 0x800180 },	/* 298 */
+	{ 0x2e064500, 0x4 },	/* 320 */
+	{ 0x2e06451c, 0x41f07ff },	/* 327 */
+	{ 0x2e064520, 0x1 },	/* 328 */
+	{ 0x2e064524, 0x1cc0800 },	/* 329 */
+	{ 0x2e064528, 0x3003cc08 },	/* 330 */
+	{ 0x2e06452c, 0x2000014e },	/* 331 */
+	{ 0x2e064530, 0x7ff0200 },	/* 332 */
+	{ 0x2e064534, 0x301 },	/* 333 */
+	{ 0x2e064540, 0x30000 },	/* 336 */
+	{ 0x2e064554, 0x2000000 },	/* 341 */
+	{ 0x2e064558, 0x51515042 },	/* 342 */
+	{ 0x2e06455c, 0x31c06000 },	/* 343 */
+	{ 0x2e064560, 0x6bf000a },	/* 344 */
+	{ 0x2e064564, 0xc0c000 },	/* 345 */
+	{ 0x2e064568, 0x1000000 },	/* 346 */
+	{ 0x2e06456c, 0x10001000 },	/* 347 */
+	{ 0x2e064570, 0xc043242 },	/* 348 */
+	{ 0x2e064574, 0xf0c1201 },	/* 349 */
+	{ 0x2e064578, 0x1000140 },	/* 350 */
+	{ 0x2e06457c, 0xc000120 },	/* 351 */
+	{ 0x2e064580, 0x143 },	/* 352 */
+	{ 0x2e064584, 0x1000203 },	/* 353 */
+	{ 0x2e064588, 0x30217465 },	/* 354 */
+	{ 0x2e06458c, 0x8 },	/* 355 */
+	{ 0x2e064590, 0x2c302c3 },	/* 356 */
+	{ 0x2e064594, 0x2c302c3 },	/* 357 */
+	{ 0x2e064598, 0x2c302c3 },	/* 358 */
+	{ 0x2e06459c, 0x2c302c3 },	/* 359 */
+	{ 0x2e0645a0, 0x2c3 },	/* 360 */
+	{ 0x2e0645a4, 0x8000 },	/* 361 */
+	{ 0x2e0645a8, 0x800080 },	/* 362 */
+	{ 0x2e0645ac, 0x800080 },	/* 363 */
+	{ 0x2e0645b0, 0x800080 },	/* 364 */
+	{ 0x2e0645b4, 0x800080 },	/* 365 */
+	{ 0x2e0645b8, 0x800080 },	/* 366 */
+	{ 0x2e0645bc, 0x800080 },	/* 367 */
+	{ 0x2e0645c0, 0x800080 },	/* 368 */
+	{ 0x2e0645c4, 0x800080 },	/* 369 */
+	{ 0x2e0645c8, 0x6b0080 },	/* 370 */
+	{ 0x2e0645cc, 0x1a00001 },	/* 371 */
+	{ 0x2e0645d4, 0x10000 },	/* 373 */
+	{ 0x2e0645d8, 0x80200 },	/* 374 */
+	{ 0x2e064800, 0x4f0 },	/* 512 */
+	{ 0x2e064808, 0x1030200 },	/* 514 */
+	{ 0x2e064814, 0x3000000 },	/* 517 */
+	{ 0x2e064818, 0x1000001 },	/* 518 */
+	{ 0x2e06481c, 0x3000400 },	/* 519 */
+	{ 0x2e064820, 0x1 },	/* 520 */
+	{ 0x2e064824, 0x1 },	/* 521 */
+	{ 0x2e064830, 0x10000 },	/* 524 */
+	{ 0x2e064838, 0xc00004 },	/* 526 */
+	{ 0x2e06483c, 0xcc0008 },	/* 527 */
+	{ 0x2e064840, 0x660601 },	/* 528 */
+	{ 0x2e064844, 0x3 },	/* 529 */
+	{ 0x2e06484c, 0x1 },	/* 531 */
+	{ 0x2e064850, 0xaaaa },	/* 532 */
+	{ 0x2e064854, 0x5555 },	/* 533 */
+	{ 0x2e064858, 0xb5b5 },	/* 534 */
+	{ 0x2e06485c, 0x4a4a },	/* 535 */
+	{ 0x2e064860, 0x5656 },	/* 536 */
+	{ 0x2e064864, 0xa9a9 },	/* 537 */
+	{ 0x2e064868, 0xb7b7 },	/* 538 */
+	{ 0x2e06486c, 0x4848 },	/* 539 */
+	{ 0x2e064878, 0x8000000 },	/* 542 */
+	{ 0x2e06487c, 0x4010008 },	/* 543 */
+	{ 0x2e064880, 0x408 },	/* 544 */
+	{ 0x2e064884, 0x3102000 },	/* 545 */
+	{ 0x2e064888, 0xc0020 },	/* 546 */
+	{ 0x2e06488c, 0x10000 },	/* 547 */
+	{ 0x2e064890, 0x55555555 },	/* 548 */
+	{ 0x2e064894, 0xaaaaaaaa },	/* 549 */
+	{ 0x2e064898, 0x55555555 },	/* 550 */
+	{ 0x2e06489c, 0xaaaaaaaa },	/* 551 */
+	{ 0x2e0648a0, 0x5555 },	/* 552 */
+	{ 0x2e0648a4, 0x1000100 },	/* 553 */
+	{ 0x2e0648a8, 0x800180 },	/* 554 */
+	{ 0x2e0648ac, 0x1 },	/* 555 */
+	{ 0x2e064900, 0x4 },	/* 576 */
+	{ 0x2e06491c, 0x41f07ff },	/* 583 */
+	{ 0x2e064920, 0x1 },	/* 584 */
+	{ 0x2e064924, 0x1cc0800 },	/* 585 */
+	{ 0x2e064928, 0x3003cc08 },	/* 586 */
+	{ 0x2e06492c, 0x2000014e },	/* 587 */
+	{ 0x2e064930, 0x7ff0200 },	/* 588 */
+	{ 0x2e064934, 0x301 },	/* 589 */
+	{ 0x2e064940, 0x30000 },	/* 592 */
+	{ 0x2e064954, 0x2000000 },	/* 597 */
+	{ 0x2e064958, 0x51515042 },	/* 598 */
+	{ 0x2e06495c, 0x31c06000 },	/* 599 */
+	{ 0x2e064960, 0x6bf000a },	/* 600 */
+	{ 0x2e064964, 0xc0c000 },	/* 601 */
+	{ 0x2e064968, 0x1000000 },	/* 602 */
+	{ 0x2e06496c, 0x10001000 },	/* 603 */
+	{ 0x2e064970, 0xc043242 },	/* 604 */
+	{ 0x2e064974, 0xf0c1201 },	/* 605 */
+	{ 0x2e064978, 0x1000140 },	/* 606 */
+	{ 0x2e06497c, 0xc000120 },	/* 607 */
+	{ 0x2e064980, 0x143 },	/* 608 */
+	{ 0x2e064984, 0x1000203 },	/* 609 */
+	{ 0x2e064988, 0x75436012 },	/* 610 */
+	{ 0x2e06498c, 0x8 },	/* 611 */
+	{ 0x2e064990, 0x2c302c3 },	/* 612 */
+	{ 0x2e064994, 0x2c302c3 },	/* 613 */
+	{ 0x2e064998, 0x2c302c3 },	/* 614 */
+	{ 0x2e06499c, 0x2c302c3 },	/* 615 */
+	{ 0x2e0649a0, 0x2c3 },	/* 616 */
+	{ 0x2e0649a4, 0x8000 },	/* 617 */
+	{ 0x2e0649a8, 0x800080 },	/* 618 */
+	{ 0x2e0649ac, 0x800080 },	/* 619 */
+	{ 0x2e0649b0, 0x800080 },	/* 620 */
+	{ 0x2e0649b4, 0x800080 },	/* 621 */
+	{ 0x2e0649b8, 0x800080 },	/* 622 */
+	{ 0x2e0649bc, 0x800080 },	/* 623 */
+	{ 0x2e0649c0, 0x800080 },	/* 624 */
+	{ 0x2e0649c4, 0x800080 },	/* 625 */
+	{ 0x2e0649c8, 0x6b0080 },	/* 626 */
+	{ 0x2e0649cc, 0x1a00001 },	/* 627 */
+	{ 0x2e0649d4, 0x10000 },	/* 629 */
+	{ 0x2e0649d8, 0x80200 },	/* 630 */
+	{ 0x2e064c00, 0x4f0 },	/* 768 */
+	{ 0x2e064c08, 0x1030200 },	/* 770 */
+	{ 0x2e064c14, 0x3000000 },	/* 773 */
+	{ 0x2e064c18, 0x1000001 },	/* 774 */
+	{ 0x2e064c1c, 0x3000400 },	/* 775 */
+	{ 0x2e064c20, 0x1 },	/* 776 */
+	{ 0x2e064c24, 0x1 },	/* 777 */
+	{ 0x2e064c30, 0x10000 },	/* 780 */
+	{ 0x2e064c38, 0xc00004 },	/* 782 */
+	{ 0x2e064c3c, 0xcc0008 },	/* 783 */
+	{ 0x2e064c40, 0x660601 },	/* 784 */
+	{ 0x2e064c44, 0x3 },	/* 785 */
+	{ 0x2e064c4c, 0x1 },	/* 787 */
+	{ 0x2e064c50, 0xaaaa },	/* 788 */
+	{ 0x2e064c54, 0x5555 },	/* 789 */
+	{ 0x2e064c58, 0xb5b5 },	/* 790 */
+	{ 0x2e064c5c, 0x4a4a },	/* 791 */
+	{ 0x2e064c60, 0x5656 },	/* 792 */
+	{ 0x2e064c64, 0xa9a9 },	/* 793 */
+	{ 0x2e064c68, 0xb7b7 },	/* 794 */
+	{ 0x2e064c6c, 0x4848 },	/* 795 */
+	{ 0x2e064c78, 0x8000000 },	/* 798 */
+	{ 0x2e064c7c, 0x4010008 },	/* 799 */
+	{ 0x2e064c80, 0x408 },	/* 800 */
+	{ 0x2e064c84, 0x3102000 },	/* 801 */
+	{ 0x2e064c88, 0xc0020 },	/* 802 */
+	{ 0x2e064c8c, 0x10000 },	/* 803 */
+	{ 0x2e064c90, 0x55555555 },	/* 804 */
+	{ 0x2e064c94, 0xaaaaaaaa },	/* 805 */
+	{ 0x2e064c98, 0x55555555 },	/* 806 */
+	{ 0x2e064c9c, 0xaaaaaaaa },	/* 807 */
+	{ 0x2e064ca0, 0x5555 },	/* 808 */
+	{ 0x2e064ca4, 0x1000100 },	/* 809 */
+	{ 0x2e064ca8, 0x800180 },	/* 810 */
+	{ 0x2e064d00, 0x4 },	/* 832 */
+	{ 0x2e064d1c, 0x41f07ff },	/* 839 */
+	{ 0x2e064d20, 0x1 },	/* 840 */
+	{ 0x2e064d24, 0x1cc0800 },	/* 841 */
+	{ 0x2e064d28, 0x3003cc08 },	/* 842 */
+	{ 0x2e064d2c, 0x2000014e },	/* 843 */
+	{ 0x2e064d30, 0x7ff0200 },	/* 844 */
+	{ 0x2e064d34, 0x301 },	/* 845 */
+	{ 0x2e064d40, 0x30000 },	/* 848 */
+	{ 0x2e064d54, 0x2000000 },	/* 853 */
+	{ 0x2e064d58, 0x51515042 },	/* 854 */
+	{ 0x2e064d5c, 0x31c06000 },	/* 855 */
+	{ 0x2e064d60, 0x6bf000a },	/* 856 */
+	{ 0x2e064d64, 0xc0c000 },	/* 857 */
+	{ 0x2e064d68, 0x1000000 },	/* 858 */
+	{ 0x2e064d6c, 0x10001000 },	/* 859 */
+	{ 0x2e064d70, 0xc043242 },	/* 860 */
+	{ 0x2e064d74, 0xf0c1201 },	/* 861 */
+	{ 0x2e064d78, 0x1000140 },	/* 862 */
+	{ 0x2e064d7c, 0xc000120 },	/* 863 */
+	{ 0x2e064d80, 0x143 },	/* 864 */
+	{ 0x2e064d84, 0x1000203 },	/* 865 */
+	{ 0x2e064d88, 0x32017465 },	/* 866 */
+	{ 0x2e064d8c, 0x8 },	/* 867 */
+	{ 0x2e064d90, 0x2c302c3 },	/* 868 */
+	{ 0x2e064d94, 0x2c302c3 },	/* 869 */
+	{ 0x2e064d98, 0x2c302c3 },	/* 870 */
+	{ 0x2e064d9c, 0x2c302c3 },	/* 871 */
+	{ 0x2e064da0, 0x2c3 },	/* 872 */
+	{ 0x2e064da4, 0x8000 },	/* 873 */
+	{ 0x2e064da8, 0x800080 },	/* 874 */
+	{ 0x2e064dac, 0x800080 },	/* 875 */
+	{ 0x2e064db0, 0x800080 },	/* 876 */
+	{ 0x2e064db4, 0x800080 },	/* 877 */
+	{ 0x2e064db8, 0x800080 },	/* 878 */
+	{ 0x2e064dbc, 0x800080 },	/* 879 */
+	{ 0x2e064dc0, 0x800080 },	/* 880 */
+	{ 0x2e064dc4, 0x800080 },	/* 881 */
+	{ 0x2e064dc8, 0x6b0080 },	/* 882 */
+	{ 0x2e064dcc, 0x1a00001 },	/* 883 */
+	{ 0x2e064dd4, 0x10000 },	/* 885 */
+	{ 0x2e064dd8, 0x80200 },	/* 886 */
+	{ 0x2e065014, 0x100 },	/* 1029 */
+	{ 0x2e065018, 0x201 },	/* 1030 */
+	{ 0x2e06502c, 0x400000 },	/* 1035 */
+	{ 0x2e065030, 0x80 },	/* 1036 */
+	{ 0x2e065034, 0xdcba98 },	/* 1037 */
+	{ 0x2e065038, 0x3000000 },	/* 1038 */
+	{ 0x2e06504c, 0x2a },	/* 1043 */
+	{ 0x2e065050, 0x15 },	/* 1044 */
+	{ 0x2e065054, 0x15 },	/* 1045 */
+	{ 0x2e065058, 0x2a },	/* 1046 */
+	{ 0x2e06505c, 0x33 },	/* 1047 */
+	{ 0x2e065060, 0xc },	/* 1048 */
+	{ 0x2e065064, 0xc },	/* 1049 */
+	{ 0x2e065068, 0x33 },	/* 1050 */
+	{ 0x2e06506c, 0x543210 },	/* 1051 */
+	{ 0x2e065070, 0x3f0000 },	/* 1052 */
+	{ 0x2e065074, 0xf013f },	/* 1053 */
+	{ 0x2e065078, 0xf },	/* 1054 */
+	{ 0x2e06507c, 0x3cc },	/* 1055 */
+	{ 0x2e065080, 0x30000 },	/* 1056 */
+	{ 0x2e065084, 0x300 },	/* 1057 */
+	{ 0x2e065088, 0x300 },	/* 1058 */
+	{ 0x2e06508c, 0x300 },	/* 1059 */
+	{ 0x2e065090, 0x300 },	/* 1060 */
+	{ 0x2e065094, 0x300 },	/* 1061 */
+	{ 0x2e065098, 0x42080010 },	/* 1062 */
+	{ 0x2e06509c, 0x332 },	/* 1063 */
+	{ 0x2e0650a0, 0x2 },	/* 1064 */
+	{ 0x2e065414, 0x100 },	/* 1285 */
+	{ 0x2e065418, 0x201 },	/* 1286 */
+	{ 0x2e06542c, 0x400000 },	/* 1291 */
+	{ 0x2e065430, 0x80 },	/* 1292 */
+	{ 0x2e065434, 0xdcba98 },	/* 1293 */
+	{ 0x2e065438, 0x3000000 },	/* 1294 */
+	{ 0x2e06544c, 0x2a },	/* 1299 */
+	{ 0x2e065450, 0x15 },	/* 1300 */
+	{ 0x2e065454, 0x15 },	/* 1301 */
+	{ 0x2e065458, 0x2a },	/* 1302 */
+	{ 0x2e06545c, 0x33 },	/* 1303 */
+	{ 0x2e065460, 0xc },	/* 1304 */
+	{ 0x2e065464, 0xc },	/* 1305 */
+	{ 0x2e065468, 0x33 },	/* 1306 */
+	{ 0x2e06546c, 0x543210 },	/* 1307 */
+	{ 0x2e065470, 0x3f0000 },	/* 1308 */
+	{ 0x2e065474, 0xf013f },	/* 1309 */
+	{ 0x2e065478, 0xf },	/* 1310 */
+	{ 0x2e06547c, 0x3cc },	/* 1311 */
+	{ 0x2e065480, 0x30000 },	/* 1312 */
+	{ 0x2e065484, 0x300 },	/* 1313 */
+	{ 0x2e065488, 0x300 },	/* 1314 */
+	{ 0x2e06548c, 0x300 },	/* 1315 */
+	{ 0x2e065490, 0x300 },	/* 1316 */
+	{ 0x2e065494, 0x300 },	/* 1317 */
+	{ 0x2e065498, 0x42080010 },	/* 1318 */
+	{ 0x2e06549c, 0x332 },	/* 1319 */
+	{ 0x2e0654a0, 0x2 },	/* 1320 */
+	{ 0x2e065804, 0x100 },	/* 1537 */
+	{ 0x2e065814, 0x50000 },	/* 1541 */
+	{ 0x2e065818, 0x4000100 },	/* 1542 */
+	{ 0x2e06581c, 0x55 },	/* 1543 */
+	{ 0x2e06582c, 0xf0001 },	/* 1547 */
+	{ 0x2e065830, 0x280040 },	/* 1548 */
+	{ 0x2e065834, 0x5002 },	/* 1549 */
+	{ 0x2e065838, 0x10101 },	/* 1550 */
+	{ 0x2e065840, 0x90e0000 },	/* 1552 */
+	{ 0x2e065844, 0x101010f },	/* 1553 */
+	{ 0x2e065848, 0x10f0004 },	/* 1554 */
+	{ 0x2e065854, 0x64 },	/* 1557 */
+	{ 0x2e06585c, 0x1000000 },	/* 1559 */
+	{ 0x2e065860, 0x8040201 },	/* 1560 */
+	{ 0x2e065864, 0x2010201 },	/* 1561 */
+	{ 0x2e065868, 0xf0f0f },	/* 1562 */
+	{ 0x2e06586c, 0x241342 },	/* 1563 */
+	{ 0x2e065874, 0x1020000 },	/* 1565 */
+	{ 0x2e065878, 0x701 },	/* 1566 */
+	{ 0x2e06587c, 0x54 },	/* 1567 */
+	{ 0x2e065880, 0x4102000 },	/* 1568 */
+	{ 0x2e065884, 0x24410 },	/* 1569 */
+	{ 0x2e065888, 0x4410 },	/* 1570 */
+	{ 0x2e06588c, 0x4410 },	/* 1571 */
+	{ 0x2e065890, 0x4410 },	/* 1572 */
+	{ 0x2e065894, 0x4410 },	/* 1573 */
+	{ 0x2e065898, 0x4410 },	/* 1574 */
+	{ 0x2e06589c, 0x4410 },	/* 1575 */
+	{ 0x2e0658a0, 0x4410 },	/* 1576 */
+	{ 0x2e0658a4, 0x4410 },	/* 1577 */
+	{ 0x2e0658b0, 0x60000 },	/* 1580 */
+	{ 0x2e0658b8, 0x66 },	/* 1582 */
+	{ 0x2e0658bc, 0x10000 },	/* 1583 */
+	{ 0x2e0658c0, 0x8 },	/* 1584 */
+	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
+	{ 0x2e0658e8, 0x4102006 },	/* 1594 */
+	{ 0x2e0658ec, 0x41020 },	/* 1595 */
+	{ 0x2e0658f0, 0x1c98c98 },	/* 1596 */
+	{ 0x2e0658f4, 0x3f400000 },	/* 1597 */
+	{ 0x2e0658f8, 0x3f3f1f3f },	/* 1598 */
+	{ 0x2e0658fc, 0x1f },	/* 1599 */
+	{ 0x2e06590c, 0x1 },	/* 1603 */
+	{ 0x2e06591c, 0x1 },	/* 1607 */
+	{ 0x2e065920, 0x76543210 },	/* 1608 */
+	{ 0x2e065924, 0x10198 },	/* 1609 */
+	{ 0x2e065934, 0x40700 },	/* 1613 */
+	{ 0x2e06594c, 0x2 },	/* 1619 */
+	{ 0x2e065958, 0xf3c3 },	/* 1622 */
+	{ 0x2e065964, 0x11542 },	/* 1625 */
+	{ 0x2e065968, 0x30209bf },	/* 1626 */
+	{ 0x2e06596c, 0x30000 },	/* 1627 */
+	{ 0x2e065970, 0x3000300 },	/* 1628 */
+	{ 0x2e065974, 0x3000300 },	/* 1629 */
+	{ 0x2e065978, 0x3000300 },	/* 1630 */
+	{ 0x2e06597c, 0x3000300 },	/* 1631 */
+	{ 0x2e065980, 0x300 },	/* 1632 */
+	{ 0x2e065984, 0x300 },	/* 1633 */
+	{ 0x2e065988, 0x300 },	/* 1634 */
+	{ 0x2e06598c, 0x337cc },	/* 1635 */
+	{ 0x2e065990, 0x8 },	/* 1636 */
+	{ 0x2e065994, 0x1b7 },	/* 1637 */
+	{ 0x2e06599c, 0x1b7 },	/* 1639 */
+	{ 0x2e0659a4, 0x1b700 },	/* 1641 */
+	{ 0x2e0659a8, 0x1980000 },	/* 1642 */
+	{ 0x2e0659ac, 0x1b7cc },	/* 1643 */
+	{ 0x2e0659b4, 0x1b700 },	/* 1645 */
+	{ 0x2e0659b8, 0x1980000 },	/* 1646 */
+	{ 0x2e0659bc, 0x1b700 },	/* 1647 */
+	{ 0x2e0659c0, 0x1980000 },	/* 1648 */
+	{ 0x2e0659c4, 0x1b700 },	/* 1649 */
+	{ 0x2e0659c8, 0x1980000 },	/* 1650 */
+	{ 0x2e0659cc, 0x1b700 },	/* 1651 */
+	{ 0x2e0659d0, 0x1980000 },	/* 1652 */
+	{ 0x2e0659d4, 0x20040003 },	/* 1653 */
+};
+
+/** PHY_F2 settings **/
+struct dram_cfg_param ddr_phy_f2_cfg[] = {
+};
+
+/* ddr timing config params */
+struct dram_timing_info2 dram_timing = {
+	.ctl_cfg = ddr_ctl_cfg,
+	.ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg),
+	.pi_cfg = ddr_pi_cfg,
+	.pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg),
+	.phy_f1_cfg = ddr_phy_f1_cfg,
+	.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
+	.phy_f2_cfg = ddr_phy_f2_cfg,
+	.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
+	.fsp_table = { 96, 528 },
+};
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index b3149014098..d3cdad2d76a 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -35,8 +35,17 @@ u32 spl_boot_device(void)
 
 int power_init_board(void)
 {
-	/* Set buck3 to 1.1v OD */
-	upower_pmic_i2c_write(0x22, 0x28);
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		/* Set buck3 to 0.9v LD */
+		upower_pmic_i2c_write(0x22, 0x18);
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		/* Set buck3 to 1.0v ND */
+		upower_pmic_i2c_write(0x22, 0x20);
+	} else {
+		/* Set buck3 to 1.1v OD */
+		upower_pmic_i2c_write(0x22, 0x28);
+	}
+
 	return 0;
 }
 
@@ -69,6 +78,8 @@ void spl_board_init(void)
 
 	power_init_board();
 
+	clock_init_late();
+
 	/* DDR initialization */
 	spl_dram_init();
 
-- 
2.35.1

[PATCH V2 07/26] imx: imx8ulp: add ND/LD clock

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Add a new ddr script, defconfig for ND
> Configure the clock for ND mode
> changing A35 to 960MHz for OD mode
> Update NIC CLK for the various modes
> Introduce clock_init_early/late, late is used after pmic voltage
> setting, early is used in the very early stage for upower mu, lpuart and
> etc.
> Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
> cpuidle enabled now.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 08/26] imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/cgc.h |  2 +-
 arch/arm/mach-imx/imx8ulp/cgc.c         | 20 +++++++++++---------
 arch/arm/mach-imx/imx8ulp/clock.c       |  2 +-
 board/freescale/imx8ulp_evk/spl.c       | 12 ++++++++++--
 4 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index e45f04624db..83a246b15a7 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -150,7 +150,7 @@ void cgc1_pll3_init(ulong freq);
 void cgc1_pll2_init(ulong freq);
 void cgc1_soscdiv_init(void);
 void cgc1_init_core_clk(ulong freq);
-void cgc2_pll4_init(void);
+void cgc2_pll4_init(bool pll4_reset);
 void cgc2_ddrclk_config(u32 src, u32 div);
 void cgc2_ddrclk_wait_unlock(void);
 u32 cgc1_sosc_div(enum cgc_clk clk);
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 494ddb0f329..ccd977f1a5d 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -187,7 +187,7 @@ void cgc1_pll3_init(ulong freq)
 	}
 }
 
-void cgc2_pll4_init(void)
+void cgc2_pll4_init(bool pll4_reset)
 {
 	/* Disable PFD DIV and clear DIV */
 	writel(0x80808080, &cgc2_regs->pll4div_pfd0);
@@ -196,16 +196,18 @@ void cgc2_pll4_init(void)
 	/* Gate off and clear PFD  */
 	writel(0x80808080, &cgc2_regs->pll4pfdcfg);
 
-	/* Disable PLL4 */
-	writel(0x0, &cgc2_regs->pll4csr);
+	if (pll4_reset) {
+		/* Disable PLL4 */
+		writel(0x0, &cgc2_regs->pll4csr);
 
-	/* Configure PLL4 to 528Mhz and clock source from SOSC */
-	writel(22 << 16, &cgc2_regs->pll4cfg);
-	writel(0x1, &cgc2_regs->pll4csr);
+		/* Configure PLL4 to 528Mhz and clock source from SOSC */
+		writel(22 << 16, &cgc2_regs->pll4cfg);
+		writel(0x1, &cgc2_regs->pll4csr);
 
-	/* wait for PLL4 output valid */
-	while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
-		;
+		/* wait for PLL4 output valid */
+		while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
+			;
+	}
 
 	/* Enable all 4 PFDs */
 	setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 46971578a91..69cccafbcef 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -101,7 +101,7 @@ void init_clk_ddr(void)
 	writel(0xc0000000, PCC5_LPDDR4_ADDR);
 
 	/* enable pll4 and ddrclk*/
-	cgc2_pll4_init();
+	cgc2_pll4_init(true);
 	cgc2_ddrclk_config(4, 1);
 
 	/* enable ddr pcc */
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index d3cdad2d76a..e6949b5e431 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -24,8 +24,16 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void spl_dram_init(void)
 {
-	init_clk_ddr();
-	ddr_init(&dram_timing);
+	/* Reboot in dual boot setting no need to init ddr again */
+	bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT);
+
+	if (!ddr_enable) {
+		init_clk_ddr();
+		ddr_init(&dram_timing);
+	} else {
+		/* reinit pfd/pfddiv and lpavnic except pll4*/
+		cgc2_pll4_init(false);
+	}
 }
 
 u32 spl_boot_device(void)
-- 
2.35.1

[PATCH V2 08/26] imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
> during APD reset. So no need to init DDR again after reboot, but need to
> reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
> change or disable some of them.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 09/26] imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

When reset with dual boot mode, the LPAV domain won't power down
due to its master is not assigned to APD. So the NICLPAV keeps the
last setting to use PLL4PFD1. So before SPL initialize the PLL4,
we need to switch NICLPAV to FRO192, otherwise system will hang.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/cgc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index ccd977f1a5d..d240abaee46 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -189,6 +189,14 @@ void cgc1_pll3_init(ulong freq)
 
 void cgc2_pll4_init(bool pll4_reset)
 {
+	/* Check the NICLPAV first to ensure not from PLL4 PFD1 clock */
+	if ((readl(&cgc2_regs->niclpavclk) & GENMASK(29, 28)) == BIT(28)) {
+		/* switch to FRO 192 first */
+		clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28));
+		while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+			;
+	}
+
 	/* Disable PFD DIV and clear DIV */
 	writel(0x80808080, &cgc2_regs->pll4div_pfd0);
 	writel(0x80808080, &cgc2_regs->pll4div_pfd1);
-- 
2.35.1

[PATCH V2 09/26] imx: imx8ulp: cgc: Switch to NICLPAV to FRO192 before PLL4 init

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> When reset with dual boot mode, the LPAV domain won't power down
> due to its master is not assigned to APD. So the NICLPAV keeps the
> last setting to use PLL4PFD1. So before SPL initialize the PLL4,
> we need to switch NICLPAV to FRO192, otherwise system will hang.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 10/26] imx: imx8ulp: enable MU0_B clk by default

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Enable MU0_B clk by default. When M33 image is loaded by Jlink,
the previous method not enable MU0_B clk and not able to communicate
with M33, so let's enable it by default.

And we not put it under kernel dts, because it conflicts with i.MX8QM
suspend/resume logic which requires large change.

Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/clock.c | 3 +++
 arch/arm/mach-imx/imx8ulp/soc.c   | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 69cccafbcef..3e71a4f6c3b 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -214,6 +214,9 @@ void clock_init_late(void)
 		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
 	}
 
+	/* enable MU0_MUB clock before access the register of MU0_MUB */
+	pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
+
 	/*
 	 * Enable clock division
 	 * TODO: may not needed after ROM ready.
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 85bf57b8e51..5f0a45b356a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -156,9 +156,6 @@ int m33_image_handshake(ulong timeout_ms)
 	int ret;
 	ulong timeout_us = timeout_ms * 1000;
 
-	/* enable MU0_MUB clock before access the register of MU0_MUB */
-	pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
-
 	/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
 	setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
 
-- 
2.35.1

[PATCH V2 10/26] imx: imx8ulp: enable MU0_B clk by default

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Enable MU0_B clk by default. When M33 image is loaded by Jlink,
> the previous method not enable MU0_B clk and not able to communicate
> with M33, so let's enable it by default.
> And we not put it under kernel dts, because it conflicts with i.MX8QM
> suspend/resume logic which requires large change.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 11/26] misc: imx8ulp: Add OEM SRK Hash fuse support

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Since latest S400 firmware has supported to read OEM SRK Hash, add
it to the driver's table

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/imx8ulp/fuse.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c
index d1feb62ab59..01db470e8f1 100644
--- a/drivers/misc/imx8ulp/fuse.c
+++ b/drivers/misc/imx8ulp/fuse.c
@@ -61,6 +61,7 @@ struct s400_map_entry s400_api_mapping_table[] = {
 	{ 1, 8 },	/* LOCK */
 	{ 2, 8 },	/* ECID */
 	{ 7, 4, 0, 1 },	/* OTP_UNIQ_ID */
+	{ 15, 8 }, /* OEM SRK HASH */
 	{ 23, 1, 4, 2 }, /* OTFAD */
 };
 
-- 
2.35.1

[PATCH V2 11/26] misc: imx8ulp: Add OEM SRK Hash fuse support

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Since latest S400 firmware has supported to read OEM SRK Hash, add
> it to the driver's table
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 12/26] imx: imx8ulp: Change LPAV assignment for dual boot

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Assign the LPAV owner to RTD, and assign LPAV masters and peripherals
to APD. So except the masters and peripherals, other resources
(like DDR, cgc2, pcc5) in LPAV won't be reset during reboot and suspend.

No needs to initialize DDR again after reboot.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 5f0a45b356a..eb540e3881f 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -524,10 +524,10 @@ static int trdc_set_access(void)
 	return 0;
 }
 
-void lpav_configure(void)
+void lpav_configure(bool lpav_to_m33)
 {
-	/* LPAV to APD */
-	setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));
+	if (!lpav_to_m33)
+		setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); /* LPAV to APD */
 
 	/* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */
 	setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);
@@ -584,8 +584,9 @@ int arch_cpu_init(void)
 				release_rdc(RDC_TRDC);
 
 			trdc_set_access();
-
-			lpav_configure();
+			lpav_configure(false);
+		} else {
+			lpav_configure(true);
 		}
 
 		/* Release xrdc, then allow A35 to write SRAM2 */
-- 
2.35.1

[PATCH V2 12/26] imx: imx8ulp: Change LPAV assignment for dual boot

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Assign the LPAV owner to RTD, and assign LPAV masters and peripherals
> to APD. So except the masters and peripherals, other resources
> (like DDR, cgc2, pcc5) in LPAV won't be reset during reboot and suspend.
> No needs to initialize DDR again after reboot.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 13/26] imx: imx8ulp: Load the lposc fuse for dual boot

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Found the lposc fuse loading having impact to cpu idle in kernel.
Without the loading in dual boot mode, kernel will hang after idle
for a while.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/spl.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index e6949b5e431..9bc90816176 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -76,10 +76,8 @@ void spl_board_init(void)
 
 	/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
 
-	/* Load the lposc fuse for single boot to work around ROM issue,
-	 *  The fuse depends on S400 to read.
-	 */
-	if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
+	/* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */
+	if (is_soc_rev(CHIP_REV_1_0))
 		load_lposc_fuse();
 
 	upower_init();
-- 
2.35.1

[PATCH V2 13/26] imx: imx8ulp: Load the lposc fuse for dual boot

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Found the lposc fuse loading having impact to cpu idle in kernel.
> Without the loading in dual boot mode, kernel will hang after idle
> for a while.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 14/26] misc: S400_API: add ahab_release_caam

[Peng Fan (OSS)]

From: Clement Faure <clement.faure@nxp.com>

Add ahab_release_caam() function to the S400 API.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/s400_api.h |  2 ++
 drivers/misc/imx8ulp/s400_api.c              | 29 ++++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index c848f0dfb8f..b788661b098 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -19,6 +19,7 @@
 #define AHAB_READ_FUSE_REQ_CID	0x97
 #define AHAB_RELEASE_RDC_REQ_CID   0xC4
 #define AHAB_WRITE_FUSE_REQ_CID	0xD6
+#define AHAB_CAAM_RELEASE_CID 0xD7
 
 #define S400_MAX_MSG          8U
 
@@ -37,5 +38,6 @@ int ahab_verify_image(u32 img_id, u32 *response);
 int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
 int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
 int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
+int ahab_release_caam(u32 core_did, u32 *response);
 
 #endif
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index d76a95febe7..dd5f9f25da5 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -242,3 +242,32 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
 
 	return ret;
 }
+
+int ahab_release_caam(u32 core_did, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct imx8ulp_s400_msg);
+	struct imx8ulp_s400_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = AHAB_CAAM_RELEASE_CID;
+	msg.data[0] = core_did;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
-- 
2.35.1

[PATCH V2 14/26] misc: S400_API: add ahab_release_caam

[sbabic]

> From: Clement Faure <clement.faure@nxp.com>
> Add ahab_release_caam() function to the S400 API.
> Signed-off-by: Clement Faure <clement.faure@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 15/26] misc: S400_API: Update S400 API for buffer dump

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Add ahab_dump_buffer API to dump AHAB buffer for debug purpose

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/s400_api.h |  3 +-
 drivers/misc/imx8ulp/s400_api.c              | 34 ++++++++++++++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index b788661b098..1856659877e 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -21,7 +21,7 @@
 #define AHAB_WRITE_FUSE_REQ_CID	0xD6
 #define AHAB_CAAM_RELEASE_CID 0xD7
 
-#define S400_MAX_MSG          8U
+#define S400_MAX_MSG          255U
 
 struct imx8ulp_s400_msg {
 	u8 version;
@@ -39,5 +39,6 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
 int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
 int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
 int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
 
 #endif
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
index dd5f9f25da5..3ffdeb2ad2a 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/imx8ulp/s400_api.c
@@ -271,3 +271,37 @@ int ahab_release_caam(u32 core_did, u32 *response)
 
 	return ret;
 }
+
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct imx8ulp_s400_msg);
+	struct imx8ulp_s400_msg msg;
+	int ret, i = 0;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = AHAB_LOG_CID;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret) {
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+		return ret;
+	}
+
+	if (buffer) {
+		buffer[i++] = *(u32 *)&msg; /* Need dump the response header */
+		for (; i < buffer_length && i < msg.size; i++)
+			buffer[i] = msg.data[i - 1];
+	}
+
+	return i;
+}
-- 
2.35.1

[PATCH V2 15/26] misc: S400_API: Update S400 API for buffer dump

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Add ahab_dump_buffer API to dump AHAB buffer for debug purpose
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 16/26] imx: imx8ulp: release CAAM for the Cortex-A35

[Peng Fan (OSS)]

From: Clement Faure <clement.faure@nxp.com>

Release the CAAM for the A35 from the SPL.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/spl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 9bc90816176..66bfc2bd0ca 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -19,6 +19,7 @@
 #include <asm/arch/ddr.h>
 #include <asm/arch/rdc.h>
 #include <asm/arch/upower.h>
+#include <asm/arch/s400_api.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -60,6 +61,8 @@ int power_init_board(void)
 void spl_board_init(void)
 {
 	struct udevice *dev;
+	u32 res;
+	int ret;
 
 	uclass_find_first_device(UCLASS_MISC, &dev);
 
@@ -98,6 +101,11 @@ void spl_board_init(void)
 
 	/* Call it after PS16 power up */
 	set_lpav_qos();
+
+	/* Enable A35 access to the CAAM */
+	ret = ahab_release_caam(0x7, &res);
+	if (ret)
+		printf("ahab release caam failed %d, 0x%x\n", ret, res);
 }
 
 void board_init_f(ulong dummy)
-- 
2.35.1

[PATCH V2 16/26] imx: imx8ulp: release CAAM for the Cortex-A35

[sbabic]

> From: Clement Faure <clement.faure@nxp.com>
> Release the CAAM for the A35 from the SPL.
> Signed-off-by: Clement Faure <clement.faure@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 17/26] imx: imx8ulp_evk: Update LPDDR4 PHY settings

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Update DDR PHY settings to support LPDDR4 mode only by adjusting
DQ VREF ctrl, ODT and pads drive strength.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/lpddr4_timing.c | 32 ++++++++++-----------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 4546e92b01f..09240999cee 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -701,7 +701,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064154, 0x2000000 },	/* 85 */
 	{ 0x2e064158, 0x51515042 },	/* 86 */
 	{ 0x2e06415c, 0x31c06000 },	/* 87 */
-	{ 0x2e064160, 0x9bf000a },	/* 88 */
+	{ 0x2e064160, 0x6bf000a },	/* 88 */
 	{ 0x2e064164, 0xc0c000 },	/* 89 */
 	{ 0x2e064168, 0x1000000 },	/* 90 */
 	{ 0x2e06416c, 0x10001000 },	/* 91 */
@@ -777,7 +777,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064554, 0x2000000 },	/* 341 */
 	{ 0x2e064558, 0x51515042 },	/* 342 */
 	{ 0x2e06455c, 0x31c06000 },	/* 343 */
-	{ 0x2e064560, 0x9bf000a },	/* 344 */
+	{ 0x2e064560, 0x6bf000a },	/* 344 */
 	{ 0x2e064564, 0xc0c000 },	/* 345 */
 	{ 0x2e064568, 0x1000000 },	/* 346 */
 	{ 0x2e06456c, 0x10001000 },	/* 347 */
@@ -854,7 +854,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064954, 0x2000000 },	/* 597 */
 	{ 0x2e064958, 0x51515042 },	/* 598 */
 	{ 0x2e06495c, 0x31c06000 },	/* 599 */
-	{ 0x2e064960, 0x9bf000a },	/* 600 */
+	{ 0x2e064960, 0x6bf000a },	/* 600 */
 	{ 0x2e064964, 0xc0c000 },	/* 601 */
 	{ 0x2e064968, 0x1000000 },	/* 602 */
 	{ 0x2e06496c, 0x10001000 },	/* 603 */
@@ -930,7 +930,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064d54, 0x2000000 },	/* 853 */
 	{ 0x2e064d58, 0x51515042 },	/* 854 */
 	{ 0x2e064d5c, 0x31c06000 },	/* 855 */
-	{ 0x2e064d60, 0x9bf000a },	/* 856 */
+	{ 0x2e064d60, 0x6bf000a },	/* 856 */
 	{ 0x2e064d64, 0xc0c000 },	/* 857 */
 	{ 0x2e064d68, 0x1000000 },	/* 858 */
 	{ 0x2e064d6c, 0x10001000 },	/* 859 */
@@ -1032,7 +1032,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065860, 0x8040201 },	/* 1560 */
 	{ 0x2e065864, 0x2010201 },	/* 1561 */
 	{ 0x2e065868, 0xf0f0f },	/* 1562 */
-	{ 0x2e06586c, 0x241b42 },	/* 1563 */
+	{ 0x2e06586c, 0x241342 },	/* 1563 */
 	{ 0x2e065874, 0x1020000 },	/* 1565 */
 	{ 0x2e065878, 0x701 },	/* 1566 */
 	{ 0x2e06587c, 0x54 },	/* 1567 */
@@ -1047,7 +1047,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0658a0, 0x4410 },	/* 1576 */
 	{ 0x2e0658a4, 0x4410 },	/* 1577 */
 	{ 0x2e0658b0, 0x60000 },	/* 1580 */
-	{ 0x2e0658b8, 0x96 },	/* 1582 */
+	{ 0x2e0658b8, 0x66 },	/* 1582 */
 	{ 0x2e0658bc, 0x10000 },	/* 1583 */
 	{ 0x2e0658c0, 0x8 },	/* 1584 */
 	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
@@ -1074,20 +1074,20 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065980, 0x300 },	/* 1632 */
 	{ 0x2e065984, 0x300 },	/* 1633 */
 	{ 0x2e065988, 0x300 },	/* 1634 */
-	{ 0x2e06598c, 0x4bf77 },	/* 1635 */
-	{ 0x2e065990, 0x77 },	/* 1636 */
-	{ 0x2e065994, 0x27f },	/* 1637 */
-	{ 0x2e06599c, 0x27f },	/* 1639 */
-	{ 0x2e0659a4, 0x27f00 },	/* 1641 */
+	{ 0x2e06598c, 0x337cc },	/* 1635 */
+	{ 0x2e065990, 0x8 },	/* 1636 */
+	{ 0x2e065994, 0x1b7 },	/* 1637 */
+	{ 0x2e06599c, 0x1b7 },	/* 1639 */
+	{ 0x2e0659a4, 0x1b700 },	/* 1641 */
 	{ 0x2e0659a8, 0x1980000 },	/* 1642 */
-	{ 0x2e0659ac, 0x27fcc },	/* 1643 */
-	{ 0x2e0659b4, 0x27f00 },	/* 1645 */
+	{ 0x2e0659ac, 0x1b7cc },	/* 1643 */
+	{ 0x2e0659b4, 0x1b700 },	/* 1645 */
 	{ 0x2e0659b8, 0x1980000 },	/* 1646 */
-	{ 0x2e0659bc, 0x27f00 },	/* 1647 */
+	{ 0x2e0659bc, 0x1b700 },	/* 1647 */
 	{ 0x2e0659c0, 0x1980000 },	/* 1648 */
-	{ 0x2e0659c4, 0x27f00 },	/* 1649 */
+	{ 0x2e0659c4, 0x1b700 },	/* 1649 */
 	{ 0x2e0659c8, 0x1980000 },	/* 1650 */
-	{ 0x2e0659cc, 0x27f00 },	/* 1651 */
+	{ 0x2e0659cc, 0x1b700 },	/* 1651 */
 	{ 0x2e0659d0, 0x1980000 },	/* 1652 */
 	{ 0x2e0659d4, 0x20040003 },	/* 1653 */
 };
-- 
2.35.1

[PATCH V2 17/26] imx: imx8ulp_evk: Update LPDDR4 PHY settings

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Update DDR PHY settings to support LPDDR4 mode only by adjusting
> DQ VREF ctrl, ODT and pads drive strength.
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 18/26] imx: imx8ulp_evk: call the handshake with M33

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

If M33 handshake is successful, TPM and DSI panel MUX setting is
done by M33, no need to set them.
If handshake is failed or M33 is not booted, continue the TPM
and DSI panel MUX setting

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/imx8ulp_evk.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index 1502e4dbb66..b61a4cfbe8d 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -101,10 +101,18 @@ void mipi_dsi_panel_backlight(void)
 
 int board_init(void)
 {
+	int sync = -ENODEV;
+
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
 
-	if (IS_ENABLED(CONFIG_DM_VIDEO)) {
+	if (m33_image_booted()) {
+		sync = m33_image_handshake(1000);
+		printf("M33 Sync: %s\n", sync ? "Timeout" : "OK");
+	}
+
+	/* When sync with M33 is failed, use local driver to set for video */
+	if (sync != 0 && IS_ENABLED(CONFIG_DM_VIDEO)) {
 		mipi_dsi_mux_panel();
 		mipi_dsi_panel_backlight();
 	}
-- 
2.35.1

[PATCH V2 18/26] imx: imx8ulp_evk: call the handshake with M33

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> If M33 handshake is successful, TPM and DSI panel MUX setting is
> done by M33, no need to set them.
> If handshake is failed or M33 is not booted, continue the TPM
> and DSI panel MUX setting
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Biwen Li <biwen.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 19/26] imx: imx8ulp_evk: Power down the domains may used in u-boot

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Since ATF power domain will hold the enable counter for each power domain,
We need to power off them before entering kernel to avoid this
power domain can't be really powered off.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/imx8ulp_evk.c | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index b61a4cfbe8d..1bd308148f3 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -13,6 +13,8 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/gpio.h>
+#include <power-domain.h>
+#include <dt-bindings/power/imx8ulp-power.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -129,3 +131,31 @@ int board_late_init(void)
 {
 	return 0;
 }
+
+void board_quiesce_devices(void)
+{
+	/* Disable the power domains may used in u-boot before entering kernel */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	struct udevice *scmi_devpd;
+	int ret, i;
+	struct power_domain pd;
+	ulong ids[] = { IMX8ULP_PD_FLEXSPI2, IMX8ULP_PD_USB0, IMX8ULP_PD_USDHC0,
+			IMX8ULP_PD_USDHC1, IMX8ULP_PD_USDHC2_USB1, IMX8ULP_PD_DCNANO,
+			IMX8ULP_PD_MIPI_DSI };
+
+	ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &scmi_devpd);
+	if (ret) {
+		printf("Cannot get scmi devpd: err=%d\n", ret);
+		return;
+	}
+
+	pd.dev = scmi_devpd;
+
+	for (i = 0; i < ARRAY_SIZE(ids); i++) {
+		pd.id = ids[i];
+		ret = power_domain_off(&pd);
+		if (ret)
+			printf("power_domain_off %lu failed: err=%d\n", ids[i], ret);
+	}
+#endif
+}
-- 
2.35.1

Re: [PATCH V2 19/26] imx: imx8ulp_evk: Power down the domains may used in u-boot

[Stefano Babic]

Hi Peng,Ye,

On 06.04.22 08:30, Peng Fan (OSS) wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> Since ATF power domain will hold the enable counter for each power domain,
> We need to power off them before entering kernel to avoid this
> power domain can't be really powered off.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>   board/freescale/imx8ulp_evk/imx8ulp_evk.c | 30 +++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
> 
> diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
> index b61a4cfbe8d..1bd308148f3 100644
> --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
> +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
> @@ -13,6 +13,8 @@
>   #include <miiphy.h>
>   #include <netdev.h>
>   #include <asm/gpio.h>
> +#include <power-domain.h>
> +#include <dt-bindings/power/imx8ulp-power.h>

But which patch is adding the file above ? I cannot find it, it is not 
part of this series and of course build is broken without it.

Best regards,
Stefano

>   DECLARE_GLOBAL_DATA_PTR;
>   
> @@ -129,3 +131,31 @@ int board_late_init(void)
>   {
>   	return 0;
>   }
> +
> +void board_quiesce_devices(void)
> +{
> +	/* Disable the power domains may used in u-boot before entering kernel */
> +#if CONFIG_IS_ENABLED(POWER_DOMAIN)
> +	struct udevice *scmi_devpd;
> +	int ret, i;
> +	struct power_domain pd;
> +	ulong ids[] = { IMX8ULP_PD_FLEXSPI2, IMX8ULP_PD_USB0, IMX8ULP_PD_USDHC0,
> +			IMX8ULP_PD_USDHC1, IMX8ULP_PD_USDHC2_USB1, IMX8ULP_PD_DCNANO,
> +			IMX8ULP_PD_MIPI_DSI };
> +
> +	ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &scmi_devpd);
> +	if (ret) {
> +		printf("Cannot get scmi devpd: err=%d\n", ret);
> +		return;
> +	}
> +
> +	pd.dev = scmi_devpd;
> +
> +	for (i = 0; i < ARRAY_SIZE(ids); i++) {
> +		pd.id = ids[i];
> +		ret = power_domain_off(&pd);
> +		if (ret)
> +			printf("power_domain_off %lu failed: err=%d\n", ids[i], ret);
> +	}
> +#endif
> +}

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

Re: [PATCH V2 19/26] imx: imx8ulp_evk: Power down the domains may used in u-boot

[Peng Fan (OSS)]

Hi Stefano,

On 2022/4/13 1:10, Stefano Babic wrote:
> Hi Peng,Ye,
> 
> On 06.04.22 08:30, Peng Fan (OSS) wrote:
>> From: Ye Li <ye.li@nxp.com>
>>
>> Since ATF power domain will hold the enable counter for each power domain,
>> We need to power off them before entering kernel to avoid this
>> power domain can't be really powered off.
>>
>> Signed-off-by: Ye Li <ye.li@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>    board/freescale/imx8ulp_evk/imx8ulp_evk.c | 30 +++++++++++++++++++++++
>>    1 file changed, 30 insertions(+)
>>
>> diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
>> index b61a4cfbe8d..1bd308148f3 100644
>> --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
>> +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
>> @@ -13,6 +13,8 @@
>>    #include <miiphy.h>
>>    #include <netdev.h>
>>    #include <asm/gpio.h>
>> +#include <power-domain.h>
>> +#include <dt-bindings/power/imx8ulp-power.h>
> 
> But which patch is adding the file above ? I cannot find it, it is not
> part of this series and of course build is broken without it.

V5 patchset should not have such issue. I just see you already picked up 
V5 in your repo.

Thanks,
Peng.

> 
> Best regards,
> Stefano
> 
>>    DECLARE_GLOBAL_DATA_PTR;
>>    
>> @@ -129,3 +131,31 @@ int board_late_init(void)
>>    {
>>    	return 0;
>>    }
>> +
>> +void board_quiesce_devices(void)
>> +{
>> +	/* Disable the power domains may used in u-boot before entering kernel */
>> +#if CONFIG_IS_ENABLED(POWER_DOMAIN)
>> +	struct udevice *scmi_devpd;
>> +	int ret, i;
>> +	struct power_domain pd;
>> +	ulong ids[] = { IMX8ULP_PD_FLEXSPI2, IMX8ULP_PD_USB0, IMX8ULP_PD_USDHC0,
>> +			IMX8ULP_PD_USDHC1, IMX8ULP_PD_USDHC2_USB1, IMX8ULP_PD_DCNANO,
>> +			IMX8ULP_PD_MIPI_DSI };
>> +
>> +	ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &scmi_devpd);
>> +	if (ret) {
>> +		printf("Cannot get scmi devpd: err=%d\n", ret);
>> +		return;
>> +	}
>> +
>> +	pd.dev = scmi_devpd;
>> +
>> +	for (i = 0; i < ARRAY_SIZE(ids); i++) {
>> +		pd.id = ids[i];
>> +		ret = power_domain_off(&pd);
>> +		if (ret)
>> +			printf("power_domain_off %lu failed: err=%d\n", ids[i], ret);
>> +	}
>> +#endif
>> +}
> 

Re: [PATCH V2 19/26] imx: imx8ulp_evk: Power down the domains may used in u-boot

[Stefano Babic]

Hi Peng,

On 13.04.22 05:00, Peng Fan (OSS) wrote:
> Hi Stefano,
> 
> On 2022/4/13 1:10, Stefano Babic wrote:
>> Hi Peng,Ye,
>>
>> On 06.04.22 08:30, Peng Fan (OSS) wrote:
>>> From: Ye Li <ye.li@nxp.com>
>>>
>>> Since ATF power domain will hold the enable counter for each power 
>>> domain,
>>> We need to power off them before entering kernel to avoid this
>>> power domain can't be really powered off.
>>>
>>> Signed-off-by: Ye Li <ye.li@nxp.com>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>>    board/freescale/imx8ulp_evk/imx8ulp_evk.c | 30 
>>> +++++++++++++++++++++++
>>>    1 file changed, 30 insertions(+)
>>>
>>> diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c 
>>> b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
>>> index b61a4cfbe8d..1bd308148f3 100644
>>> --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
>>> +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
>>> @@ -13,6 +13,8 @@
>>>    #include <miiphy.h>
>>>    #include <netdev.h>
>>>    #include <asm/gpio.h>
>>> +#include <power-domain.h>
>>> +#include <dt-bindings/power/imx8ulp-power.h>
>>
>> But which patch is adding the file above ? I cannot find it, it is not
>> part of this series and of course build is broken without it.
> 
> V5 patchset should not have such issue. I just see you already picked up 
> V5 in your repo.
> 

Which series are you talking about ? This series is in V2, and yes, I 
merged the whole series with the exception of this patch, but none of 
the applied patches added imx8ulp-power.h.

Regards,
Stefano

> Thanks,
> Peng.
> 
>>
>> Best regards,
>> Stefano
>>
>>>    DECLARE_GLOBAL_DATA_PTR;
>>> @@ -129,3 +131,31 @@ int board_late_init(void)
>>>    {
>>>        return 0;
>>>    }
>>> +
>>> +void board_quiesce_devices(void)
>>> +{
>>> +    /* Disable the power domains may used in u-boot before entering 
>>> kernel */
>>> +#if CONFIG_IS_ENABLED(POWER_DOMAIN)
>>> +    struct udevice *scmi_devpd;
>>> +    int ret, i;
>>> +    struct power_domain pd;
>>> +    ulong ids[] = { IMX8ULP_PD_FLEXSPI2, IMX8ULP_PD_USB0, 
>>> IMX8ULP_PD_USDHC0,
>>> +            IMX8ULP_PD_USDHC1, IMX8ULP_PD_USDHC2_USB1, 
>>> IMX8ULP_PD_DCNANO,
>>> +            IMX8ULP_PD_MIPI_DSI };
>>> +
>>> +    ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &scmi_devpd);
>>> +    if (ret) {
>>> +        printf("Cannot get scmi devpd: err=%d\n", ret);
>>> +        return;
>>> +    }
>>> +
>>> +    pd.dev = scmi_devpd;
>>> +
>>> +    for (i = 0; i < ARRAY_SIZE(ids); i++) {
>>> +        pd.id = ids[i];
>>> +        ret = power_domain_off(&pd);
>>> +        if (ret)
>>> +            printf("power_domain_off %lu failed: err=%d\n", ids[i], 
>>> ret);
>>> +    }
>>> +#endif
>>> +}
>>


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 20/26] imx: dynamic setting mmcdev and mmcroot

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Dynamic setting mmcdev and mmcroot.
Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/mach-imx/sys_proto.h |  2 +
 board/freescale/common/Makefile           |  3 ++
 board/freescale/common/mmc.c              | 49 +++++++++++++++++++++++
 3 files changed, 54 insertions(+)
 create mode 100644 board/freescale/common/mmc.c

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 0c0c7814fb2..37fd427cc00 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -228,6 +228,8 @@ int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 
+void board_late_mmc_env_init(void);
+
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 			   unsigned long reg1, unsigned long reg2,
 			   unsigned long reg3);
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index f13965daf2e..4df484935f4 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -63,6 +63,9 @@ obj-$(CONFIG_ZM7300)		+= zm7300.o
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_DM_PMIC_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_POWER_MC34VR500)	+= mc34vr500.o
+ifneq (,$(filter $(SOC), imx8ulp))
+obj-y				+= mmc.o
+endif
 
 obj-$(CONFIG_LS102XA_STREAM_ID)	+= ls102xa_stream_id.o
 
diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c
new file mode 100644
index 00000000000..8cd5079f962
--- /dev/null
+++ b/board/freescale/common/mmc.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018-2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+#include <mmc.h>
+#include <env.h>
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if (autodetect_str && !strcmp(autodetect_str, "yes"))
+		return 1;
+
+	return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+	return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", mmc_map_to_kernel_blk(dev_no));
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
-- 
2.35.1

[PATCH V2 20/26] imx: dynamic setting mmcdev and mmcroot

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Dynamic setting mmcdev and mmcroot.
> Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

Re: [PATCH V2 20/26] imx: dynamic setting mmcdev and mmcroot

[Tim Harvey]

On Tue, Apr 5, 2022 at 10:56 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> Dynamic setting mmcdev and mmcroot.
> Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm/include/asm/mach-imx/sys_proto.h |  2 +
>  board/freescale/common/Makefile           |  3 ++
>  board/freescale/common/mmc.c              | 49 +++++++++++++++++++++++
>  3 files changed, 54 insertions(+)
>  create mode 100644 board/freescale/common/mmc.c
>
> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
> index 0c0c7814fb2..37fd427cc00 100644
> --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> @@ -228,6 +228,8 @@ int mxs_reset_block(struct mxs_register_32 *reg);
>  int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
>  int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
>
> +void board_late_mmc_env_init(void);
> +
>  unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
>                            unsigned long reg1, unsigned long reg2,
>                            unsigned long reg3);
> diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
> index f13965daf2e..4df484935f4 100644
> --- a/board/freescale/common/Makefile
> +++ b/board/freescale/common/Makefile
> @@ -63,6 +63,9 @@ obj-$(CONFIG_ZM7300)          += zm7300.o
>  obj-$(CONFIG_POWER_PFUZE100)   += pfuze.o
>  obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
>  obj-$(CONFIG_POWER_MC34VR500)  += mc34vr500.o
> +ifneq (,$(filter $(SOC), imx8ulp))
> +obj-y                          += mmc.o
> +endif
>
>  obj-$(CONFIG_LS102XA_STREAM_ID)        += ls102xa_stream_id.o
>
> diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c
> new file mode 100644
> index 00000000000..8cd5079f962
> --- /dev/null
> +++ b/board/freescale/common/mmc.c
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + * Copyright 2018-2022 NXP
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +#include <linux/errno.h>
> +#include <asm/io.h>
> +#include <stdbool.h>
> +#include <mmc.h>
> +#include <env.h>
> +
> +static int check_mmc_autodetect(void)
> +{
> +       char *autodetect_str = env_get("mmcautodetect");
> +
> +       if (autodetect_str && !strcmp(autodetect_str, "yes"))
> +               return 1;
> +
> +       return 0;
> +}
> +
> +/* This should be defined for each board */
> +__weak int mmc_map_to_kernel_blk(int dev_no)
> +{
> +       return dev_no;
> +}
> +
> +void board_late_mmc_env_init(void)
> +{
> +       char cmd[32];
> +       char mmcblk[32];
> +       u32 dev_no = mmc_get_env_dev();
> +
> +       if (!check_mmc_autodetect())
> +               return;
> +
> +       env_set_ulong("mmcdev", dev_no);
> +
> +       /* Set mmcblk env */
> +       sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", mmc_map_to_kernel_blk(dev_no));
> +       env_set("mmcroot", mmcblk);
> +
> +       sprintf(cmd, "mmc dev %d", dev_no);
> +       run_command(cmd, 0);
> +}
> --
> 2.35.1
>

Peng,

I see Stefano already applied this but I'm not sure I agree with it.
Why should you assume that U-Boot and Linux have the same device
mapping? The kernel device mapping is not guaranteed to be consistent.
Every time I have asked about this I've been told the standard was to
use a boot script that used 'part' to determine the UUID of the boot
device from U-Boot's perspective then use root=PARTUUID= to match that
from the kernel's perspective.

For example if using CONFIG_DISTRO_DEFAULTS=y (which I think everyone
should be using) your bootscript would look like this:
part uuid ${devtype} ${devnum}:${distro_bootpart} uuid
setenv bootargs "root=PARTUUID=${uuid} rootwait $bootargs"

Best Regards,

Tim

RE: [PATCH V2 20/26] imx: dynamic setting mmcdev and mmcroot

[Peng Fan (OSS)]

> Subject: Re: [PATCH V2 20/26] imx: dynamic setting mmcdev and mmcroot
> 
> On Tue, Apr 5, 2022 at 10:56 PM Peng Fan (OSS) <peng.fan@oss.nxp.com>
> wrote:
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Dynamic setting mmcdev and mmcroot.
> > Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm/include/asm/mach-imx/sys_proto.h |  2 +
> >  board/freescale/common/Makefile           |  3 ++
> >  board/freescale/common/mmc.c              | 49 +++++++++++++++++++++++
> >  3 files changed, 54 insertions(+)
> >  create mode 100644 board/freescale/common/mmc.c
> >
> > diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
> > b/arch/arm/include/asm/mach-imx/sys_proto.h
> > index 0c0c7814fb2..37fd427cc00 100644
> > --- a/arch/arm/include/asm/mach-imx/sys_proto.h
> > +++ b/arch/arm/include/asm/mach-imx/sys_proto.h
> > @@ -228,6 +228,8 @@ int mxs_reset_block(struct mxs_register_32 *reg);
> > int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32
> > timeout);  int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32
> > mask, u32 timeout);
> >
> > +void board_late_mmc_env_init(void);
> > +
> >  unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
> >                            unsigned long reg1, unsigned long reg2,
> >                            unsigned long reg3); diff --git
> > a/board/freescale/common/Makefile b/board/freescale/common/Makefile
> > index f13965daf2e..4df484935f4 100644
> > --- a/board/freescale/common/Makefile
> > +++ b/board/freescale/common/Makefile
> > @@ -63,6 +63,9 @@ obj-$(CONFIG_ZM7300)          += zm7300.o
> >  obj-$(CONFIG_POWER_PFUZE100)   += pfuze.o
> >  obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
> >  obj-$(CONFIG_POWER_MC34VR500)  += mc34vr500.o
> > +ifneq (,$(filter $(SOC), imx8ulp))
> > +obj-y                          += mmc.o
> > +endif
> >
> >  obj-$(CONFIG_LS102XA_STREAM_ID)        += ls102xa_stream_id.o
> >
> > diff --git a/board/freescale/common/mmc.c
> > b/board/freescale/common/mmc.c new file mode 100644 index
> > 00000000000..8cd5079f962
> > --- /dev/null
> > +++ b/board/freescale/common/mmc.c
> > @@ -0,0 +1,49 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2016 Freescale Semiconductor, Inc.
> > + * Copyright 2018-2022 NXP
> > + */
> > +
> > +#include <common.h>
> > +#include <command.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <linux/errno.h>
> > +#include <asm/io.h>
> > +#include <stdbool.h>
> > +#include <mmc.h>
> > +#include <env.h>
> > +
> > +static int check_mmc_autodetect(void) {
> > +       char *autodetect_str = env_get("mmcautodetect");
> > +
> > +       if (autodetect_str && !strcmp(autodetect_str, "yes"))
> > +               return 1;
> > +
> > +       return 0;
> > +}
> > +
> > +/* This should be defined for each board */ __weak int
> > +mmc_map_to_kernel_blk(int dev_no) {
> > +       return dev_no;
> > +}
> > +
> > +void board_late_mmc_env_init(void)
> > +{
> > +       char cmd[32];
> > +       char mmcblk[32];
> > +       u32 dev_no = mmc_get_env_dev();
> > +
> > +       if (!check_mmc_autodetect())
> > +               return;
> > +
> > +       env_set_ulong("mmcdev", dev_no);
> > +
> > +       /* Set mmcblk env */
> > +       sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
> mmc_map_to_kernel_blk(dev_no));
> > +       env_set("mmcroot", mmcblk);
> > +
> > +       sprintf(cmd, "mmc dev %d", dev_no);
> > +       run_command(cmd, 0);
> > +}
> > --
> > 2.35.1
> >
> 
> Peng,
> 
> I see Stefano already applied this but I'm not sure I agree with it.
> Why should you assume that U-Boot and Linux have the same device mapping?
> The kernel device mapping is not guaranteed to be consistent.
> Every time I have asked about this I've been told the standard was to use a boot
> script that used 'part' to determine the UUID of the boot device from U-Boot's
> perspective then use root=PARTUUID= to match that from the kernel's
> perspective.
> 
> For example if using CONFIG_DISTRO_DEFAULTS=y (which I think everyone
> should be using) your bootscript would look like this:
> part uuid ${devtype} ${devnum}:${distro_bootpart} uuid setenv bootargs
> "root=PARTUUID=${uuid} rootwait $bootargs"

For NXP internal release, we still use legacy way, with cmd in config header file,
let me check and update to fix this. Thanks for pointing out.

Thanks,
Peng.

> 
> Best Regards,
> 
> Tim

[PATCH V2 21/26] imx: imx8ulp_evk: Enable SD/MMC port auto detect

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Enable the SD/MMC port auto detect.
The mmc relevant env can be reset when auto detect is enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/imx8ulp_evk.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index 1bd308148f3..5ca72e171ce 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -129,6 +129,9 @@ int board_early_init_f(void)
 
 int board_late_init(void)
 {
+#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
+	board_late_mmc_env_init();
+#endif
 	return 0;
 }
 
-- 
2.35.1

[PATCH V2 21/26] imx: imx8ulp_evk: Enable SD/MMC port auto detect

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Enable the SD/MMC port auto detect.
> The mmc relevant env can be reset when auto detect is enabled.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 22/26] imx: imx8ulp: enable wdog_ad interrupt in CMC1

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

Enable wdog_ad interrupt being triggered by CMC1 to CM33 to let CM33
know A35 reset and reinitialize rpmsg.
Clear wdog_ad and AD_PERIPH reset interrupt after A35 up, otherwise
M33 will always receive interrupt.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index eb540e3881f..569558c7d83 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -571,6 +571,19 @@ int arch_cpu_init(void)
 		int ret;
 		bool rdc_en = true; /* Default assume DBD_EN is set */
 
+		/* Enable System Reset Interrupt using WDOG_AD */
+		setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
+		/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
+		setbits_le32(CMC1_BASE_ADDR + 0x70, BIT(4));
+
+		if (readl(CMC1_BASE_ADDR + 0x90) & BIT(13)) {
+			/* Clear System Reset Interrupt Flag Register of WDOG_AD */
+			setbits_le32(CMC1_BASE_ADDR + 0x90, BIT(13));
+			/* Reset WDOG to clear reset request */
+			pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, true);
+			pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, false);
+		}
+
 		/* Disable wdog */
 		init_wdog();
 
-- 
2.35.1

[PATCH V2 22/26] imx: imx8ulp: enable wdog_ad interrupt in CMC1

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Enable wdog_ad interrupt being triggered by CMC1 to CM33 to let CM33
> know A35 reset and reinitialize rpmsg.
> Clear wdog_ad and AD_PERIPH reset interrupt after A35 up, otherwise
> M33 will always receive interrupt.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 23/26] imx: imx8ulp: reserve tee memory

[Peng Fan (OSS)]

From: Ji Luo <ji.luo@nxp.com>

The TEE memory should be reserved when TEE is present, so need
to runtime update dram bank and memory information according to
tee present or not.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 102 +++++++++++++++++++++++++++++++-
 1 file changed, 100 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 569558c7d83..25b4fbd294e 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -413,6 +413,17 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
 
 struct mm_region *mem_map = imx8ulp_arm64_mem_map;
 
+static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
+		if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+			return i;
+
+	hang();	/* Entry not found, this must never happen. */
+}
+
 /* simplify the page table size to enhance boot speed */
 #define MAX_PTE_ENTRIES		512
 #define MAX_MEM_MAP_REGIONS	16
@@ -444,19 +455,106 @@ u64 get_page_table_size(void)
 
 void enable_caches(void)
 {
-	/* TODO: add TEE memmap region */
+	/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
+	if (rom_pointer[1]) {
+		/*
+		 * TEE are loaded, So the ddr bank structures
+		 * have been modified update mmu table accordingly
+		 */
+		int i = 0;
+		int entry = imx8ulp_find_dram_entry_in_mem_map();
+		u64 attrs = imx8ulp_arm64_mem_map[entry].attrs;
+
+		while (i < CONFIG_NR_DRAM_BANKS &&
+		       entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
+			if (gd->bd->bi_dram[i].start == 0)
+				break;
+			imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+			imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+			imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
+			imx8ulp_arm64_mem_map[entry].attrs = attrs;
+			debug("Added memory mapping (%d): %llx %llx\n", entry,
+			      imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
+			i++; entry++;
+		}
+	}
 
 	icache_enable();
 	dcache_enable();
 }
 
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
 int dram_init(void)
 {
-	gd->ram_size = PHYS_SDRAM_SIZE;
+	unsigned int entry = imx8ulp_find_dram_entry_in_mem_map();
+	phys_size_t sdram_size;
+	int ret;
+
+	ret = board_phys_sdram_size(&sdram_size);
+	if (ret)
+		return ret;
+
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = sdram_size - rom_pointer[1];
+	else
+		gd->ram_size = sdram_size;
+
+	/* also update the SDRAM size in the mem_map used externally */
+	imx8ulp_arm64_mem_map[entry].size = sdram_size;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	int bank = 0;
+	int ret;
+	phys_size_t sdram_size;
+
+	ret = board_phys_sdram_size(&sdram_size);
+	if (ret)
+		return ret;
+
+	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	if (rom_pointer[1]) {
+		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+		phys_size_t optee_size = (size_t)rom_pointer[1];
+
+		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+			if (++bank >= CONFIG_NR_DRAM_BANKS) {
+				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+				return -1;
+			}
+
+			gd->bd->bi_dram[bank].start = optee_start + optee_size;
+			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+				sdram_size - gd->bd->bi_dram[bank].start;
+		}
+	} else {
+		gd->bd->bi_dram[bank].size = sdram_size;
+	}
 
 	return 0;
 }
 
+phys_size_t get_effective_memsize(void)
+{
+	/* return the first bank as effective memory */
+	if (rom_pointer[1])
+		return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+
+	return gd->ram_size;
+}
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 void get_board_serial(struct tag_serialnr *serialnr)
 {
-- 
2.35.1

[PATCH V2 23/26] imx: imx8ulp: reserve tee memory

[sbabic]

> From: Ji Luo <ji.luo@nxp.com>
> The TEE memory should be reserved when TEE is present, so need
> to runtime update dram bank and memory information according to
> tee present or not.
> Signed-off-by: Ji Luo <ji.luo@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 24/26] imx: imx8ulp_evk: enlarge CONFIG_NR_DRAM_BANKS

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

When TEE is present, the DRAM maybe split to two parts,
so enlarge CONFIG_NR_DRAM_BANKS

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 configs/imx8ulp_evk_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index dafb817f9f3..a8cdb501601 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x1002000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_IMX_CONFIG=""
-- 
2.35.1

[PATCH V2 24/26] imx: imx8ulp_evk: enlarge CONFIG_NR_DRAM_BANKS

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> When TEE is present, the DRAM maybe split to two parts,
> so enlarge CONFIG_NR_DRAM_BANKS
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 25/26] imx: imx8ulp_evk: Enable multiple env storage devices

[Peng Fan (OSS)]

From: Ye Li <ye.li@nxp.com>

Enable multiple storages for u-boot env:
MMC or SPI flash or NOWHERE for usb
so u-boot can runtime select the storage flash according to boot device.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 36 +++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 25b4fbd294e..35020c9714d 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -27,6 +27,8 @@
 #include <fuse.h>
 #include <thermal.h>
 #include <linux/iopoll.h>
+#include <env.h>
+#include <env_internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -787,3 +789,37 @@ u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
 
 	return image_offset;
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	enum boot_device dev = get_boot_device();
+	enum env_location env_loc = ENVL_UNKNOWN;
+
+	if (prio)
+		return env_loc;
+
+	switch (dev) {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+	case QSPI_BOOT:
+		env_loc = ENVL_SPI_FLASH;
+		break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case SD3_BOOT:
+	case MMC1_BOOT:
+	case MMC2_BOOT:
+	case MMC3_BOOT:
+		env_loc =  ENVL_MMC;
+		break;
+#endif
+	default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+		env_loc = ENVL_NOWHERE;
+#endif
+		break;
+	}
+
+	return env_loc;
+}
-- 
2.35.1

[PATCH V2 25/26] imx: imx8ulp_evk: Enable multiple env storage devices

[sbabic]

> From: Ye Li <ye.li@nxp.com>
> Enable multiple storages for u-boot env:
> MMC or SPI flash or NOWHERE for usb
> so u-boot can runtime select the storage flash according to boot device.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH V2 26/26] misc: imx8ulp: Update fuse driver

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

- According to S400 API, the fuse bank 25 (Testconfig2) is able to
access. Add it into driver's mapping table.
- According to FSB words list, the reserved 48 words are ahead of
the bank 5 and bank 6. Fix the wrong position.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/imx8ulp/fuse.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c
index 01db470e8f1..090e702d9f7 100644
--- a/drivers/misc/imx8ulp/fuse.c
+++ b/drivers/misc/imx8ulp/fuse.c
@@ -34,9 +34,9 @@ struct s400_map_entry {
 struct fsb_map_entry fsb_mapping_table[] = {
 	{ 3, 8 },
 	{ 4, 8 },
+	{ -1, 48 }, /* Reserve 48 words */
 	{ 5, 8 },
 	{ 6, 8 },
-	{ -1, 48 }, /* Reserve 48 words */
 	{ 8,  4, true },
 	{ 24, 4, true },
 	{ 26, 4, true },
@@ -63,6 +63,7 @@ struct s400_map_entry s400_api_mapping_table[] = {
 	{ 7, 4, 0, 1 },	/* OTP_UNIQ_ID */
 	{ 15, 8 }, /* OEM SRK HASH */
 	{ 23, 1, 4, 2 }, /* OTFAD */
+	{ 25, 8 }, /* Test config2 */
 };
 
 static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
-- 
2.35.1

[PATCH V2 26/26] misc: imx8ulp: Update fuse driver

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> - According to S400 API, the fuse bank 25 (Testconfig2) is able to
> access. Add it into driver's mapping table.
> - According to FSB words list, the reserved 48 words are ahead of
> the bank 5 and bank 6. Fix the wrong position.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================