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From: Niklas Cassel <niklas.cassel@wdc.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Niklas Cassel <niklas.cassel@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
Date: Thu, 14 Apr 2022 17:16:38 +0200	[thread overview]
Message-ID: <20220414151639.1359969-1-niklas.cassel@wdc.com> (raw)

sv57 is defined in the RISC-V Privileged Specification document.

Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
changed the default MMU mode to sv57, if supported by current hardware.

Add riscv,sv57 to the list of valid mmu-type values.

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..3100fa233ca4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
       - riscv,sv32
       - riscv,sv39
       - riscv,sv48
+      - riscv,sv57
       - riscv,none
 
   riscv,isa:
-- 
2.35.1


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WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <niklas.cassel@wdc.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Niklas Cassel <niklas.cassel@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
Date: Thu, 14 Apr 2022 17:16:38 +0200	[thread overview]
Message-ID: <20220414151639.1359969-1-niklas.cassel@wdc.com> (raw)

sv57 is defined in the RISC-V Privileged Specification document.

Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
changed the default MMU mode to sv57, if supported by current hardware.

Add riscv,sv57 to the list of valid mmu-type values.

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..3100fa233ca4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
       - riscv,sv32
       - riscv,sv39
       - riscv,sv48
+      - riscv,sv57
       - riscv,none
 
   riscv,isa:
-- 
2.35.1


             reply	other threads:[~2022-04-14 15:17 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-14 15:16 Niklas Cassel [this message]
2022-04-14 15:16 ` [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57 Niklas Cassel
2022-04-14 15:39 ` Niklas Cassel
2022-04-14 15:39   ` Niklas Cassel
2022-04-19 18:15 ` Rob Herring
2022-04-19 18:15   ` Rob Herring

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