* [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
@ 2022-04-14 15:16 ` Niklas Cassel
0 siblings, 0 replies; 6+ messages in thread
From: Niklas Cassel @ 2022-04-14 15:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: Niklas Cassel, Palmer Dabbelt, devicetree, linux-riscv
sv57 is defined in the RISC-V Privileged Specification document.
Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
changed the default MMU mode to sv57, if supported by current hardware.
Add riscv,sv57 to the list of valid mmu-type values.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..3100fa233ca4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
- riscv,sv32
- riscv,sv39
- riscv,sv48
+ - riscv,sv57
- riscv,none
riscv,isa:
--
2.35.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
@ 2022-04-14 15:16 ` Niklas Cassel
0 siblings, 0 replies; 6+ messages in thread
From: Niklas Cassel @ 2022-04-14 15:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: Niklas Cassel, Palmer Dabbelt, devicetree, linux-riscv
sv57 is defined in the RISC-V Privileged Specification document.
Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
changed the default MMU mode to sv57, if supported by current hardware.
Add riscv,sv57 to the list of valid mmu-type values.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..3100fa233ca4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
- riscv,sv32
- riscv,sv39
- riscv,sv48
+ - riscv,sv57
- riscv,none
riscv,isa:
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
2022-04-14 15:16 ` Niklas Cassel
@ 2022-04-14 15:39 ` Niklas Cassel
-1 siblings, 0 replies; 6+ messages in thread
From: Niklas Cassel @ 2022-04-14 15:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: devicetree, linux-riscv
On Thu, Apr 14, 2022 at 05:16:38PM +0200, Niklas Cassel wrote:
> sv57 is defined in the RISC-V Privileged Specification document.
>
> Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
> changed the default MMU mode to sv57, if supported by current hardware.
>
> Add riscv,sv57 to the list of valid mmu-type values.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d632ac76532e..3100fa233ca4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -61,6 +61,7 @@ properties:
> - riscv,sv32
> - riscv,sv39
> - riscv,sv48
> + - riscv,sv57
> - riscv,none
>
> riscv,isa:
> --
> 2.35.1
>
Hello Palmer,
I got a bounce on your old email address.
My git-send-email scripts, for getting the list of CC, uses:
./scripts/get_maintainer.pl --nom --norolestats --nogit --nogit-fallback <patch>
You might want to either:
a) Update your email in the DT bindings:
$ git grep palmer@sifive
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml: - Palmer Debbelt <palmer@sifive.com>
Documentation/devicetree/bindings/riscv/cpus.yaml: - Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/riscv/sifive.yaml: - Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/serial/sifive-serial.yaml: - Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/spi/spi-sifive.yaml: - Palmer Dabbelt <palmer@sifive.com>
or
b) Tell get_maintainer.pl to redirect your old address to your new address
by adding an entry in the .mailmap file:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/.mailmap
Kind regards,
Niklas
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
@ 2022-04-14 15:39 ` Niklas Cassel
0 siblings, 0 replies; 6+ messages in thread
From: Niklas Cassel @ 2022-04-14 15:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: devicetree, linux-riscv
On Thu, Apr 14, 2022 at 05:16:38PM +0200, Niklas Cassel wrote:
> sv57 is defined in the RISC-V Privileged Specification document.
>
> Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
> changed the default MMU mode to sv57, if supported by current hardware.
>
> Add riscv,sv57 to the list of valid mmu-type values.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d632ac76532e..3100fa233ca4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -61,6 +61,7 @@ properties:
> - riscv,sv32
> - riscv,sv39
> - riscv,sv48
> + - riscv,sv57
> - riscv,none
>
> riscv,isa:
> --
> 2.35.1
>
Hello Palmer,
I got a bounce on your old email address.
My git-send-email scripts, for getting the list of CC, uses:
./scripts/get_maintainer.pl --nom --norolestats --nogit --nogit-fallback <patch>
You might want to either:
a) Update your email in the DT bindings:
$ git grep palmer@sifive
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml: - Palmer Debbelt <palmer@sifive.com>
Documentation/devicetree/bindings/riscv/cpus.yaml: - Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/riscv/sifive.yaml: - Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/serial/sifive-serial.yaml: - Palmer Dabbelt <palmer@sifive.com>
Documentation/devicetree/bindings/spi/spi-sifive.yaml: - Palmer Dabbelt <palmer@sifive.com>
or
b) Tell get_maintainer.pl to redirect your old address to your new address
by adding an entry in the .mailmap file:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/.mailmap
Kind regards,
Niklas
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
2022-04-14 15:16 ` Niklas Cassel
@ 2022-04-19 18:15 ` Rob Herring
-1 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2022-04-19 18:15 UTC (permalink / raw)
To: Niklas Cassel
Cc: Albert Ou, Palmer Dabbelt, devicetree, Paul Walmsley,
linux-riscv, Krzysztof Kozlowski
On Thu, 14 Apr 2022 17:16:38 +0200, Niklas Cassel wrote:
> sv57 is defined in the RISC-V Privileged Specification document.
>
> Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
> changed the default MMU mode to sv57, if supported by current hardware.
>
> Add riscv,sv57 to the list of valid mmu-type values.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57
@ 2022-04-19 18:15 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2022-04-19 18:15 UTC (permalink / raw)
To: Niklas Cassel
Cc: Albert Ou, Palmer Dabbelt, devicetree, Paul Walmsley,
linux-riscv, Krzysztof Kozlowski
On Thu, 14 Apr 2022 17:16:38 +0200, Niklas Cassel wrote:
> sv57 is defined in the RISC-V Privileged Specification document.
>
> Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly")
> changed the default MMU mode to sv57, if supported by current hardware.
>
> Add riscv,sv57 to the list of valid mmu-type values.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-19 18:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-14 15:16 [PATCH] dt-bindings: riscv: Add mmu-type riscv,sv57 Niklas Cassel
2022-04-14 15:16 ` Niklas Cassel
2022-04-14 15:39 ` Niklas Cassel
2022-04-14 15:39 ` Niklas Cassel
2022-04-19 18:15 ` Rob Herring
2022-04-19 18:15 ` Rob Herring
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.