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From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
	Anup Patel <anup.patel@wdc.com>, Jim Shu <jim.shu@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v4 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
Date: Wed, 20 Apr 2022 16:08:57 +0800	[thread overview]
Message-ID: <20220420080901.14655-2-frank.chang@sifive.com> (raw)
In-Reply-To: <20220420080901.14655-1-frank.chang@sifive.com>

From: Frank Chang <frank.chang@sifive.com>

If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesses.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
 hw/intc/riscv_aclint.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index e43b050e92..37e9ace801 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = {
     .valid = {
         .min_access_size = 4,
         .max_access_size = 8
+    },
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 8,
     }
 };
 
-- 
2.35.1



WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Jim Shu <jim.shu@sifive.com>, Bin Meng <bmeng.cn@gmail.com>,
	Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v4 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
Date: Wed, 20 Apr 2022 16:08:57 +0800	[thread overview]
Message-ID: <20220420080901.14655-2-frank.chang@sifive.com> (raw)
In-Reply-To: <20220420080901.14655-1-frank.chang@sifive.com>

From: Frank Chang <frank.chang@sifive.com>

If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesses.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
 hw/intc/riscv_aclint.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index e43b050e92..37e9ace801 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = {
     .valid = {
         .min_access_size = 4,
         .max_access_size = 8
+    },
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 8,
     }
 };
 
-- 
2.35.1



  reply	other threads:[~2022-04-20  8:15 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-20  8:08 [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses frank.chang
2022-04-20  8:08 ` frank.chang
2022-04-20  8:08 ` frank.chang [this message]
2022-04-20  8:08   ` [PATCH v4 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT frank.chang
2022-04-20  8:08 ` [PATCH v4 2/4] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " frank.chang
2022-04-20  8:08   ` frank.chang
2022-04-20  8:08 ` [PATCH v4 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable frank.chang
2022-04-20  8:08   ` frank.chang
2022-04-20  8:09 ` [PATCH v4 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices frank.chang
2022-04-20  8:09   ` frank.chang
2022-04-20 22:40 ` [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses Alistair Francis
2022-04-20 22:40   ` Alistair Francis

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