From: Alistair Francis <alistair23@gmail.com> To: Frank Chang <frank.chang@sifive.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses Date: Thu, 21 Apr 2022 08:40:30 +1000 [thread overview] Message-ID: <CAKmqyKMFWO+aJdAyKviysp7AzhAHnRw2KnqK=7UY6ZvrxZNtBg@mail.gmail.com> (raw) In-Reply-To: <20220420080901.14655-1-frank.chang@sifive.com> On Wed, Apr 20, 2022 at 6:09 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > This patchset makes ACLINT mtime to be writable as RISC-V privilege > spec defines that mtime is exposed as a memory-mapped machine-mode > read-write register. Also, mtimecmp and mtime should be 32/64-bit memory > accessible registers. ACLINT reset function is also added, which requires > mtime to be resetable if we need to support core power-gating feature in > the future. > > This patchset is the updated verion of: > https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/ Thanks! Applied to riscv-to-apply.next Alistair > > Changelog: > > v4: > * Replace the error log mask for invalid 8-byte timecmp_hi and time_hi > writes from LOG_UNIMP to LOG_GUEST_ERROR. > > v3: > * Forbid 8-byte write access to timecmp_hi and time_hi. > * Add ACLINT reset function. > > v2: > * Support 32/64-bit mtimecmp/mtime memory accesses. > * Add .impl.[min|max]_access_size declaration. > > Frank Chang (3): > hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT > hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V > ACLINT > hw/intc: Make RISC-V ACLINT mtime MMIO register writable > > Jim Shu (1): > hw/intc: riscv_aclint: Add reset function of ACLINT devices > > hw/intc/riscv_aclint.c | 144 ++++++++++++++++++++++++++------- > include/hw/intc/riscv_aclint.h | 1 + > target/riscv/cpu.h | 8 +- > target/riscv/cpu_helper.c | 4 +- > 4 files changed, 121 insertions(+), 36 deletions(-) > > -- > 2.35.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Frank Chang <frank.chang@sifive.com> Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org> Subject: Re: [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses Date: Thu, 21 Apr 2022 08:40:30 +1000 [thread overview] Message-ID: <CAKmqyKMFWO+aJdAyKviysp7AzhAHnRw2KnqK=7UY6ZvrxZNtBg@mail.gmail.com> (raw) In-Reply-To: <20220420080901.14655-1-frank.chang@sifive.com> On Wed, Apr 20, 2022 at 6:09 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > This patchset makes ACLINT mtime to be writable as RISC-V privilege > spec defines that mtime is exposed as a memory-mapped machine-mode > read-write register. Also, mtimecmp and mtime should be 32/64-bit memory > accessible registers. ACLINT reset function is also added, which requires > mtime to be resetable if we need to support core power-gating feature in > the future. > > This patchset is the updated verion of: > https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/ Thanks! Applied to riscv-to-apply.next Alistair > > Changelog: > > v4: > * Replace the error log mask for invalid 8-byte timecmp_hi and time_hi > writes from LOG_UNIMP to LOG_GUEST_ERROR. > > v3: > * Forbid 8-byte write access to timecmp_hi and time_hi. > * Add ACLINT reset function. > > v2: > * Support 32/64-bit mtimecmp/mtime memory accesses. > * Add .impl.[min|max]_access_size declaration. > > Frank Chang (3): > hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT > hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V > ACLINT > hw/intc: Make RISC-V ACLINT mtime MMIO register writable > > Jim Shu (1): > hw/intc: riscv_aclint: Add reset function of ACLINT devices > > hw/intc/riscv_aclint.c | 144 ++++++++++++++++++++++++++------- > include/hw/intc/riscv_aclint.h | 1 + > target/riscv/cpu.h | 8 +- > target/riscv/cpu_helper.c | 4 +- > 4 files changed, 121 insertions(+), 36 deletions(-) > > -- > 2.35.1 > >
next prev parent reply other threads:[~2022-04-20 22:44 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-20 8:08 [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses frank.chang 2022-04-20 8:08 ` frank.chang 2022-04-20 8:08 ` [PATCH v4 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT frank.chang 2022-04-20 8:08 ` frank.chang 2022-04-20 8:08 ` [PATCH v4 2/4] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " frank.chang 2022-04-20 8:08 ` frank.chang 2022-04-20 8:08 ` [PATCH v4 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable frank.chang 2022-04-20 8:08 ` frank.chang 2022-04-20 8:09 ` [PATCH v4 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices frank.chang 2022-04-20 8:09 ` frank.chang 2022-04-20 22:40 ` Alistair Francis [this message] 2022-04-20 22:40 ` [PATCH v4 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses Alistair Francis
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