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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table
Date: Thu, 21 Apr 2022 12:18:27 +0100	[thread overview]
Message-ID: <20220421111846.2011565-13-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org>

The exynos4210 code currently has two very similar arrays of IRQs:

 * board_irqs is a field of the Exynos4210Irq struct which is filled
   in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
   for each IRQ the board/SoC can assert
 * irq_table is a set of qemu_irqs pointed to from the
   Exynos4210State struct.  It's allocated in exynos4210_init_irq,
   and the only behaviour these irqs have is that they pass on the
   level to the equivalent board_irqs[] irq

The extra indirection through irq_table is unnecessary, so coalesce
these into a single irq_table[] array as a direct field in
Exynos4210State which exynos4210_init_board_irqs() fills in.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  8 ++------
 hw/arm/exynos4210.c         |  6 +-----
 hw/intc/exynos4210_gic.c    | 32 ++++++++------------------------
 3 files changed, 11 insertions(+), 35 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index 923ce987627..a9f186370ee 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -83,7 +83,6 @@ typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
-    qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 } Exynos4210Irq;
 
 struct Exynos4210State {
@@ -92,7 +91,7 @@ struct Exynos4210State {
     /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
-    qemu_irq *irq_table;
+    qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 
     MemoryRegion chipid_mem;
     MemoryRegion iram_mem;
@@ -112,12 +111,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-/* Initialize exynos4210 IRQ subsystem stub */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
-
 /* Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210Irq *s);
+void exynos4210_init_board_irqs(Exynos4210State *s);
 
 /* Get IRQ number from exynos4210 IRQ subsystem stub.
  * To identify IRQ source use internal combiner group and bit number
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 60fc5a2ffe7..11e321d7830 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -228,10 +228,6 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
     }
 
-    /*** IRQs ***/
-
-    s->irq_table = exynos4210_init_irq(&s->irqs);
-
     /* IRQ Gate */
     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
@@ -296,7 +292,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
-    exynos4210_init_board_irqs(&s->irqs);
+    exynos4210_init_board_irqs(s);
 
     /*** Memory ***/
 
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index 794f6b5ac72..ec79b96f6d1 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -192,30 +192,14 @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-static void exynos4210_irq_handler(void *opaque, int irq, int level)
-{
-    Exynos4210Irq *s = (Exynos4210Irq *)opaque;
-
-    /* Bypass */
-    qemu_set_irq(s->board_irqs[irq], level);
-}
-
-/*
- * Initialize exynos4210 IRQ subsystem stub.
- */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
-{
-    return qemu_allocate_irqs(exynos4210_irq_handler, s,
-            EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
-}
-
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
  */
-void exynos4210_init_board_irqs(Exynos4210Irq *s)
+void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
+    Exynos4210Irq *is = &s->irqs;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -230,11 +214,11 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
             irq_id = EXT_GIC_ID_MCT_G1;
         }
         if (irq_id) {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_gic_irq[irq_id-32]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
         } else {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_combiner_irq[n]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@@ -245,8 +229,8 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
         if (irq_id) {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_gic_irq[irq_id-32]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
         }
     }
 }
-- 
2.25.1



  parent reply	other threads:[~2022-04-21 11:30 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-21 11:18 [PULL 00/31] target-arm queue Peter Maydell
2022-04-21 11:18 ` [PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF Peter Maydell
2022-04-21 11:18 ` [PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding Peter Maydell
2022-04-21 11:18 ` [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Peter Maydell
2022-04-21 11:18 ` [PULL 04/31] hw/arm: versal: Create an APU CPU Cluster Peter Maydell
2022-04-21 11:18 ` [PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs Peter Maydell
2022-04-21 11:18 ` [PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL Peter Maydell
2022-04-21 11:18 ` [PULL 07/31] hw/arm: versal: Connect the CRL Peter Maydell
2022-04-21 11:18 ` [PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device Peter Maydell
2022-04-21 11:18 ` [PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE Peter Maydell
2022-04-21 11:18 ` [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` Peter Maydell [this message]
2022-04-21 11:18 ` [PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] Peter Maydell
2022-04-21 11:18 ` [PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions Peter Maydell
2022-04-21 11:18 ` [PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines Peter Maydell
2022-04-21 11:18 ` [PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners Peter Maydell
2022-04-21 11:18 ` [PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs Peter Maydell
2022-04-21 11:18 ` [PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 24/31] hw/arm/exynos4210: Put combiners into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' Peter Maydell
2022-04-21 11:18 ` [PULL 27/31] hw/arm/stellaris: " Peter Maydell
2022-04-21 11:18 ` [PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function Peter Maydell
2022-04-21 11:18 ` [PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs Peter Maydell
2022-04-21 11:18 ` [PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module Peter Maydell
2022-04-21 11:18 ` [PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs Peter Maydell
2022-04-21 16:24 ` [PULL 00/31] target-arm queue Richard Henderson

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