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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
Date: Thu, 21 Apr 2022 12:18:37 +0100	[thread overview]
Message-ID: <20220421111846.2011565-23-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org>

The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
connect multiple IRQs up to the same external GIC input, which
is not permitted. We do the same thing in the code in
exynos4210_init_board_irqs() because the conditionals selecting
an irq_id in the first loop match multiple interrupt IDs.

Overall we do this for interrupt IDs
(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
and
(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1

These correspond to the cases for the multi-core timer that we are
wiring up to multiple inputs on the combiner in
exynos4210_combiner_get_gpioin().  That code already deals with all
these interrupt IDs being the same input source, so we don't need to
connect the external GIC interrupt for any of them except the first
(1, 4) and (1, 5). Remove the array entries and conditionals which
were incorrectly causing us to wire up extra lines.

This bug didn't cause any visible effects, because we only connect
up a device to the "primary" ID values (1, 4) and (1, 5), so the
extra lines would never be set to a level.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  2 +-
 hw/arm/exynos4210.c         | 12 +++++-------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index f58ee0f2686..7da3eddea5f 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -77,7 +77,7 @@
  * one for every non-zero entry in combiner_grp_to_gic_id[].
  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
  */
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
 
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 962d6d0ac2a..39e334e0773 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -231,7 +231,7 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     /* int combiner group 34 */
     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
     /* int combiner group 35 */
-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
     /* int combiner group 36 */
     { EXT_GIC_ID_MIXER },
     /* int combiner group 37 */
@@ -240,11 +240,11 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     /* groups 38-50 */
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
     /* int combiner group 51 */
-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { EXT_GIC_ID_MCT_L0 },
     /* group 52 */
     { },
     /* int combiner group 53 */
-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { EXT_GIC_ID_WDT },
     /* groups 54-63 */
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
 };
@@ -268,13 +268,11 @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
             /* MCT_G0 is passed to External GIC */
             irq_id = EXT_GIC_ID_MCT_G0;
         }
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
             /* MCT_G1 is passed to External and GIC */
             irq_id = EXT_GIC_ID_MCT_G1;
         }
-- 
2.25.1



  parent reply	other threads:[~2022-04-21 11:44 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-21 11:18 [PULL 00/31] target-arm queue Peter Maydell
2022-04-21 11:18 ` [PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF Peter Maydell
2022-04-21 11:18 ` [PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding Peter Maydell
2022-04-21 11:18 ` [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Peter Maydell
2022-04-21 11:18 ` [PULL 04/31] hw/arm: versal: Create an APU CPU Cluster Peter Maydell
2022-04-21 11:18 ` [PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs Peter Maydell
2022-04-21 11:18 ` [PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL Peter Maydell
2022-04-21 11:18 ` [PULL 07/31] hw/arm: versal: Connect the CRL Peter Maydell
2022-04-21 11:18 ` [PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device Peter Maydell
2022-04-21 11:18 ` [PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE Peter Maydell
2022-04-21 11:18 ` [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table Peter Maydell
2022-04-21 11:18 ` [PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] Peter Maydell
2022-04-21 11:18 ` [PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions Peter Maydell
2022-04-21 11:18 ` [PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines Peter Maydell
2022-04-21 11:18 ` [PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners Peter Maydell
2022-04-21 11:18 ` Peter Maydell [this message]
2022-04-21 11:18 ` [PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 24/31] hw/arm/exynos4210: Put combiners into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' Peter Maydell
2022-04-21 11:18 ` [PULL 27/31] hw/arm/stellaris: " Peter Maydell
2022-04-21 11:18 ` [PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function Peter Maydell
2022-04-21 11:18 ` [PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs Peter Maydell
2022-04-21 11:18 ` [PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module Peter Maydell
2022-04-21 11:18 ` [PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs Peter Maydell
2022-04-21 16:24 ` [PULL 00/31] target-arm queue Richard Henderson

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