From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module
Date: Thu, 21 Apr 2022 12:18:45 +0100 [thread overview]
Message-ID: <20220421111846.2011565-31-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org>
From: Hao Wu <wuhaotsh@google.com>
Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
index 13109d9d324..9419e0a7d2a 100644
--- a/include/hw/misc/npcm7xx_gcr.h
+++ b/include/hw/misc/npcm7xx_gcr.h
@@ -19,6 +19,36 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
+/*
+ * NPCM7XX PWRON STRAP bit fields
+ * 12: SPI0 powered by VSBV3 at 1.8V
+ * 11: System flash attached to BMC
+ * 10: BSP alternative pins.
+ * 9:8: Flash UART command route enabled.
+ * 7: Security enabled.
+ * 6: HI-Z state control.
+ * 5: ECC disabled.
+ * 4: Reserved
+ * 3: JTAG2 enabled.
+ * 2:0: CPU and DRAM clock frequency.
+ */
+#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12)
+#define NPCM7XX_PWRON_STRAP_SFAB BIT(11)
+#define NPCM7XX_PWRON_STRAP_BSPA BIT(10)
+#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8)
+#define FUP_NORM_UART2 3
+#define FUP_PROG_UART3 2
+#define FUP_PROG_UART2 1
+#define FUP_NORM_UART3 0
+#define NPCM7XX_PWRON_STRAP_SECEN BIT(7)
+#define NPCM7XX_PWRON_STRAP_HIZ BIT(6)
+#define NPCM7XX_PWRON_STRAP_ECC BIT(5)
+#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4)
+#define NPCM7XX_PWRON_STRAP_J2EN BIT(3)
+#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x)
+#define CKFRQ_SKIPINIT 0x000
+#define CKFRQ_DEFAULT 0x111
+
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
--
2.25.1
next prev parent reply other threads:[~2022-04-21 11:56 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 11:18 [PULL 00/31] target-arm queue Peter Maydell
2022-04-21 11:18 ` [PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF Peter Maydell
2022-04-21 11:18 ` [PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding Peter Maydell
2022-04-21 11:18 ` [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Peter Maydell
2022-04-21 11:18 ` [PULL 04/31] hw/arm: versal: Create an APU CPU Cluster Peter Maydell
2022-04-21 11:18 ` [PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs Peter Maydell
2022-04-21 11:18 ` [PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL Peter Maydell
2022-04-21 11:18 ` [PULL 07/31] hw/arm: versal: Connect the CRL Peter Maydell
2022-04-21 11:18 ` [PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device Peter Maydell
2022-04-21 11:18 ` [PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE Peter Maydell
2022-04-21 11:18 ` [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table Peter Maydell
2022-04-21 11:18 ` [PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] Peter Maydell
2022-04-21 11:18 ` [PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions Peter Maydell
2022-04-21 11:18 ` [PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines Peter Maydell
2022-04-21 11:18 ` [PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners Peter Maydell
2022-04-21 11:18 ` [PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs Peter Maydell
2022-04-21 11:18 ` [PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 24/31] hw/arm/exynos4210: Put combiners into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' Peter Maydell
2022-04-21 11:18 ` [PULL 27/31] hw/arm/stellaris: " Peter Maydell
2022-04-21 11:18 ` [PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function Peter Maydell
2022-04-21 11:18 ` [PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs Peter Maydell
2022-04-21 11:18 ` Peter Maydell [this message]
2022-04-21 11:18 ` [PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs Peter Maydell
2022-04-21 16:24 ` [PULL 00/31] target-arm queue Richard Henderson
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